DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15, in the reply filed on 2/17/26 is acknowledged.
Applicant's election with traverse of Species 1, figure 2, in the reply filed on 2/17/26 is acknowledged. The traversal is on the ground(s) that there is no serious burden. This is not found persuasive because, as noted in the restriction, they are different is design. Figure 2 is a flat metal stack and figure 3C is a metal stack in an opening.
The requirement is still deemed proper and is therefore made FINAL.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Double Rejection over U.S. Patent No. 12,022,650
Claims 1-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,022,650, hereafter referred to as the patent. Although the claims at issue are not identical, they are not patentably distinct from each other because these claims are broader.
Regarding claim 1, the patent claims a method of depositing a metal stack, the method comprising:
depositing a tungsten (W) layer on a semiconductor substrate (column 16, lines 61-64); and
depositing a molybdenum (Mo) layer on the tungsten (W) layer to form the metal stack (column 17, lines 1-2), the tungsten (W) layer having a thickness in a range of from 5 A to 30 A (claim 4) and the molybdenum (Mo) layer having a thickness in a range of from 80 A to 200 A (claim 10).
With respect to claim 2, the patent claims the thickness of the tungsten (W) layer is in a range of from 15 A to 25 A (claim 4) and the thickness of the molybdenum (Mo) layer is in a range of from 100 A to 150 A (claim 10).
As to claim 3, though the patent fails to claim performed in situ in an integrated processing tool, it would have been obvious to one of ordinary skill in the art at the time of the invention to perform it in situ in an integrated process tool in the invention of the patent because in situ integrated process tools are conventionally known and used in the art. In situ integrated process tools are used because they provide control over parameters and process conditions. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In re claim 4, though the patent fails to claim the semiconductor substrate comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), tungsten silicide (WSi), or tungsten silicon nitride (WSiN), it would have been obvious to one of ordinary skill in the art at the time of the invention to use one of these substrates in the invention of the patent because they are conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Concerning claim 5, the patent (claim 3) claims the semiconductor substrate is maintained at a temperature in a range of from 200 °C to 400 C.
Pertaining to claim 6, the patent claims one or more of the tungsten (W) layer or the molybdenum (Mo) layer is deposited using a direct current (DC) PVD process or a radiofrequency (RF) PVD process (column 16, lines 61-62).
In claim 7, the patent (claim 12) claims the metal stack has a resistivity of less than or equal to 10 when the metal stack has a total thickness of 140 A.
Regarding claim 8, though the patent fails to claim performing a thermal treatment ex situ after depositing the metal stack, it would have been obvious to one of ordinary skill in the art at the time of the invention to perform a thermal treatment in the invention of the patent because a thermal treatment can be used to harden the metal stack, for example. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
With respect to claim 9, the patent (claim 12) claims the metal stack has a resistivity of less than or equal to 11 after the thermal treatment when the metal stack has a total thickness of 140 A.
Claims 10-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,022,650, in view of Thombare et al., US 10,510,590.
As to claim 10, the patent claims a method of depositing a metal stack, the method comprising:
depositing a tungsten (W) layer on a semiconductor substrate (column 16, lines 61-64);
depositing a molybdenum (Mo) layer on the tungsten (W) layer to form the metal stack (column 17, lines 1-2), depositing the tungsten (W) layer and the molybdenum (Mo) layer where the semiconductor substrate is maintained at a temperature in a range of from 200 °C to 400 °C (claims 3 & 11) the tungsten (W) layer having a thickness in a range of from 5 A to 30 A (claim 4) and the molybdenum (Mo) layer having a thickness in a range of from 80 A to 200 A (claim 10).
The patent fails to claim the process is performed in situ in an integrated processing tool.
It would have been obvious to one of ordinary skill in the art at the time of the invention to perform it in situ in an integrated process tool in the invention of the patent because in situ integrated process tools are conventionally known and used in the art. In situ integrated process tools are used because they provide control over parameters and process conditions. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
The patent fails to claim performing a thermal treatment ex situ after depositing the metal stack.
Thombare (column 13, lines 1-19) teaches performing a thermal treatment (annealing) ex situ (column 13, lines 7 & 12-13 teaches using a furnace, and also teaches exposing to air, therefore being ex situ) after depositing the metal stack.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use a thermal treatment in the invention of Thombare in the invention of the patent because Thombare teaches it improves grain growth and lowers resistivity (column 13, lines 1-5).
In re claim 110, the patent (claim 4) claims the thickness of the tungsten (W) layer is in a range of from 15 A to 25 A and the thickness of the molybdenum (Mo) layer is in a range of from 100 A to 150 A (claim 10).
Concerning claim 12, though the patent fails to claim the semiconductor substrate comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), tungsten silicide (WSi), or tungsten silicon nitride (WSiN), it would have been obvious to one of ordinary skill in the art at the time of the invention to use one of these substrates in the invention of the patent because they are conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Pertaining to claim 13, the patent (column 16, lines 61-62) claims one or more of the tungsten (W) layer or the molybdenum (Mo) layer is deposited using a direct current (DC) PVD process or a radiofrequency (RF) PVD process.
In claim 14, the patent (claim 12) claims the metal stack has a resistivity of less than or equal to 10 [p0-cm prior to the thermal treatment when the metal stack has a total thickness of 140 A.
Regarding claim 15, the patent (claim 12) claims the metal stack has a resistivity of less than or equal to 11 [p0-cm after the thermal treatment when the metal stack has a total thickness of 140 A.
Double Rejection over US 11,587,936
Claims 1-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,587,936, hereafter referred to as the patent. Although the claims at issue are not identical, they are not patentably distinct from each other because these claims are broader.
Regarding claim 1, the patent claims a method of depositing a metal stack, the method comprising:
depositing a tungsten (W) layer on a semiconductor substrate (column 16, lines 57 & claim 2); and
depositing a molybdenum (Mo) layer on the tungsten (W) layer to form the metal stack (column 16, lines 62-63), the tungsten (W) layer having a thickness in a range of from 5 A to 30 A (claim 7) and the molybdenum (Mo) layer having a thickness in a range of from 80 A to 200 A (claim 14).
With respect to claim 2, the patent claims the thickness of the tungsten (W) layer is in a range of from 15 A to 25 A (claim 7) and the thickness of the molybdenum (Mo) layer is in a range of from 100 A to 150 A (claim 14).
As to claim 3, though the patent fails to claim performed in situ in an integrated processing tool, it would have been obvious to one of ordinary skill in the art at the time of the invention to perform it in situ in an integrated process tool in the invention of the patent because in situ integrated process tools are conventionally known and used in the art. In situ integrated process tools are used because they provide control over parameters and process conditions. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In re claim 4, though the patent, which claims a gate oxide layer (column 16, lines 58-61), fails to claim the semiconductor substrate comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), tungsten silicide (WSi), or tungsten silicon nitride (WSiN), it would have been obvious to one of ordinary skill in the art at the time of the invention to use one of these in the invention of the patent because at least SiOx, SiN are conventionally known and used gate oxide layers. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Concerning claim 5, the patent (claims 6 & 15) claims the semiconductor substrate is maintained at a temperature in a range of from 200 °C to 400 C.
Pertaining to claim 6, the patent (column 16, lines 57-58) claims one or more of the tungsten (W) layer or the molybdenum (Mo) layer is deposited using a direct current (DC) PVD process or a radiofrequency (RF) PVD process.
In claim 7, the patent (claim 16) claims the metal stack has a resistivity of less than or equal to 10 when the metal stack has a total thickness of 140 A.
Regarding claim 8, though the patent fails to claim performing a thermal treatment ex situ after depositing the metal stack, it would have been obvious to one of ordinary skill in the art at the time of the invention to perform a thermal treatment in the invention of the patent because a thermal treatment can be used to harden the metal stack, for example. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
With respect to claim 9, the patent (claim 16) claims the metal stack has a resistivity of less than or equal to 11 after the thermal treatment when the metal stack has a total thickness of 140 A.
Claims 10-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,587,936, in view of Thombare et al., US 10,510,590.
As to claim 10, the patent claims a method of depositing a metal stack, the method comprising:
depositing a tungsten (W) layer on a semiconductor substrate (column 16, lines 57-58 & claim 2);
depositing a molybdenum (Mo) layer on the tungsten (W) layer to form the metal stack (column 16, lines 62-63), where the semiconductor substrate is maintained at a temperature in a range of from 200 °C to 400 °C (claims 6 & 15) the tungsten (W) layer having a thickness in a range of from 5 A to 30 A (claim 7) and the molybdenum (Mo) layer having a thickness in a range of from 80 A to 200 A (claim 14).
The patent fails to claim depositing the tungsten (W) layer and the molybdenum (Mo) layer performed in situ in an integrated processing tool
It would have been obvious to one of ordinary skill in the art at the time of the invention to perform it in situ in an integrated process tool in the invention of the patent because in situ integrated process tools are conventionally known and used in the art. In situ integrated process tools are used because they provide control over parameters and process conditions. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
The patent fails to claim performing a thermal treatment ex situ after depositing the metal stack.
Thombare (column 13, lines 1-19) teaches performing a thermal treatment (annealing) ex situ (column 13, lines 7 & 12-13 teaches using a furnace, and also teaches exposing to air, therefore being ex situ) after depositing the metal stack.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use a thermal treatment in the invention of Thombare in the invention of the patent because Thombare teaches it improves grain growth and lowers resistivity (column 13, lines 1-5).
In re claim 11, the patent claims the thickness of the tungsten (W) layer is in a range of from 15 A to 25 A (claim 7) and the thickness of the molybdenum (Mo) layer is in a range of from 100 A to 150 A (claim 14).
Concerning claim 12, though the patent, which claims a gate oxide layer (column 16, lines 58-61), fails to claim the semiconductor substrate comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), tungsten silicide (WSi), or tungsten silicon nitride (WSiN), it would have been obvious to one of ordinary skill in the art at the time of the invention to use one of these in the invention of the patent because at least SiOx, SiN are conventionally known and used gate oxide layers. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Pertaining to claim 13, the patent (column 16, lines 57-58) claims one or more of the tungsten (W) layer or the molybdenum (Mo) layer is deposited using a direct current (DC) PVD process or a radiofrequency (RF) PVD process.
In claim 14, the patent (claim 16) claims the metal stack has a resistivity of less than or equal to 10 [p0-cm prior to the thermal treatment when the metal stack has a total thickness of 140 A.
Regarding claim 15, the patent (claim 16) claims the metal stack has a resistivity of less than or equal to 11 [p0-cm after the thermal treatment when the metal stack has a total thickness of 140 A.
Double Rejection over US 12,453,086
Claims 1-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of U.S. Patent No. 12,453,086, hereafter referred to as the patent. Although the claims at issue are not identical, they are not patentably distinct from each other because these claims are broader.
With respect to claim 1, the patent claims a method of depositing a metal stack, the method comprising:
depositing a tungsten (W) layer on a semiconductor substrate (column 14, lines 8-10); and
depositing a molybdenum (Mo) layer on the tungsten (W) layer to form the metal stack (column 14, lines 11-12), the tungsten (W) layer having a thickness in a range of from 5 A to 30 A (claim 3) and the molybdenum (Mo) layer having a thickness in a range of from 80 A to 200 A (claim 10).
As to claim 2, the patent claims the thickness of the tungsten (W) layer is in a range of from 15 A to 25 A (claim 3) and the thickness of the molybdenum (Mo) layer is in a range of from 100 A to 150 A (claim 10).
In re claim 3, though the patent fails to claim the process is performed in situ in an integrated processing tool, it would have been obvious to one of ordinary skill in the art at the time of the invention to perform it in situ in an integrated process tool in the invention of the patent because in situ integrated process tools are conventionally known and used in the art. In situ integrated process tools are used because they provide control over parameters and process conditions. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Concerning claim 4, though the patent, which claims a gate dielectric, fails to claim the semiconductor substrate comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), tungsten silicide (WSi), or tungsten silicon nitride (WSiN), it would have been obvious to one of ordinary skill in the art at the time of the invention to use one of these in the invention of the patent because at least SiOx, SiN are conventionally known and used gate oxide layers. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Pertaining to claim 5, the patent (claims 2 & 11) claim the semiconductor substrate is maintained at a temperature in a range of from 200 °C to 400 C.
In claim 6, the patent (column 14, lines 8-10) claims one or more of the tungsten (W) layer or the molybdenum (Mo) layer is deposited using a direct current (DC) PVD process or a radiofrequency (RF) PVD process.
Regarding claim 7, the patent (claim 12) claims the metal stack has a resistivity of less than or equal to 10 when the metal stack has a total thickness of 140 A.
With respect to claim 8, further comprising performing a thermal treatment ex situ after depositing the metal stack, it would have been obvious to one of ordinary skill in the art at the time of the invention to perform a thermal treatment in the invention of the patent because a thermal treatment can be used to harden the metal stack, for example. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
As to claim 9, the patent (claim 12) claims the metal stack has a resistivity of less than or equal to 11 after the thermal treatment when the metal stack has a total thickness of 140 A.
Claims 10-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of U.S. Patent No. 12,453,086, in view of Thombare et al., US 10,510,590.
In re claim 10, the patent claims a method of depositing a metal stack, the method comprising:
depositing a tungsten (W) layer on a semiconductor substrate (column 14, liens 8-10);
depositing a molybdenum (Mo) layer on the tungsten (W) layer to form the metal stack (column 14, lines 11-12), depositing the tungsten (W) layer and the molybdenum (Mo) where the semiconductor substrate is maintained at a temperature in a range of from 200 °C to 400 °C (claims 2 & 11) the tungsten (W) layer having a thickness in a range of from 5 A to 30 A (claim 3) and the molybdenum (Mo) layer having a thickness in a range of from 80 A to 200 A (claim 10).
It would have been obvious to one of ordinary skill in the art at the time of the invention to perform it in situ in an integrated process tool in the invention of the patent because in situ integrated process tools are conventionally known and used in the art. In situ integrated process tools are used because they provide control over parameters and process conditions. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
The patent fails to claim performing a thermal treatment ex situ after depositing the metal stack.
Thombare (column 13, lines 1-19) teaches performing a thermal treatment (annealing) ex situ (column 13, lines 7 & 12-13 teaches using a furnace, and also teaches exposing to air, therefore being ex situ) after depositing the metal stack.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use a thermal treatment in the invention of Thombare in the invention of the patent because Thombare teaches it improves grain growth and lowers resistivity (column 13, lines 1-5).
Concerning claim 11, the patent claims the thickness of the tungsten (W) layer is in a range of from 15 A to 25 A (claim 3) and the thickness of the molybdenum (Mo) layer is in a range of from 100 A to 150 A (claim 10).
Pertaining to claim 12, though the patent, which claims a gate dielectric (column 14, lines 11-15) fails to claim the semiconductor substrate comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), tungsten silicide (WSi), or tungsten silicon nitride (WSiN), it would have been obvious to one of ordinary skill in the art at the time of the invention to use one of these in the invention of the patent because at least SiOx, SiN are conventionally known and used gate oxide layers. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In claim 13, the patent (column 14, lines 8-10) claims one or more of the tungsten (W) layer or the molybdenum (Mo) layer is deposited using a direct current (DC) PVD process or a radiofrequency (RF) PVD process.
Regarding claim 14, the patent (claim 12) claims the metal stack has a resistivity of less than or equal to 10 [p0-cm prior to the thermal treatment when the metal stack has a total thickness of 140 A.
With respect to claim 15, the patent (claim 12) claims the metal stack has a resistivity of less than or equal to 11 [p0-cm after the thermal treatment when the metal stack has a total thickness of 140 A.
Double Rejection over US 2024/0145300
Claims 1-9 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 2024/0145300, hereafter referred to as the reference application. Although the claims at issue are not identical, they are not patentably distinct from each other because these claims are broader.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Regarding claim 1, the reference application claims a method of depositing a metal stack, the method comprising:
depositing a tungsten (W) layer on a semiconductor substrate (claim 1, line 2 & claim 4); and
depositing a molybdenum (Mo) layer on the tungsten (W) layer to form the metal stack (claim 1, line 11 & claim 4), the tungsten (W) layer having a thickness in a range of from 5 A to 30 A (claim 5) and the molybdenum (Mo) layer having a thickness in a range of from 80 A to 200 A (claim 6).
With respect to claim 2, the reference application claims the thickness of the tungsten (W) layer is in a range of from 15 A to 25 A (claim 5) and the thickness of the molybdenum (Mo) layer is in a range of from 100 A to 150 A (claim 6).
As to claim 3, the reference application (claim 7) claims performed in situ in an integrated processing tool.
In re claim 4, the reference application, which claims a dielectric layer (claim 1, lines 2-3), fails to claim the semiconductor substrate comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), tungsten silicide (WSi), or tungsten silicon nitride (WSiN), it would have been obvious to one of ordinary skill in the art at the time of the invention to use these materials because at least SiOx and SiN are conventionally known dielectric materials. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Concerning claim 5, though the reference application fails to claim the semiconductor substrate is maintained at a temperature in a range of from 200 °C to 400 C, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the temperature through routine experimentation (MPEP 2144.05).
Pertaining to claim 6, the reference application (claim 1, lines 4 & 12) claims one or more of the tungsten (W) layer or the molybdenum (Mo) layer is deposited using a direct current (DC) PVD process or a radiofrequency (RF) PVD process.
In claim 7, though the reference application fails to claim the metal stack has a resistivity of less than or equal to 10 when the metal stack has a total thickness of 140 A, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the resistivity through routine experimentation (MPEP 2144.05).
Regarding claim 8, though the reference application performing a thermal treatment ex situ after depositing the metal stack, it would have been obvious to one of ordinary skill in the art at the time of the invention to perform a thermal treatment in the invention of the reference application because a thermal treatment can be used to harden the metal stack, for example. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
With respect to claim 9, the reference application the metal stack has a resistivity of less than or equal to 11 after the thermal treatment when the metal stack has a total thickness of 140 A, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the resistivity through routine experimentation (MPEP 2144.05).
Claims 10-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 2024/0145300, in view of Thombare et al., 10,510,590.
As to claim 10, the reference application claims a method of depositing a metal stack, the method comprising:
depositing a tungsten (W) layer on a semiconductor substrate (claim 1, line 2 & claim 4);
depositing a molybdenum (Mo) layer on the tungsten (W) layer to form the metal stack (claim 1, line 11 & claim 4), depositing the tungsten (W) layer and the molybdenum (Mo) layer performed in situ in an integrated processing tool (claim 7) having a thickness in a range of from 5 A to 30 A (claim 5) and the molybdenum (Mo) layer having a thickness in a range of from 80 A to 200 A (claim 6).
The reference application fails to claim the semiconductor substrate is maintained at a temperature in a range of from 200 °C to 400 °C the tungsten (W) layer
It would have been obvious to one ordinary skill in the art at the time of the invention to optimize the temperature through routine experimentation (MPEP 2144.05).
The reference application fails to claim forming a thermal treatment ex situ after depositing the metal stack.
Thombare (column 13, lines 1-19) teaches performing a thermal treatment (annealing) ex situ (column 13, lines 7 & 12-13 teaches using a furnace, and also teaches exposing to air, therefore being ex situ) after depositing the metal stack.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use a thermal treatment in the invention of Thombare in the invention of the reference application because Thombare teaches it improves grain growth and lowers resistivity (column 13, lines 1-5).
In re claim 11, the reference application the thickness of the tungsten (W) layer is in a range of from 15 A to 25 A (claim 5) and the thickness of the molybdenum (Mo) layer is in a range of from 100 A to 150 A (claim 6).
Concerning claim 12, the reference application, which claims a dielectric layer (claim 1, lines 2-3), fails to claim the semiconductor substrate comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), tungsten silicide (WSi), or tungsten silicon nitride (WSiN), it would have been obvious to one of ordinary skill in the art at the time of the invention to use these materials because at least SiOx and SiN are conventionally known dielectric materials. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Pertaining to claim 13, the reference application (claim 1, lines 4 & 12) claims one or more of the tungsten (W) layer or the molybdenum (Mo) layer is deposited using a direct current (DC) PVD process or a radiofrequency (RF) PVD process.
In claim 14, the reference application the metal stack has a resistivity of less than or equal to 10 [p0-cm prior to the thermal treatment when the metal stack has a total thickness of 140 A it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the resistivity through routine experimentation (MPEP 2144.05).
Regarding claim 15, the reference application the metal stack has a resistivity of less than or equal to 11 [p0-cm after the thermal treatment when the metal stack has a total thickness of 140 A. it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the resistivity through routine experimentation (MPEP 2144.05).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Schloss et al., US 12,598,925.
Regarding claim 1, Schloss (figure 1A) teaches a method of depositing a metal stack, the method comprising:
depositing a tungsten (W) layer 108 (column 9, lines 31-34 states tungsten oxynitride or WN) on a semiconductor substrate 102/104; and
depositing a molybdenum (Mo) (column 9, lines 17-21) layer 110 on the tungsten (W) layer 108 to form the metal stack), the tungsten (W) layer having a thickness in a range of from 5 A to 30 A (column 9, lines 47-48) and the molybdenum (Mo) layer having a thickness in a range of from 80 A to 200 A (column 9, lines 49-50).
With respect to claim 2, Schloss teaches the thickness of the tungsten (W) layer is in a range of from 15 A to 25 A (column 9, lines 47-48) and the thickness of the molybdenum (Mo) layer is in a range of from 100 A to 150 A (column 9, lines 49-50).
As to claim 3, Schloss (figure 6) teaches performed in situ in an integrated processing tool.
In re claim 4, Schloss (column 8, lines 4-12) teaches the semiconductor substrate comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), tungsten silicide (WSi), or tungsten silicon nitride (WSiN).
Concerning claim 5, Schloss (column 22, lines 22-34) teaches the semiconductor substrate is maintained at a temperature in a range of from 200 °C to 400 C.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schloss et al., US 12,598,925, as applied to claim 1 above.
Pertaining to claim 6, though Schloss fails to teach one or more of the tungsten (W) layer or the molybdenum (Mo) layer is deposited using a direct current (DC) PVD process or a radiofrequency (RF) PVD process, it would have been obvious to one of ordinary skill in the art at the time of the invention to use DC PVD or RF PVD in the invention of Schloss because they are conventionally known and used deposition methods. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In claim 7, though Schloss, which teaches achieving low resistivities (abstract), fails to teach the metal stack has a resistivity of less than or equal to 10 when the metal stack has a total thickness of 140 A, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the resistivity through routine experimentation (MPEP 2144.05).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schloss et al., US 12,598,925, as applied to claim 1 above, and further in view of Thombare et al., US 10,510,590.
Regarding claim 8, Schloss fails to teach performing a thermal treatment ex situ after depositing the metal stack.
Thombare (column 13, lines 1-19) teaches performing a thermal treatment (annealing) ex situ (column 13, lines 7 & 12-13 teaches using a furnace, and also teaches exposing to air, therefore being ex situ) after depositing the metal stack.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use a thermal treatment in the invention of Thombare in the invention of Schloss because Thombare teaches it improves grain growth and lowers resistivity (column 13, lines 1-5).
With respect to claim 9, though Schloss fails to teach the metal stack has a resistivity of less than or equal to 11 after the thermal treatment when the metal stack has a total thickness of 140 A, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the resistivity through routine experimentation (MPEP 2144.05).
Claim(s) 10-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schloss et al., US 12,598,925, in view of Thombare et al., US 10,510,590.
As to claim 10, Schloss (figure 1A) teaches a method of depositing a metal stack, the method comprising:
depositing a tungsten (W) (column 9, lines 31-34 states tungsten oxynitride or WN) layer 108 on a semiconductor substrate 102/104;
depositing a molybdenum (Mo) layer 110 on the tungsten (W) layer to form the metal stack (column 9, lines 17-21), depositing the tungsten (W) layer and the molybdenum (Mo) layer performed in situ in an integrated processing tool (figure 6) where the semiconductor substrate is maintained at a temperature in a range of from 200 °C to 400 °C (column 22, lines 22-34) the tungsten (W) layer having a thickness in a range of from 5 A to 30 A (column 9, lines 47-48) and the molybdenum (Mo) layer having a thickness in a range of from 80 A to 200 A (column 9, lines 49-50).
Schloss fails to teach performing a thermal treatment ex situ after depositing the metal stack.
Thombare (column 13, lines 1-19) teaches performing a thermal treatment (annealing) ex situ (column 13, lines 7 & 12-13 teaches using a furnace, and also teaches exposing to air, therefore being ex situ) after depositing the metal stack.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use a thermal treatment in the invention of Thombare in the invention of Schloss because Thombare teaches it improves grain growth and lowers resistivity (column 13, lines 1-5).
In re claim 11, wherein the thickness of the tungsten (W) layer is in a range of from 15 A to 25 A (column 9, lines 47-48) and the thickness of the molybdenum (Mo) layer is in a range of from 100 A to 150 A (column 9, lines 49-50).
Concerning claim 12, Schloss (column 8, lines 4-12) teaches the semiconductor substrate comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), tungsten silicide (WSi), or tungsten silicon nitride (WSiN).
Pertaining to claim 13, though Schloss fails to teach one or more of the tungsten (W) layer or the molybdenum (Mo) layer is deposited using a direct current (DC) PVD process or a radiofrequency (RF) PVD process, it would have been obvious to one of ordinary skill in the art at the time of the invention to use DC PVD or RF PVD in the invention of Schloss because they are conventionally known and used deposition methods. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In claim 14, though Schloss fails to teach the metal stack has a resistivity of less than or equal to 10 [p0-cm prior to the thermal treatment when the metal stack has a total thickness of 140 A, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the resistivity through routine experimentation (MPEP 2144.05).
Regarding claim 15, wherein the metal stack has a resistivity of less than or equal to 11 [p0-cm after the thermal treatment when the metal stack has a total thickness of 140 A, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the resistivity through routine experimentation (MPEP 2144.05).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art teaches various aspects of the invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
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/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 4/30/26
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