DETAILED ACTION
This correspondence is in response to the communications received 01/23/2026. Claims 11-20 have been amended. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 in the reply filed on 01/23/2026 is acknowledged.
Claims 11-20 would be withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, however, claims 11-20 were amended so as to now be of the elected group. Therefore, no claims are withdrawn. Election was made without traverse in the reply filed on 01/23/2026.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/14/2025 and 12/05/2025 have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the turns of the copper inductor coil" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 8, a method of forming a radio frequency (RF) inductor device (6), the method comprising:
forming semiconductor devices (32) on a semiconductor wafer (30);
after forming the semiconductor devices, forming an interconnect structure comprising a plurality of patterned metallization layers (34) spaced apart by dielectric material (36) on the semiconductor wafer (see Fig. 3); and
forming a copper inductor coil (10) on the interconnect structure by plating, wherein the copper inductor coil comprises textured copper having at least 90% (111) orientation and wherein the copper inductor coil is electrically connected with at least one patterned metallization layer of the interconnect structure (see Fig. 3, 10 is electrically connected with at least one of 34 via "electrical vias 44").
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kuwajima et al. (US 10,886,213 B2) in view of Uzoh (US 11,244,920 B2).
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Regarding claim 1, Figs. 26-32 of Kuwajima disclose a method of forming a radio frequency (RF) inductor device (see patent summary) including the method comprising:
forming an insulator layer (“interlayer insulation film IL7 having the opening part in the pad region and configured using a lamination film of the insulation film IL7a and the insulation film IL7b is formed”, col. 15, lines 15-19); and
forming a copper inductor coil on the insulator layer by plating (“Next, as shown in FIG. 30, the re-wiring (not shown) and the coil (inductor) CL are formed on the insulation film IL7b including the pad region (not shown). The re-wiring (not shown) and the coil (inductor) CL are formed by growing a Cu film (copper film) by, for example, the electrolytic plating method”, col. 15, lines 20-25).
Kuwajima fails to disclose “wherein the copper inductor coil comprises textured copper having at least 90% (111) orientation.”
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Fig. 2 of Uzoh teaches wherein the copper inductor coil comprises textured copper having at least 90% (111) orientation (“a conductive layer 206 that is several microns thick is formed over the seed layer 204 and fills the cavity 202 to form the conductive features 110 or 110′. For example, the conductive layer 206 may comprise copper or a copper alloy, for example, and may be formed using a plating bath, such as an acid bath, or the like”, col 6, lines 51-56, where “a conductive feature 110, 110′, or 110″ having a very low concentration of impurities (or substantially no impurities) may have a texture with a high percentage (e.g., >97%) of {111} oriented grains”, col. 13, lines 18-21, thus CL of Kuwajima can be formed of textured copper having at least 90% (111) orientation).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the copper inductor coil comprises textured copper having at least 90% (111) orientation” as taught by Uzoh in the system of Kuwajima for the purpose of minimizing thermal damage to rest of the RF inductor device structure by utilizing a relatively low temperature metal formation process.
Regarding claim 2, Figs. 26-32 of Kuwajima in combination with Fig. 2 of Uzoh disclose the method of claim 1, Fig. 2 of Uzoh further discloses wherein the copper inductor coil comprises textured copper having at least 97% (111) orientation (as discussed previously, 110 may have a texture of >97% {111} oriented grains).
Regarding claim 6, Figs. 26-32 of Kuwajima in combination with Fig. 2 of Uzoh disclose the method of claim 1.
Figs. 26-32 of Kuwajima in combination with Uzoh fail to specify “wherein the turns of the copper inductor coil are rectangular or octagonal”
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However, in a similar field of endeavor, Fig. 2 of Kuwajima teaches wherein the turns of the copper inductor coil are rectangular or octagonal (as seen in Fig. 2, the turns of “coil (spiral inductor) CL”, col. 5, line 20, are octagonal).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the turns of the copper inductor coil are rectangular or octagonal” as taught by Fig. 2 of Kuwajima in the system of Figs. 26-32 of Kuwajima in combination with Uzoh for the purpose of showing the arrangement of the inductor coil in the plan view.
Regarding claim 8, Figs. 26-32 of Kuwajima disclose a method of forming a radio frequency (RF) inductor device (see patent summary) including the method comprising:
forming semiconductor devices (“The semiconductor substrate SUB has the region MCA in which the MOM capacitance element configuring the loop filter LPF is formed, the region MTA in which the MOS transistor MT configuring the LC-VCO circuit is formed, and the region BTA in which the MOS varactor BT configuring the LC-VCO circuit is formed”, col. 13, lines 31-36) on a semiconductor wafer (“the wafer-like semiconductor substrate SUB is diced for each chip region to be divided (fragmented) into a plurality of semiconductor chips”, col. 15, lines 30-32);
after forming the semiconductor devices (as seen in Fig. 30, the following elements are on MOM, MT, and BT and are therefore formed afterwards), forming an interconnect structure (together “plugs P1-P6” and “wirings M1-M6”, both seen in Fig. 30 form an interconnect structure), comprising a plurality of patterned metallization layers (“wirings M1-M6” are patterned metallization layers where “the wirings M1 configured using a conductive film are formed on the plug P1”, col. 14, lines 43-44, “an aluminum film as a conductive film is deposited on the plug P2, and then is patterned to form the wirings M2”, col. 14, lines 58-60, and “by repeating the formation steps of the interlayer insulation film, the wirings (M3 to M6) are formed”, col. 14, lines 64-67) spaced apart by dielectric material (“interlayer insulation films IL1-IL6” are a dielectric material, where “an interlayer insulation film IL1 is formed on the main surface (entire main surface) of the semiconductor substrate SUB”, col. 14, lines 25-27, “an interlayer insulation film IL2 is formed on the wirings M1. For example, an oxide silicon film is deposited on the wirings M1 by the CVD method and the like”, col. 14, lines 52-55, and silicon oxide is known in the art as a dielectric material, thus as seen in Fig. 30, M1-M6 are spaced apart by the dielectric material IL1-IL6) on the semiconductor wafer (as seen in Fig. 30, M1-M6 are on SUB); and
forming a copper inductor coil on the interconnect structure by plating (“Next, as shown in FIG. 30, the re-wiring (not shown) and the coil (inductor) CL are formed on the insulation film IL7b including the pad region (not shown). The re-wiring (not shown) and the coil (inductor) CL are formed by growing a Cu film (copper film) by, for example, the electrolytic plating method”, col. 15, lines 20-25, and as seen in Fig. 30 CL are formed on P1-P6 and M1-M6).
Kuwajima fails to disclose “wherein the copper inductor coil comprises textured copper having at least 90% (111) orientation and wherein the copper inductor coil is electrically connected with at least one patterned metallization layer of the interconnect structure.”
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Fig. 2 of Uzoh teaches wherein the copper inductor coil comprises textured copper having at least 90% (111) orientation (“a conductive layer 206 that is several microns thick is formed over the seed layer 204 and fills the cavity 202 to form the conductive features 110 or 110′. For example, the conductive layer 206 may comprise copper or a copper alloy, for example, and may be formed using a plating bath, such as an acid bath, or the like”, col 6, lines 51-56, where “a conductive feature 110, 110′, or 110″ having a very low concentration of impurities (or substantially no impurities) may have a texture with a high percentage (e.g., >97%) of {111} oriented grains”, col. 13, lines 18-21, thus CL of Kuwajima can be formed of textured copper having at least 90% (111) orientation).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the copper inductor coil comprises textured copper having at least 90% (111) orientation” as taught by Uzoh in the system of Kuwajima for the purpose of minimizing thermal damage to rest of the RF inductor device structure by utilizing a relatively low temperature metal formation process.
Figs. 26-32 of Kuwajima in combination with Uzoh fail to specify “wherein the copper inductor coil is electrically connected with at least one patterned metallization layer of the interconnect structure”.
However, in a similar field of endeavor, Fig. 2 of Kuwajima teaches wherein the copper inductor coil is electrically connected with at least one patterned metallization layer of the plurality of patterned metallization layers (“The coil (spiral inductor) CL shown in FIG. 2A is provided in a re-wiring layer, and is configured using a spiral wiring. Here, single winding of the coil CL is formed in an octagon shape. Pad parts PD are provided at both ends of the coil CL. Plugs are provided under the pad parts PD, and the pad parts PD are coupled to wirings (for example, sixth wirings M6) just below the pad parts PD through the plugs”, col. 5, lines 23-29).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the copper inductor coil is electrically connected with at least one patterned metallization layer of the plurality of patterned metallization layers” as taught by Fig. 2 of Kuwajima in the system of Figs. 26-32 of Kuwajima in combination with Uzoh for the purpose of providing electrical connections to the inductor coil in order to operate the coil.
Regarding claim 9, Figs. 26-32 of Kuwajima in combination with Fig. 2 of Uzoh disclose the method of claim 8, Fig. 2 of Uzoh further discloses wherein the copper inductor coil comprises textured copper having at least 97% (111) orientation (as discussed previously, 110 may have a texture of >97% {111} oriented grains).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kuwajima et al. (US 10,886,213 B2) in view of Uzoh (US 11,244,920 B2) in view of Lee et al. (US 20240030128 A1).
Regarding claim 3, Figs. 26-32 of Kuwajima in combination with Fig. 2 of Uzoh disclose the method of claim 1.
Kuwajima in combination with Uzoh fails to discloses “depositing an insulating coating over the copper inductor coil.”
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However, in a similar field of endeavor, Fig. 5 of Lee teaches depositing an insulating coating over the copper inductor coil (“A protective layer 600 covering at least a part of the redistribution conductive layer 510 may be formed on the redistribution insulating layer 500. In some embodiments, the protective layer 600 may include a lower protective layer 610 and an upper protective layer 620”, [0126], here, 610 is interpreted as the insulating coating, where “The portion of the redistribution conductive layer 510 which covers the upper surface of the redistribution insulating layer 500 may be a connection pad OPD, the redistribution line RDLM, the first inductor redistribution line RDLI1, the second inductor redistribution line RDLI2, or the third inductor redistribution line RDLI3”, [0121], thus RDLI1, RDLI2, and RDLI3 of Lee are the equivalent inductor coil to structure to CL of Kuwajima, further, “lower protective layer 610 may include silicon nitride, and the upper protective layer 620 may be formed of photosensitive polyimide (PSPI), photo imageable dielectric (PID), epoxy, or polyimide”, [0030], thus as silicon nitride is known in the art as an insulating material, 610 is an insulating coating).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “depositing an insulating coating over the copper inductor coil” as taught by Yang in the system of Kuwajima in combination with Uzoh for the purpose of protecting the inductor coil structure and providing additional insulation.
Regarding claim 4, Figs. 26-32 of Kuwajima in combination with Fig. 2 of Uzoh and Fig. 5 of Lee disclose the method of claim 1, Figs. 26-32 of Kuwajima further disclose further comprising:
after depositing the insulating coating, encapsulating the copper inductor coil in polyimide (“a photosensitive polyimide film as an insulation film (protection film) PRO is formed on the re-wiring (not shown), the coil (inductor) CL, and the interlayer insulation film IL7”, col. 15, lines 26-29, (PRO of Kuwajima is equivalent to 620 of Lee, which as seen in Fig. 5, is deposited after 610).
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kuwajima et al. (US 10,886,213 B2) in view of Uzoh (US 11,244,920 B2) in view of Park et al. (US 11,056,271 B2).
Regarding claim 5, Figs. 26-32 of Kuwajima in combination with Fig. 2 of Uzoh disclose the method of claim 1.
Kuwajima in combination with Uzoh fails to discloses “wherein the forming of the copper inductor coil includes forming an upper dome on turns of the copper inductor coil.”
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However, in a similar field of endeavor, Figs. 8-10 of Park teach wherein the forming of the copper inductor coil includes forming an upper dome on turns of the copper inductor coil (“as illustrated in (d) of FIG. 9 and (d) of FIG. 10, when the ratio a:b of a first plating film is approximately 0.2:1, the final plating pattern is formed to have upper surfaces almost roundly formed”, col. 11, lines 16-20).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the forming of the copper inductor coil includes forming an upper dome on turns of the copper inductor coil” as taught by Park in the system of Kuwajima in combination with Uzoh for the purpose of tuning the resistance of the inductor coils (“the greater the widths of the upper and lower surfaces, the greater the change in the measured resistance with respect to the design resistance”, col. 11, lines 52-54).
Regarding claim 10, Figs. 26-32 of Kuwajima in combination with Fig. 2 of Uzoh disclose the method of claim 8.
Kuwajima in combination with Uzoh fails to discloses “wherein the forming of the copper inductor coil includes forming an upper dome on turns of the copper inductor coil.”
However, in a similar field of endeavor, Figs. 8-10 of Park teach wherein the forming of the copper inductor coil includes forming an upper dome on turns of the copper inductor coil (“as illustrated in (d) of FIG. 9 and (d) of FIG. 10, when the ratio a:b of a first plating film is approximately 0.2:1, the final plating pattern is formed to have upper surfaces almost roundly formed”, col. 11, lines 16-20).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the forming of the copper inductor coil includes forming an upper dome on turns of the copper inductor coil” as taught by Park in the system of Kuwajima in combination with Uzoh for the purpose of tuning the resistance of the inductor coils (“the greater the widths of the upper and lower surfaces, the greater the change in the measured resistance with respect to the design resistance”, col. 11, lines 52-54).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kuwajima et al. (US 10,886,213 B2) in view of Uzoh (US 11,244,920 B2) in view of Zhu et al. (US 11,239,307 B2).
Regarding claim 7, Figs. 26-32 of Kuwajima in combination with Fig. 2 of Uzoh disclose the method of claim 1, Figs. 26-32 of Kuwajima further disclose further comprising;
performing back end-of-line (BEOL) processing (Kuwajima does not specify BEOL processing, however a secondary referenced will be utilized below to teach this limitation) to form a plurality of patterned metallization layers (“wirings M1-M6” are patterned metallization layers where “the wirings M1 configured using a conductive film are formed on the plug P1”, col. 14, lines 43-44, “an aluminum film as a conductive film is deposited on the plug P2, and then is patterned to form the wirings M2”, col. 14, lines 58-60, and “by repeating the formation steps of the interlayer insulation film, the wirings (M3 to M6) are formed”, col. 14, lines 64-67) spaced apart by a dielectric material (“interlayer insulation films IL1-IL6” are a dielectric material, where “an interlayer insulation film IL1 is formed on the main surface (entire main surface) of the semiconductor substrate SUB”, col. 14, lines 25-27, “an interlayer insulation film IL2 is formed on the wirings M1. For example, an oxide silicon film is deposited on the wirings M1 by the CVD method and the like”, col. 14, lines 52-55, and silicon oxide is known in the art as a dielectric material, thus as seen in Fig. 30, M1-M6 are spaced apart by the dielectric material IL1-IL6) and electrically interconnected by conductive vias (“plugs P1-P6” are conductive vias, where “the plug P1 is formed in the interlayer insulation film IL1”, col. 14, lines 32-33, “a conductive film is buried inside the contact hole to form a plug P2 in the interlayer insulation film IL2”, col. 14, lines 57-58, and “by repeating the formation steps of the interlayer insulation film, the plug, and the wiring, the plugs (P3 to P6) … are formed”, col. 14, lines 64-67, as seen in Fig. 30, M1-M6 are electrically interconnected by P1-P6) passing through the dielectric material (as seen in Fig. 30, P1-P6 pass through IL1-IL6 respectively).
Kuwajima in combination with Uzoh does not specify “performing back end-of-line (BEOL) processing to form a plurality of patterned metallization layers spaced apart by a dielectric material and electrically interconnected by conductive vias passing through the dielectric material;
wherein the copper inductor coil is formed as part of the BEOL processing and is electrically connected with at least one patterned metallization layer of the plurality of patterned metallization layers.
However, in a similar field of endeavor, Zhu teaches therefore Kuwajima teaches performing back end-of-line (BEOL) processing to form a plurality of patterned metallization layers spaced apart by a dielectric material and electrically interconnected by conductive vias passing through the dielectric material (“back-end-of-line (BEOL) fabrication processes may use a damascene scheme to form metallization layers and conductive vias. In aspects, the BEOL fabrication process may take place after front-end-of-line (FEOL) fabrication processes, when active electrical devices (e.g., transistors) are patterned on a substrate (e.g., a silicon wafer). For example, the BEOL fabrication process may involve various passive electrical devices (e.g., resistors, capacitors, and/or inductors) being formed above the active electrical devices and the various electrical devices (active and/or passive) being electrically interconnected”, col 2, lines 55-65, thus the process taught by Kuwajima is a BEOL process).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “performing back end-of-line (BEOL) processing to form a plurality of patterned metallization layers spaced apart by a dielectric material and electrically interconnected by conductive vias passing through the dielectric material” as taught by Zhu in the system of Kuwajima in combination with Uzoh for the purpose of ordering the processing steps in the manufacture of a semiconductor device.
Figs. 26-32 of Kuwajima in combination with Uzoh and Zhu fail to specify “wherein the copper inductor coil is formed as part of the BEOL processing and is electrically connected with at least one patterned metallization layer of the plurality of patterned metallization layers”.
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However, in a similar field of endeavor, Fig. 2 of Kuwajima teaches wherein the copper inductor coil is formed as part of the BEOL processing (as discussed above, Zhu teaches that the formation of CL of Kuwajima is part of the BEOL processing) and is electrically connected with at least one patterned metallization layer of the plurality of patterned metallization layers (“The coil (spiral inductor) CL shown in FIG. 2A is provided in a re-wiring layer, and is configured using a spiral wiring. Here, single winding of the coil CL is formed in an octagon shape. Pad parts PD are provided at both ends of the coil CL. Plugs are provided under the pad parts PD, and the pad parts PD are coupled to wirings (for example, sixth wirings M6) just below the pad parts PD through the plugs”, col. 5, lines 23-29).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the copper inductor coil is formed as part of the BEOL processing and is electrically connected with at least one patterned metallization layer of the plurality of patterned metallization layers” as taught by Fig. 2 of Kuwajima in the system of Figs. 26-32 of Kuwajima in combination with Uzoh for the purpose of providing electrical connections to the inductor coil in order to operate the coil.
Claims 11, 12, 13, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kuwajima et al. (US 10,886,213 B2) in view of Uzoh (US 11,244,920 B2) in view of Aleksov et al (US 8,621,744 B2).
Regarding claim 11, Figs. 26-32 of Kuwajima disclose a method of forming a radio frequency (RF) inductor device (see patent summary) including the method comprising:
forming an insulator layer (“interlayer insulation film IL7 having the opening part in the pad region and configured using a lamination film of the insulation film IL7a and the insulation film IL7b is formed”, col. 15, lines 15-19);
plating a copper inductor coil having a plurality of turns on the patterned seed layer formed on the insulator layer plating (“Next, as shown in FIG. 30, the re-wiring (not shown) and the coil (inductor) CL are formed on the insulation film IL7b including the pad region (not shown). The re-wiring (not shown) and the coil (inductor) CL are formed by growing a Cu film (copper film) by, for example, the electrolytic plating method”, col. 15, lines 20-25, Kuwajima does not disclose a patterned seed layer, however a secondary reference will be utilized to teach this limitation below).
Kuwajima fails to disclose “forming a patterned seed layer on the insulator layer; and
plating a copper inductor coil having a plurality of turns on the patterned seed layer formed on the insulator layer, wherein an area of the plated copper inductor coil having the plurality of coils is limited to an area of the patterned seed layer, and wherein the copper inductor coil comprises textured copper having at least 90% (111) orientation.
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Fig. 2 of Uzoh teaches forming a patterned seed layer on the insulator layer (“seed layer 204 (of copper or a copper alloy, for example) may be deposited over the interior of the cavity 202, which may extend over the insulating layer 106”, col. 6, lines 43-46, Uzoh does not disclose that 204 is patterned, however, a secondary reference will be utilized to teach this limitation below); and
plating a copper inductor coil having a plurality of turns on the seed layer formed on the insulator layer, and wherein the copper inductor coil comprises textured copper having at least 90% (111) orientation (“a conductive layer 206 that is several microns thick is formed over the seed layer 204 and fills the cavity 202 to form the conductive features 110 or 110′. For example, the conductive layer 206 may comprise copper or a copper alloy, for example, and may be formed using a plating bath, such as an acid bath, or the like”, col 6, lines 51-56, where “a conductive feature 110, 110′, or 110″ having a very low concentration of impurities (or substantially no impurities) may have a texture with a high percentage (e.g., >97%) of {111} oriented grains”, col. 13, lines 18-21, thus CL of Kuwajima can be formed of textured copper having at least 90% (111) orientation).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “forming a patterned seed layer on the insulator layer; and
plating a copper inductor coil having a plurality of turns on the seed layer formed on the insulator layer, and wherein the copper inductor coil comprises textured copper having at least 90% (111) orientation” as taught by Uzoh in the system of for the purpose of minimizing thermal damage to rest of the RF inductor device structure by utilizing a relatively low temperature metal formation process.
Kuwajima in combination with Uzoh fails to disclose “forming a patterned seed layer; and
plating a copper inductor coil having a plurality of turns on the patterned seed layer formed on the insulator layer, wherein an area of the plated copper inductor coil having the plurality of coils is limited to an area of the patterned seed layer.
However, in a similar field of endeavor, Fig. 15 of Aleksov teaches forming a patterned seed layer (“A step 1515 of method 1500 is to pattern the first metallic seed layer in order to define a first plating region on the first metallic seed layer”, col. 10, , lines 17-19); and
plating a copper inductor coil having a plurality of turns on the patterned seed layer (“A step 1520 of method 1500 is to plate a first electrically conductive material onto the first metallic seed layer in order to form a first plurality of inductor windings in the first plating region”, col. 10, lines 20-23), wherein an area of the plated copper inductor coil having the plurality of coils is limited to an area of the patterned seed layer (as discussed above, the first plurality of inductor windings is limited to the first plating region).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “forming a patterned seed layer; and
plating a copper inductor coil having a plurality of turns on the patterned seed layer formed on the insulator layer, wherein an area of the plated copper inductor coil having the plurality of coils is limited to an area of the patterned seed layer” as taught by Aleksov in the system of Kuwajima in combination with Uzoh for the purpose of shaping the inductor coil material without requiring further processing steps.
Regarding claim 12, Figs. 26-32 of Kuwajima in combination with Fig. 2 of Uzoh and Fig. 15 of Aleksov disclose the method of claim 11, Fig. 2 of Uzoh further discloses wherein the copper inductor coil comprises textured copper having at least 97% (111) orientation (as discussed previously, 110 may have a texture of >97% {111} oriented grains).
Regarding claim 13, Figs. 26-32 of Kuwajima in combination with Fig. 2 of Uzoh and Fig. 15 of Aleksov disclose the method of claim 12.
Figs. 26-32 of Kuwajima in combination with Uzoh and Aleksov fail to disclose “wherein:
the copper inductor coil has a height in a height direction that is transverse to the insulator layer of between one micron and seven microns; and
the turns of the copper inductor coil have a width of between one micron and 50 microns.”
However, in a similar field of endeavor, Figs. 36-38 of Kuwajima teach the copper inductor coil has a height in a height direction that is transverse to the insulator layer of between one micron and seven microns (“The re-wiring RW and the coil (inductor) CL are formed by growing a Cu film (copper film) by, for example, the electrolytic plating method to have a thickness of about 5 to 8 μm”, col. 17, lines 9-12).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the copper inductor coil has a height in a height direction that is transverse to the insulator layer of between one micron and seven microns” as taught by Figs. 36-38 of Kuwajima in the system of Kuwajima in combination with Uzoh and Aleksov for the purpose of specifying the height of the inductor coil.
Figs. 26-32 and 36-38 of Kuwajima in combination with Uzoh and Aleksov fail to disclose “wherein:
the turns of the copper inductor coil have a width of between one micron and 50 microns.”
However, in a similar field of endeavor, Fig. 6 of Kuwajima teaches the turns of the copper inductor coil have a width of between one micron and 50 microns (“The width of the coil CL is 10 μm, and an interval of the coil CL is 8 μm”, col. 6, lines 58-59).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the turns of the copper inductor coil have a width of between one micron and 50 microns”, as taught by Fig. 6 of Kuwajima in the system of Kuwajima in combination with Uzoh and Aleksov for the purpose of specifying the width of the turns of the inductor coil.
Regarding claim 14, Figs. 6, 26-32, and 36-38 of Kuwajima in combination with Fig. 2 of Uzoh and Fig. 15 of Aleksov disclose the method of claim 13, Fig. 6 of Kuwajima further discloses wherein the turns of the copper inductor coil are spaced apart by a distance of between one micron and 50 microns (as discussed above, Kuwajima states that the interval of the coil CL is 8 µm).
Regarding claim 20, Figs. 6, 26-32, and 36-38 of Kuwajima in combination with Fig. 2 of Uzoh and Fig. 15 of Aleksov disclose the method of claim 11, Figs. 26-32 of Kuwajima further disclose further comprising;
forming an interconnect structure (together “plugs P1-P6” and “wirings M1-M6”, both seen in Fig. 30 form an interconnect structure) comprising a plurality of patterned metallization layers (“wirings M1-M6” are patterned metallization layers where “the wirings M1 configured using a conductive film are formed on the plug P1”, col. 14, lines 43-44, “an aluminum film as a conductive film is deposited on the plug P2, and then is patterned to form the wirings M2”, col. 14, lines 58-60, and “by repeating the formation steps of the interlayer insulation film, the wirings (M3 to M6) are formed”, col. 14, lines 64-67) spaced apart by a dielectric material (“interlayer insulation films IL1-IL6” are a dielectric material, where “an interlayer insulation film IL1 is formed on the main surface (entire main surface) of the semiconductor substrate SUB”, col. 14, lines 25-27, “an interlayer insulation film IL2 is formed on the wirings M1. For example, an oxide silicon film is deposited on the wirings M1 by the CVD method and the like”, col. 14, lines 52-55, and silicon oxide is known in the art as a dielectric material, thus as seen in Fig. 30, M1-M6 are spaced apart by the dielectric material IL1-IL6) and electrically interconnected by conductive vias (“plugs P1-P6” are conductive vias, where “the plug P1 is formed in the interlayer insulation film IL1”, col. 14, lines 32-33, “a conductive film is buried inside the contact hole to form a plug P2 in the interlayer insulation film IL2”, col. 14, lines 57-58, and “by repeating the formation steps of the interlayer insulation film, the plug, and the wiring, the plugs (P3 to P6) … are formed”, col. 14, lines 64-67, as seen in Fig. 30, M1-M6 are electrically interconnected by P1-P6) passing through the dielectric material (as seen in Fig. 30, P1-P6 pass through IL1-IL6 respectively);
wherein the copper inductor coil is formed in or on the interconnect structure (as seen in Fig. 30, CL are formed on P1-P6 and M1-M6).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kuwajima et al. (US 10,886,213 B2) in view of Uzoh (US 11,244,920 B2) in view of Aleksov et al (US 8,621,744 B2) in view of Lee et al. (US 20240030128 A1).
Regarding claim 16, Figs. 6, 26-32, and 36-38 of Kuwajima in combination with Fig. 2 of Uzoh and Fig. 15 of Aleksov disclose the method of claim 13.
Figs. 6, 26-32, and 36-38 of Kuwajima in combination with Uzoh and Aleksov fail to disclose further comprising;
disposing an insulating coating over the copper inductor coil, the insulating coating having a thickness of between 0.5 micron and two microns.”
However, in a similar field of endeavor, Fig. 5 of Lee teaches disposing an insulating coating over the copper inductor coil, the insulating coating having a thickness of between 0.5 micron and two microns (“A protective layer 600 covering at least a part of the redistribution conductive layer 510 may be formed on the redistribution insulating layer 500. In some embodiments, the protective layer 600 may include a lower protective layer 610 and an upper protective layer 620”, [0126], here, 610 is interpreted as the insulating coating, where “The portion of the redistribution conductive layer 510 which covers the upper surface of the redistribution insulating layer 500 may be a connection pad OPD, the redistribution line RDLM, the first inductor redistribution line RDLI1, the second inductor redistribution line RDLI2, or the third inductor redistribution line RDLI3”, [0121], thus RDLI1, RDLI2, and RDLI3 of Lee are the equivalent inductor coil to structure to CL of Kuwajima, further, “lower protective layer 610 may include silicon nitride, and the upper protective layer 620 may be formed of photosensitive polyimide (PSPI), photo imageable dielectric (PID), epoxy, or polyimide”, [0030], thus as silicon nitride is known in the art as an insulating material, 610 is an insulating coating).
Lee does not directly disclose with sufficient specificity the insulating coating having a thickness of between 0.5 micron and two microns.
However, Lee does teach “the lower protective layer 610 may have a thickness of several thousand Å” ([0126]). MPEP 2144.05 I states “In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists.”
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kuwajima et al. (US 10,886,213 B2) in view of Uzoh (US 11,244,920 B2) in view of Aleksov et al (US 8,621,744 B2) in view of Park et al. (US 11,056,271 B2).
Regarding claim 17, Figs. 26-32 of Kuwajima in combination with Fig. 2 of Uzoh and Fig. 15 of Aleksov disclose the method of claim 11.
Kuwajima in combination with Uzoh and Aleksov fail to disclose “further comprising:
etching the turns of the copper inductor coil to form an upper dome on the turns of the copper inductor coil distal from the insulator layer.”
However, in a similar field of endeavor, Figs. 8-10 of Park teach etching the turns of the copper inductor coil (“FIG. 8 is a schematic cross-sectional view illustrating various examples of a pattern shape formed through inclined etching of a first plating film, and FIGS. 9 and 10 are respectively a schematic cross-sectional view and a cross-sectional photograph which illustrate shapes of a second plating film through inclined etching on the first plating film having various shapes”, col. 10, lines 27-33) to form an upper dome on the turns of the copper inductor coil distal from the insulator layer (“as illustrated in (d) of FIG. 9 and (d) of FIG. 10, when the ratio a:b of a first plating film is approximately 0.2:1, the final plating pattern is formed to have upper surfaces almost roundly formed”, col. 11, lines 16-20, thus the plating film, equivalent to CL of Kuwajima is etched to form a geometry that then undergoes a second plating process to develop an upper dome shape).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “etching the turns of the copper inductor coil to form an upper dome on the turns of the copper inductor coil distal from the insulator layer” as taught by Park in the system of Kuwajima in combination with Uzoh for the purpose of tuning the resistance of the inductor coils (“the greater the widths of the upper and lower surfaces, the greater the change in the measured resistance with respect to the design resistance”, col. 11, lines 52-54).
Allowable Subject Matter
Claims 15, 18, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the method of forming a radio frequency (RF) inductor device as recited in the claims of the instant application.
Regarding claim 15, the prior art of Kuwajima et al. (US 10,886,213 B2) in combination with Uzoh (US 11,244,920 B2) and Aleksov et al (US 8,621,744 B2) discloses a similar RF inductor device but fails to disclose the specific claims of the instant application regarding the geometry of the lower portion of the cross section of the copper inductor coil e.g. “wherein the turns of the copper inductor coil further include footings disposed on the insulator layer and extending between 0.1 micron and one micron away from opposite sides of the turn”.
Regarding claim 18, the prior art of Kuwajima et al. (US 10,886,213 B2) in combination with Uzoh (US 11,244,920 B2), Aleksov et al (US 8,621,744 B2), and Park et al. (US 11,056,271 B2) discloses a similar RF inductor device but fails to disclose the specific claims of the instant application regarding the geometry of the upper portion of the cross section of the copper inductor e.g. “the copper inductor coil including the upper dome has a height in a height direction that is transverse to the insulator layer of between one micron and seven microns; and
the dome has a height in the height direction of between 0.2 microns and one micron”.
Claim 19 is allowable by virtue of its dependence on claim 18.
Conclusion
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893