Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 10-12, and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mallik et al. (US Patent Pub 20230207525 A1, Embodiment of Figure 4, hereafter referred to as Mallik 4).
Regarding Claim 1, Mallik 4 teaches an electronic device, comprising:
a first semiconductor chip (Mallik, Fig. 4, first semiconductor chip 108) ;
a second semiconductor chip stacked on the first semiconductor chip, and electrically connected to the first semiconductor chip by hybrid bonding (Fig. 4, second semiconductor chip 110. Paragraph 0041 teaches 108 and 110 are electrically connected via hybrid bonding);
and a third semiconductor chip stacked on the second semiconductor chip, and electrically connected to the second semiconductor chip through a plurality of bumps (Fig. 4, third semiconductor chip 114. 114 is electrically connected to the second semiconductor chip via a plurality of bumps 120 (120 is pointed to in Fig. 1 and is present but not labeled in Fig. 4),
wherein a lateral surface of the first semiconductor chip is aligned with a lateral surface of the second semiconductor chip and is aligned with a lateral surface of the third semiconductor chip (Fig. 4, lateral surface of the first semiconductor chip 144 is aligned with lateral surface of the second semiconductor chip 146 and is aligned with a lateral surface of the third semiconductor chip 142).
Regarding Claim 2, Mallik 4 teaches the electronic device of Claim 1, wherein a bottom surface of the second semiconductor chip contacts a top surface of the first semiconductor chip (Fig. 4, bottom surface of the second semiconductor chip 178 (178 is pointed to in Fig. 2 and is present but not labeled in Fig. 4) contacts a top surface of the first semiconductor chip 176 (176 is pointed to in Fig. 2 and is present but not labeled in Fig. 4)).
Regarding Claim 3, Mallik 4 teaches the electronic device of Claim 1, wherein a bottom surface of the third semiconductor chip is spaced apart from a top surface of the second semiconductor chip (Fig. 4, bottom surface of the third semiconductor chip 204 (204 is pointed to in Fig. 2 and is present but not labeled in Fig. 4) is spaced apart (see space marked between Z1 and Z2) from a top surface of the second semiconductor chip 125).
Regarding Claim 10, Mallik 4 teaches the electronic device of Claim 1, further comprising a fourth semiconductor chip stacked on the third semiconductor chip, and electrically connected to the third semiconductor chip by hybrid bonding, wherein a lateral surface of the fourth semiconductor chip is aligned with the lateral surface of the third semiconductor chip (Mallik, Fig. 4 teaches fourth semiconductor chip 116 stacked on the third semiconductor chip 114, and electrically connected to the third semiconductor chip by hybrid bonding (Fig. 4, hybrid bonding occurs at interface 118 and is taught in paragraph 0033. While paragraph 0033 references Fig. 1, the elements are referred to in the same manner). A lateral surface of 116 (surface in direct line with surface 142 (see annotated figure below) is
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aligned with the lateral surface of third semiconductor chip 142).
Regarding claim 11, Mallik 4 teaches an electronic device, comprising:
a first assembly including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by hybrid bonding (Fig. 4, first assembly 104 including first semiconductor chip 108 and second semiconductor chip 110 stacked on 108 and electrically connected to the first semiconductor chip by hybrid bonding (Paragraph 0033. While paragraph 0033 references Fig. 1, the elements are referred to in the same manner));
and a second assembly including a third semiconductor chip and a fourth semiconductor chip stacked on the third semiconductor chip and electrically connected to the third semiconductor chip by hybrid bonding (Fig. 4, second assembly 106 including a third semiconductor chip 114 and a fourth semiconductor chip 116 stacked onto 114 and electrically connected to 114 by hybrid bonding (Paragraph 0033)),
wherein the second assembly is electrically connected to the first assembly through a plurality of bumps (Fig. 4, second assembly 106 electrically connected to first assembly 104 through a plurality of bumps 120 (paragraph 0033));
wherein a lateral surface of the first assembly is aligned with the lateral surface of the second assembly (Fig.4, lateral surface of first assembly 104 (surface pointed to by 144 and 146) is aligned with the lateral surface of second assembly (surface pointed to by 142)).
Regarding Claim 12, Mallik 4 teaches the electronic device of Claim 11, wherein the plurality of bumps include a reflowable material (Paragraph 0048).
Regarding Claim 14, Mallik 4 teaches the electronic device of Claim 11, wherein the second semiconductor chip and the first semiconductor chip are in face-to-face contact, the fourth semiconductor chip and the third semiconductor chip are in face-to-face contact, and the first assembly is spaced apart from the second assembly (Fig. 4, second semiconductor chip 110 and first semiconductor chip 108 are in face-to-face contact at interface 112 (122 is pointed to in Fig. 1 and is present but not labeled in Fig. 4), the fourth semiconductor chip 116 and the third semiconductor chip 114 are in face-to-face contact at interface 118 (118 is pointed to in Fig. 1 and is present but not labeled in Fig. 4), and the first assembly 104 is spaced apart from the second assembly 106 by a plurality of bumps 120).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-9 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mallik (US Patent Pub 20230207525 A1, Embodiment of Figure 4, referred to as Mallik 4) as applied to claims 1-3, 10-12, and 14 above, and further in view of Mallik US Patent Pub 20230207525 A1, Embodiment of Figure 6, hereafter referred to as Mallik 6).
Regarding Claim 4, Mallik 4 teaches the electronic device of Claim 3.
Mallik 4 fails to teach an underfill disposed between the bottom surface of the third semiconductor chip and the top surface of the second semiconductor chip to cover the plurality of bumps in the embodiment of fig. 4.
However, Mallik 6 teaches an embodiment of the electronic device wherein the device further comprises an underfill disposed between the bottom surface of the third semiconductor chip and the top surface of the second semiconductor chip to cover the plurality of bumps (Mallik 6, Fig. 6, underfill 124 disposed between the bottom surface of the third semiconductor chip 204 (204 is pointed to in Fig. 2 and is present but not labeled in Fig. 6) and the top surface of the second semiconductor chip 178 (125 in figure 4) to cover the plurality of bumps 120).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Mallik 6 into Mallik 4 by forming the electronic device comprising an underfill disposed between the bottom surface of the third semiconductor chip and the top surface of the second semiconductor chip to cover the plurality of bumps. The ordinary artisan would have been motivated to modify Mallik 4 in the manner set forth above for at least the purpose of adjoining sidewall structures of the semiconductor chips (paragraph 0036), resulting in the formation of multichip packages that may enable IC dies from heterogeneous silicon processes to be combined, enable small dis-aggregated IC dies from identical silicon processes to be combined, or both (paragraph 002).
Regarding Claim 5, Mallik 4 teaches the electronic device of claim 1, wherein the first semiconductor chip comprises a first base portion to define the lateral surface of the first semiconductor chip, and the second semiconductor chip comprises a second base portion to define the lateral surface of the second semiconductor chip at an outer surface of the second base portion (Mallik, Fig. 4, first semiconductor chip 108 includes a first base portion 154 (154 is pointed to in Fig. 2 and is present but not labeled in Fig. 4) to define the lateral surface of the first semiconductor chip 144. Second semiconductor chip 110 comprises second base portion 156 (156 is pointed to in Fig. 2 and is present but not labeled in Fig. 4) to define a lateral surface of the second semiconductor chip 146 at an outer surface of the second base portion).
Mallik 4 fails to teach a first encapsulant disposed around the first base portion of the first semiconductor chip and the second base portion of the second semiconductor chip in the embodiment of fig. 4.
However, Mallik 6 teaches an embodiment of the electronic device wherein a first encapsulant is disposed around the first base portion to define the lateral surface of the first semiconductor chip at an outer surface of the first encapsulant, and the first encapsulant is arranged such that the outer surface of the second base portion of the second semiconductor chip is aligned with the outer surface of the first encapsulant of the first semiconductor chip (Mallik 6, Fig. 6, First encapsulant 126 disposed around first base portion 154 (154 is pointed to in Fig. 2 and is present but not labeled in Fig. 6) to define the lateral surface of the first semiconductor chip 144 (144 is pointed to in Fig. 4 and is present but not labeled in Fig. 6) at an outer surface of the first encapsulant (144 would be in contact with outer surface of first encapsulant 126). The outer surface of the second base portion is aligned with the outer surface of the first encapsulant of the first semiconductor chip at lateral surface 146).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Mallik 6 into Mallik 4 by forming the electronic device wherein the first semiconductor chip comprises a first base portion and a first encapsulant disposed around the first base portion to define the lateral surface of the first semiconductor chip at an outer surface of the first encapsulant, wherein the second semiconductor chip comprises a second base portion to define the lateral surface of the second semiconductor chip at an outer surface of the second base portion, such that the outer surface of the second base portion of the second semiconductor chip is aligned with the outer surface of the first encapsulant of the first semiconductor chip. The ordinary artisan would have been motivated to modify Mallik 4 in the manner set forth above for at least the purpose of adjoining sidewall structures of the semiconductor chips (paragraph 0036), resulting in the formation of multichip packages that may enable IC dies from heterogeneous silicon processes to be combined, enable small dis-aggregated IC dies from identical silicon processes to be combined, or both (paragraph 0002).
Regarding Claim 6, Mallik 6 teaches the electronic device of Claim 5, wherein the first semiconductor chip further comprises:
a first conductive structure disposed on a first surface of the first base portion (Fig. 6, first conductive structure 158 (158 is pointed to in Fig. 2 and is present but not labeled in Fig. 6) disposed on a first surface 176 of first base portion 154);
a first lower structure disposed on the first conductive structure (Fig. 6, first lower structure 150 (150 is pointed to in Fig. 2 and is present but not labeled in Fig. 6) disposed on first conductive structure 158);
and a first upper structure disposed on a second surface of the first base portion opposite to the first surface of the first base portion (Fig. 6, first upper structure 168 (168 is pointed to in Fig. 2 and is present but not labeled in Fig. 6) disposed on a second surface 164 (164 is pointed to in Fig. 2 and is present but not labeled in Fig. 6) of first base portion 154 opposite to first surface 176 of first base portion 154) ;
wherein the first conductive structure, the first lower structure, and the first upper structure are surrounded by the first encapsulant (Fig. 6, first conductive structure 158, first lower structure 150, and first upper structure 168 are surrounded by first encapsulant 126).
Regarding Claim 7, Mallik 6 teaches the electronic device of Claim 6, wherein the first semiconductor chip further includes a plurality of first conductive vias extending through the first base portion, wherein the first lower structure includes a first lower dielectric layer and a plurality of first lower pads embedded in and exposed by the first lower dielectric layer, and the plurality of first lower pads are electrically connected to the plurality of first conductive vias through the first conductive structure (Mallik, Fig. 6, First semiconductor chip 108 including a plurality of first conductive vias 174 (174 is pointed to in Fig. 2 and is present but not labeled in Fig. 6) extending through the first base portion 154, wherein first lower structure 150 includes a first lower dielectric layer (paragraph 0043 teaches first lower structure 150 is a dielectric material) and a plurality of lower pads 147 (147 is pointed to in Fig. 2 and is present but not labeled in Fig. 6) embedded in and exposed by first lower dielectric layer (Fig. 6 and paragraph 0042), and the plurality of first lower pads 147 are electrically connected to the plurality of first conductive vias 174 through first conductive structure 158).
Regarding claim 8, Mallik 6 teaches the electronic device of Claim 7, wherein the plurality of first conductive vias extend into the first conductive structure (Fig. 6, plurality of first conductive vias 174 extend into first conductive structure 158).
Regarding Claim 9, Mallik 6 teaches the electronic device of Claim 7, wherein the first upper structure includes a first upper dielectric layer and a plurality of first upper pads embedded in and exposed by the first upper dielectric layer, and the plurality of first upper pads contact the plurality of first conductive vias (Mallik, Fig. 6, first upper structure 168 (168 is pointed to in Fig. 2 and is present but not labeled in Fig. 6) includes a first upper dielectric layer (paragraph 0042 teaches upper structure 168 is a dielectric material) and a plurality of first upper pads 162 (162 is pointed to in Fig. 2 and is present but not labeled in Fig. 6) embedded in and exposed by the first upper dielectric layer (Fig. 6, paragraph 0042), and the plurality of first upper pads 162 contact the plurality of first conductive vias 174 (174 is pointed to in Fig. 2 and is present but not labeled in Fig. 6)).
Regarding Claim 13, Mallik 4 teaches he electronic device of claim 11.
Mallik 4 fails to teach the electronic device comprising an underfill disposed between the second assembly and the first assembly and covering the plurality of bumps.
However, Mallik 6 teaches the electronic device of claim 11, further comprising an underfill disposed between the second assembly and the first assembly and covering the plurality of bumps (Mallik 6, Fig. 6, underfill 124 disposed between the second assembly 106 and first assembly 218 and covering plurality of bumps 120)
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Mallik 6 into Mallik 4 by forming the electronic device further comprising an underfill disposed between the second assembly and the first assembly and covering the plurality of bumps. The ordinary artisan would have been motivated to modify Mallik 4 in the manner set forth above for at least the purpose of adjoining sidewall structures of the semiconductor chips (paragraph 0036), resulting in the formation of multichip packages that may enable IC dies from heterogeneous silicon processes to be combined, enable small dis-aggregated IC dies from identical silicon processes to be combined, or both (paragraph 0002).
Claim(s) 15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mallik US Patent Pub 20230207525 A1, Embodiment of Figure 4, referred to as Mallik 4) as applied to claims 1-3, 10-12, and 14 above, and further in view of Pappu et al. (US Patent Pub 20180096979 A1).
Regarding Claim 15, Mallik 4 teaches the electronic device of Claim 11, wherein the first semiconductor chip (108) includes:
a first base portion (Fig. 4, first base portion 154 (154 is pointed to in Fig. 2 and is present but not labeled in Fig. 4));
a first conductive structure disposed on a first surface of the first base portion (Fig. 4, first conductive structure 158 (158 is pointed to in Fig. 2 and is present but not labeled in Fig. 4));
a first lower structure disposed on the first conductive structure (Fig. 4, first lower structure 150 (150 is pointed to in Fig. 2 and is present but not labeled in Fig. 4));
and a first upper structure disposed on a second surface of the first base portion opposite to the first surface of the first base portion (Fig. 4, first upper structure 168 (168 is pointed to in Fig. 2 and is present but not labeled in Fig. 4) disposed on a second surface 164 (164 is pointed to in Fig. 2 and is present but not labeled in Fig. 4) of first base portion 154 opposite to the first surface 176 of 154.
wherein the second semiconductor chip (110) includes:
a second base portion (Fig. 4, 156 (156 is pointed to in Fig. 2 and is present but not labeled in Fig. 4));
a second conductive structure disposed on the second base portion (Fig. 4, second conductive structure 160 (160 is pointed to in Fig. 2 and is present but not labeled in Fig. 4) disposed on 156);
a second lower structure disposed on the second conductive structure (Fig. 4, second lower structure 152 (152 is pointed to in Fig. 2 and is present but not labeled in Fig. 4) disposed on 160);
and a second upper structure disposed on the second base portion (Fig. 4, second upper structure 170 (170 is pointed to in Fig. 2 and is present but not labeled in Fig. 4) disposed on 156).
Mallik 4 fails to teach the electronic device being formed having a width of the second base portion is greater than a width of the first base portion; and a width of the second conductive structure of the second semiconductor chip is greater than a width of the first conductive structure of the first semiconductor chip.
However, Pappu teaches a stacked semiconductor device formed having:
a width of the second base portion is greater than a width of the first base portion (Pappu, Fig. 1A, second base portion 110 has a width greater than a width of the first base portion 105);
and a width of the second conductive structure of the second semiconductor chip is greater than a width of the first conductive structure of the first semiconductor chip (Pappu, Fig. 1A, see annotated figure below).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Pappu into Mallik 4 by forming the electronic device formed having a width of the second base portion is greater than a width of the first base portion; and a width of the second conductive structure of the second semiconductor chip is greater than a width of the first conductive structure of the first semiconductor chip. The ordinary artisan would have been motivated to modify Mallik in the manner set forth above for at least the purpose of fabricating a device that meets the low power consumption and high bandwidth requirements now demanded by the computing industry and consumer electronics marketplace. (Pappu, Paragaph 0068).
Regarding Claim 17, Mallik 4 teaches the electronic device of Claim 11, wherein the third semiconductor chip (Fig. 4, 114) includes:
a third base portion (Fig. 4, third base portion 194 (194 is pointed to in Fig. 2 and is present but not labeled in Fig. 4));
a third conductive structure disposed on the third base portion (Fig. 4, third conductive structure 198 (198 is pointed to in Fig. 2 and is present but not labeled in Fig. 4) disposed on 194);
a third lower structure disposed on the third conductive structure (Fig. 4, third lower structure 190 (190 is pointed to in Fig. 2 and is present but not labeled in Fig. 4) disposed on 198);
and a third upper structure disposed on the third base portion (Fig. 4, third upper structure 206 (206 is pointed to in Fig. 2 and is present but not labeled in Fig. 4) disposed on 194);
wherein the fourth semiconductor chip (Fig. 4, 116) includes:
a fourth base portion (Fig. 4, fourth base portion 196 (196 is pointed to in Fig. 2 and is present but not labeled in Fig. 4));
a fourth conductive structure disposed on the fourth base portion (Fig. 4, fourth conductive structure 200 (200 is pointed to in Fig. 2 and is present but not labeled in Fig. 4) disposed on 196);
and a fourth lower structure disposed on the fourth conductive structure (Fig. 4, fourth lower structure 192 (192 is pointed to in Fig. 2 and is present but not labeled in Fig. 4) disposed on 200).
Mallik 4 fails to teach the fourth base portion is greater than a width of the third base portion, and the width of the fourth conductive structure of the fourth semiconductor chip is greater than a width of the third conductive structure of the third semiconductor chip.
However, Pappu teaches a stacked semiconductor device formed having:
a width of the fourth base portion is greater than a width of the third base portion (Pappu, Fig. 1A, fourth base portion 110 has a width greater than a width of the third base portion 105);
wherein a width of the fourth conductive structure of the fourth semiconductor chip is greater than a width of the third conductive structure of the third semiconductor chip (Pappu, Fig. 1A, see annotated figure below).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Pappu into Mallik 4 by forming the electronic device formed having the third semiconductor chip includes: a third base portion; a third conductive structure disposed on the third base portion; a third lower structure disposed on the third conductive structure; and a third upper structure disposed on the third base portion; wherein the fourth semiconductor chip includes: a fourth base portion; a fourth conductive structure disposed on the fourth base portion; and a fourth lower structure disposed on the fourth conductive structure; wherein a width of the fourth base portion is greater than a width of the third base portion; wherein a width of the fourth conductive structure of the fourth semiconductor chip is greater than a width of the third conductive structure of the third semiconductor chip. The ordinary artisan would have been motivated to modify Mallik in the manner set forth above for at least the purpose of fabricating a device that meets the low power consumption and high bandwidth requirements now demanded by the computing industry and consumer electronics marketplace. (Pappu, Paragaph 0068).
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Claim(s) 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mallik 4 in view of Pappu as applied to claim 15 and 17 above, and further in view of Mallik 6 (Mallik US Patent Pub 20230207525 A1, Embodiment of Figure 6, referred to as Mallik 6).
Regarding Claim 16, Mallik 4 in view of Pappu teaches the electronic device of claim 15.
Mallik 4 in view of Pappu fail to teach the electronic device having a first encapsulant disposed around the first base portion, the first conductive structure, the first lower structure and the first upper structure, wherein the second semiconductor chip contacts the first encapsulant, wherein the lateral surface of the first assembly is defined at an outer surface of the first encapsulant of the first semiconductor chip and an outer surface of the second base portion of the second semiconductor chip.
However, Mallik 6 teaches an electronic device wherein the first semiconductor chip further includes a first encapsulant disposed around the first base portion, the first conductive structure, the first lower structure and the first upper structure, wherein the second semiconductor chip contacts the first encapsulant, wherein the lateral surface of the first assembly is defined at an outer surface of the first encapsulant of the first semiconductor chip and an outer surface of the second base portion of the second semiconductor chip (Mallik 6, Fig. 6, First semiconductor chip 108 includes a first encapsulant 126 disposed around first base portion 154 (154 is pointed to in Fig. 2 and is present but not labeled in Fig. 6) the first conductive structure 158, the first lower structure 150 and the first upper structure 168, wherein the second semiconductor chip 610 contacts the first encapsulant 126, wherein the lateral surface of the first assembly (first assembly 218 having lateral surface 144 defined on the first semiconductor chip 108) defined at an outer face of the first encapsulant of the first semiconductor chip and an outer surface of the second base portion 146 of second semiconductor chip 110).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Mallik 6 into the method of Mallik 4 in view of Pappu by forming the electronic device having a first encapsulant disposed around the first base portion, the first conductive structure, the first lower structure and the first upper structure, wherein the second semiconductor chip contacts the first encapsulant, wherein the lateral surface of the first assembly is defined at an outer surface of the first encapsulant of the first semiconductor chip and an outer surface of the second base portion of the second semiconductor chip. The ordinary artisan would have been motivated to modify Mallik 4 in view of Pappu in the manner set forth above for at least the purpose of adjoining sidewall structures of the semiconductor chips (Mallik, paragraph 0036), resulting in the formation of multichip packages that may enable IC dies from heterogeneous silicon processes to be combined, enable small dis-aggregated IC dies from identical silicon processes to be combined, or both (Mallik, paragraph 0002).
Regarding Claim 18, Mallik 4 in view of Pappu teaches the electronic device of Claim 17.
Mallik 4 in view of Pappu fails to teach the electronic device having a third encapsulant disposed around the third base portion, the third conductive structure, the third lower structure and the third upper structure, wherein the fourth semiconductor chip contacts the third encapsulant, wherein the lateral surface of the second assembly is defined at an outer surface of the third encapsulant of the third semiconductor chip and an outer surface of the fourth base portion of the fourth semiconductor chip.
However, Mallik 6 teaches The electronic device of Claim 17, wherein the third semiconductor chip further includes a third encapsulant disposed around the third base portion, the third conductive structure, the third lower structure and the third upper structure, wherein the fourth semiconductor chip contacts the third encapsulant, wherein the lateral surface of the second assembly is defined at an outer surface of the third encapsulant of the third semiconductor chip and an outer surface of the fourth base portion of the fourth semiconductor chip (Mallik 6, Fig. 6, third semiconductor chip 114 includes a third encapsulant 124 disposed around third base portion 194 (194 is pointed to in Fig. 2 and is present but not labeled in Fig. 6), third conductive structure 198 (198 is pointed to in Fig. 2 and is present but not labeled in Fig. 6), the third lower structure 190 (190 is pointed to in Fig. 2 and is present but not labeled in Fig. 6) and the third upper structure 206 (206 is pointed to in Fig. 2 and is present but not labeled in Fig. 6), wherein the fourth semiconductor chip 116 contacts 124, and wherein the lateral surface of second assembly (surface pointed to by 142) is defined at an outer surface of 124 and an outer surface of fourth base portion 196 (196 is pointed to in Fig. 2 and is present but not labeled in Fig. 6, an outer surface of 196 is in line with lateral surface 142 (see annotated figure in claim 10 rejection above)).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Mallik 6 into the method of Mallik 4 in view of Pappu by forming the electronic device having wherein the third semiconductor chip further includes a third encapsulant disposed around the third base portion, the third conductive structure, the third lower structure and the third upper structure, wherein the fourth semiconductor chip contacts the third encapsulant, wherein the lateral surface of the second assembly is defined at an outer surface of the third encapsulant of the third semiconductor chip and an outer surface of the fourth base portion of the fourth semiconductor chip. The ordinary artisan would have been motivated to modify Mallik 4 in view of Pappu in the manner set forth above for at least the purpose of adjoining sidewall structures of the semiconductor chips (Mallik, paragraph 0036), resulting in the formation of multichip packages that may enable IC dies from heterogeneous silicon processes to be combined, enable small dis-aggregated IC dies from identical silicon processes to be combined, or both (Mallik, paragraph 0002).
Response to Arguments
Applicant's arguments filed 20 January 2026 have been fully considered but they are not persuasive.
Applicant argues that Mallik fails to teach that a lateral surface of the first semiconductor chip is aligned with a lateral surface of the second semiconductor chip and is aligned with a lateral surface of the third semiconductor chip. However, the amendment has required a new interpretation of the art as explained above, the lateral surfaces of the first, second, and third semiconductor chips (108, 110, and 114, respectively) do align at lateral surfaces 144, 146, and 142 in the embodiment of figure 4 in Mallik.
Applicant also argues that Mallik fails to teach a first encapsulant disposed around the first base portion to define the lateral surface of the first semiconductor chip at an outer surface of the first encapsulant, as well as fails to teach that the outer surface of the second base portion of the second semiconductor chip is aligned with the outer surface of the first encapsulant of the first semiconductor chip. However, the amendment has required a new ground of rejection as explained above. The combination of the embodiments of Mallik teaches the limitations as claimed (Fig. 6, First encapsulant 126 disposed around first base portion 154 (154 is pointed to in Fig. 2 and is present but not labeled in Fig. 6) to define the lateral surface of the first semiconductor chip 144 (144 is pointed to in Fig. 4 and is present but not labeled in Fig. 6) at an outer surface of the first encapsulant (144 would be in contact with outer surface of first encapsulant 126). The outer surface of the second base portion is aligned with the outer surface of the first encapsulant of the first semiconductor chip at lateral surface 146).
Applicant also argues that Mallik fails to teach the first conductive structure, the first lower structure, and the first upper structure are surrounded by the first encapsulant. However, the amendment has required a new ground of rejection as explained above. The combination of the embodiments of Mallik teaches the limitations as claimed (Fig. 6, first conductive structure 158, first lower structure 150, and first upper structure 168 are surrounded by first encapsulant 126).
Applicant also argues that Mallik fails to teach a lateral surface of the fourth semiconductor chip is aligned with the lateral surface of the third semiconductor chip. However, the amendment has required a new interpretation of the art as explained above ((surface in direct line with surface 142 (see annotated figure below) is aligned with the lateral surface of third semiconductor chip 142).
Applicant also argues that Mallik fails to teach a lateral surface of the first assembly is aligned with the lateral surface of the second assembly. However, the amendment has required a new interpretation of the art as explained above (surface pointed to by 144 and 146) is aligned with the lateral surface of second assembly (surface pointed to by 142).
Applicant also argues that Mallik fails to teach that a width of the second base portion is greater than a width of the first base portion, as well as that a width of the second conductive structure of the second semiconductor chip is greater than a width of the first conductive structure of the first semiconductor chip. However, the amendment has required a new ground of rejection as explained above. The combination of Mallik 4 in view of Pappu teaches the limitations as claimed (a width of the second base portion is greater than a width of the first base portion (Pappu, Fig. 1A, second base portion 110 has a width greater than a width of the first base portion 105); and a width of the second conductive structure of the second semiconductor chip is greater than a width of the first conductive structure of the first semiconductor chip (Pappu, Fig. 1A, see annotated figure referenced above)).
Applicant also argues that Mallik fails to teach the lateral surface of the first assembly is defined at an outer surface of the first encapsulant of the first semiconductor chip and an outer surface of the second base portion of the second semiconductor chip. However, the amendment has required a new ground of rejection as explained above. The combination of Mallik 4 in view of Pappu, and in further view of Mallik 6 teaches the limitations as claimed (first assembly 218 having lateral surface 144 defined on the first semiconductor chip 108) defined at an outer face of the first encapsulant of the first semiconductor chip and an outer surface of the second base portion 146 of second semiconductor chip 110).
Applicant also argues that Mallik fails to teach a width of the fourth base portion is greater than a width of the third base portion, as well as a width of the fourth conductive structure of the fourth semiconductor chip is greater than a width of the third conductive structure of the third semiconductor chip. However, the amendment has required a new ground of rejection as explained above. The combination of Mallik 4 in view of Pappu teaches the limitations as claimed (a width of the fourth base portion is greater than a width of the third base portion (Pappu, Fig. 1A, fourth base portion 110 has a width greater than a width of the third base portion 105); wherein a width of the fourth conductive structure of the fourth semiconductor chip is greater than a width of the third conductive structure of the third semiconductor chip (Pappu, Fig. 1A, see annotated figure referenced above).
Applicant also argues that the lateral surface of the second assembly is defined at an outer surface of the third encapsulant of the third semiconductor chip and an outer surface of the fourth base portion of the fourth semiconductor chip. However, the amendment has required a new ground of rejection as explained above. The combination of Mallik 4 in view of Pappu, and in further view of Mallik 6 teaches the limitations as claimed (wherein the lateral surface of second assembly (surface pointed to by 142) is defined at an outer surface of 124 and an outer surface of fourth base portion 196 (196 is pointed to in Fig. 2 and is present but not labeled in Fig. 6, an outer surface of 196 is in line with lateral surface 142 (see annotated figure in claim 10 rejection above))).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/V.R.G./Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899