DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statements (IDS) filed on 24 September 2023, 13 March 2024, 6 January 2025 and 5 August 2025. The references cited on the PTOL 1449 forms have been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 6-10 and 12 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Pei et al. (U.S. Patent 9,852,982).
Referring to Claim 6, Pei teaches in Fig. 1-5, a semiconductor device, comprising: a substrate (14) having a transistor region (left side) and an one time programmable (OTP) capacitor region (right side); a first fin-shaped structure (10) on the transistor region and a second fin-shaped structure (12) on the OTP capacitor region, wherein the first fin-shaped structure (10) and the second fin-shaped structure (12) comprise different shapes; and a first gate electrode (36) on the first fin-shaped structure (10) and a second gate electrode (40) on the second fin-shaped structure (12).
It has been held that when the claimed and prior art products are identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. See MPEP § 2112.01. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997).
"The identical invention must be shown in as complete detail as is contained in the ... claim." Richardson v. Suzuki Motor Co., 868 F.2d 1226, 1236, 9 USPQ2d 1913, 1920 (Fed. Cir. 1989). The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990). See MPEP § 2131.
Referring to Claim 7, Pei further teaches wherein a concentration of dopants in the first fin-shaped structure (10) is less than a concentration of dopants in the second fin-shaped structure (12).
Referring to Claim 8, Pei further teaches wherein the first fin-shaped structure (10) comprises a rectangle in a cross-section perspective.
Referring to Claim 9, Pei further teaches wherein the second fin-shaped structure (12) comprises a triangle in a cross-section perspective.
Referring to Claim 10, Pei further teaches wherein the first gate electrode (36) comprises a metal gate (Col. 6, Lines 9-10).
Referring to Claim 12, Pei teaches in Fig. 1-5, a semiconductor device, comprising: a substrate (14) having a transistor region (38) and an anti-fuse capacitor region (44); a first fin-shaped structure (10) on the transistor region (38) and a second fin-shaped structure (12) on the anti-fuse capacitor region (44), wherein the first fin-shaped structure (10) and the second fin-shaped structure (12) comprise different shapes; and a first gate electrode (36) on the first fin-shaped structure (10) and a second gate electrode (40) on the second fin-shaped structure (12).
It has been held that when the claimed and prior art products are identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. See MPEP § 2112.01. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997).
"The identical invention must be shown in as complete detail as is contained in the ... claim." Richardson v. Suzuki Motor Co., 868 F.2d 1226, 1236, 9 USPQ2d 1913, 1920 (Fed. Cir. 1989). The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990). See MPEP § 2131.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Pei et al. (U.S. Patent 9,852,982) in view of in further view of Ou et al. (U.S. Patent Application Publication 2021/0249421).
Referring to Claim 11, Pei teaches the limitations of claim 6 and further teaches wherein the first gate electrode comprise: a high-k dielectric layer (34) on the first fin-shaped structure (10) (Col. 6, Lines 1-7). Pei teaches the well-known replacement gate process using a dummy gate located in the space over fin (10) subsequently occupied by the gate electrode (36) and dummy terminal located in the space over fin (12) subsequently occupied by the terminal (40). Sharpening is performed after removing the dummy terminal from its location on the fin (12) thereby exposing the top surface of the fin (12) and before the terminal (40) and gate electrode (36) are concurrently formed (Col. 7, Lines 1-17). While Pei discloses performing a replacement metal gate (RMG) process to transform the first gate electrode (“dummy gate”) and the second gate electrode (“dummy terminal”) into a first metal gate (36) and a second metal gate (40), Pei does not explicitly state having a work function metal layer on the high-k dielectric layer (34); and a low resistance metal layer on the work function metal layer.
Ou teaches in Fig. 5A-6D for example, a work function metal layer (195) on the high-k dielectric layer (192); and a low resistance metal layer (196) on the work function metal layer (195) (par. 40).
Therefore, it would have been obvious to one having ordinary skill in the art before the invention was effectively filed to provide the gate structure at taught by Ou for the gate structure of Pei based on its well-known suitability in the art in order to provide the desired electrical properties (i.e. threshold voltage) of the device structures utilizing the disclosed metal gate materials.
Claims 1, 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Pei et al. (U.S. Patent 9,852,982) in view of Hafez et al. (U.S. Patent Application Publication 2013/0270559).
Referring to Claim 1, Pei teaches a method for fabricating a semiconductor device, comprising: providing a substrate (14) having a transistor region (left side) and an one time programmable (OTP) capacitor region (right side); forming a first fin-shaped structure (10) on the transistor region and a second fin-shaped structure (12) on the OTP capacitor region; and forming a gate oxide layer (34, 42; Col. 5, Line 53 to Col. 6, Line 13) on the first fin-shaped structure (10) and the second fin-shaped structure (12), wherein the first fin-shaped structure (10) and the second fin-shaped structure (12) comprise different shapes.
While Pei does perform an oxidation process to form the shape of second fin-shaped structure (12) (Fig. 3; Col. 4, Lines 7-30), Pei does not explicitly state performing an oxidation process to form the gate oxide layer (34, 42).
In the same field of endeavor, Hafez teaches forming a FinFET antifuse transistor structure utilizing a fin with a tapered upper portion has a relatively lower breakdown voltage, and the degree of tapering can be adjusted to provide the desired breakdown voltage (par. 18). Hafez further teaches forming the gate oxide layer (“isolation dielectric”) by oxidation process to achieve the desired shape of the fin and provide the benefits noted above (Fig. 13-15; par. 35-38).
Therefore, it would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the oxidation process taught by Hafez to form the gate oxide layer of Pei based on its well-known suitability in the art in order to provide the desired electrical properties for the taper shaped fin of the antifuse as envisioned.
It has been held that when the claimed and prior art products are identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. See MPEP § 2112.01. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997).
"The identical invention must be shown in as complete detail as is contained in the ... claim." Richardson v. Suzuki Motor Co., 868 F.2d 1226, 1236, 9 USPQ2d 1913, 1920 (Fed. Cir. 1989). The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990). See MPEP § 2131.
Referring to Claim 4, as modified, Pei further teaches wherein the first fin-shaped structure (10) comprises a rectangle in a cross-section perspective.
Referring to Claim 5, as modified, Pei further teaches wherein the second fin-shaped structure (12) comprises a triangle in a cross-section perspective.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Pei et al. (U.S. Patent 9,852,982) in view of Hafez et al. (U.S. Patent Application Publication 2013/0270559) in further view of Ou et al. (U.S. Patent Application Publication 2021/0249421).
Referring to Claim 2, as modified, Pei further comprising: performing a heavy doping process (24) to form a doped region (22) in the second fin-shaped structure (12; Fig. 2); forming a first gate electrode (36) on the first fin-shaped structure (10) and a second gate electrode (40) on the second fin-shaped structure (12); forming a source/drain region (not shown; Col. 5, Lines 47-52) adjacent to two sides of the first gate electrode (36). Pei also teaches the well-known replacement gate process using a dummy gate located in the space over fin (10) subsequently occupied by the gate electrode 36 and dummy terminal located in the space over fin (12) subsequently occupied by the terminal (40). Sharpening is performed after removing the dummy terminal from its location on the fin (12) thereby exposing the top surface of the fin (12) and before the terminal (40) and gate electrode (36) are concurrently formed (Col. 7, Lines 1-17). While Pei discloses performing a replacement metal gate (RMG) process to transform the first gate electrode (“dummy gate”) and the second gate electrode (“dummy terminal”) into a first metal gate (36) and a second metal gate (40), Pei does not explicitly state forming an interlayer dielectric (ILD) layer around the first gate electrode (“dummy gate”) and the second gate electrode (“dummy terminal”), per se.
It is noted that Hafez also teaches the known use of utilizing a sacrificial gate material that is later removed for a replacement metal gate process (page 2, par. 19, right column, Lines 41-48).
Ou teaches in Fig. 5A-6D for example, forming an interlayer dielectric (ILD) layer (180) around the first and second gate electrodes (140a and 140b); and performing a replacement metal gate (RMG) process to transform the first and second gate electrodes (140a and 140b) into a first and second metal gates (190a and 190b) (par. 39-40).
Therefore, it would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the ILD and replacement gate process taught by Ou to form the metal gates of Pei in view of Hafez based on its well-known suitability in the art in order to protect the parts of transistor structures and provide the desired electrical properties (i.e. threshold voltage) with the metal gate materials.
Referring to Claim 3, as modified, Pei further teaches wherein a concentration of dopants in the first fin-shaped structure (10) is less than a concentration of dopants in the second fin-shaped structure (12).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896