DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 4/24/24, 8/14/25, and 1/28,26 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of claims 1 through 15 in the reply filed on 2/24/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 4, and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “a plurality of patterned metal layers” in line 2, it is unclear if this refers to “a plurality of patterned metal layer” recited in claim 1 lines 10 and 11.
Claim 3 recites ”a dielectric structure” in line 3, it is unclear if this refers to a dielectric structure recited in claim1 line 11.
Claim 3 lines 1 through 5 are identical to claim 1 lines 10 through 14. It is therefore unclear whether the elements are the same or different. For the purpose of examination, the examiner will understand the elements of claim 3 to be duplicates of claim 1
Claim 4 depends from and incorporates claim 3.
Claim 15 recites “the second conductive structure defines an opening to expose a portion of the second test pad” in lines 2 and 3. However, claim 4 also recites that “the bonding layer extends into the opening to contact the portion of the second test pad” in lines 3 and 4. Since the portion of the test pad in the opening is in contact with the bonding layer it is not exposed, and if it is exposed then it is not in contact with the bonding layer. For the purpose of examination the examiner will understand that the claim to mean“the second conductive structure comprises an opening”.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 3 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 3 lines 1 through 5 are identical to claim 1 lines 10 through 14.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, 3, 4, 5, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 2015/0228547) in view of Chen (US 2021/0375721)
Regarding claim 1.
Shih teaches:
an electronic device (fig 5:400; [para 0024]), comprising:
a substrate (fig 5:10; [para 0023]);
a conductive structure (fig 5:25,30; [para 0026]) disposed on the substrate (fig 5:10; [para 0023]) and including a test pad (fig 5:32; [para 0022]) configured to be contacted by a probe (fig 5:50; [para 0022]) during a testing process;
and at least one external connector (fig 5:38,40; [para 0023]) electrically connected to the conductive structure (fig 5:25,30; [para 0022]) and exposed from a surface of the electronic device (fig 5:400; [para 0024]) for an external electrical connection,
wherein a vertical projection of the at least one external connector (fig 5:38,40; [para 0023]) overlaps a vertical projection of the pad (fig 5:32; [para 0022]);
wherein the conductive structure (fig 5:25,30; [para 0026]) further includes a plurality of patterned metal layers (fig 5:25; [para 0022]) and a dielectric structure (fig 5:24,36; [para 0022]),
wherein the pad (fig 5:32; [para 0022]) is electrically connected to the plurality of patterned metal layers (fig 5:25; [para 0022]),
and the pad (fig 5:32; [para 0022]) and the plurality of patterned metal layers (fig 5:25; [para 0022]) are embedded in the dielectric structure (fig 5:24,36; [para 0022]);
wherein the at least one external connector (fig 5:38,40; [para 0023]) includes a conductive via (fig 5:38; [para 0023]),
and a bottom passivation layer (fig 5:46; [para 0023]) disposed on a bottom surface of the substrate (fig 5:10; [para 0023]) and surrounding the conductive via (fig 5:38; [para 0023]).
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Shih does not teach that the bonding pad portion can be used for testing.
Chen teaches:
a bonding pad (fig 1I:130a; [para 0023]) configured to be contacted by a probe (fig 1I:132[para 0023]) during a testing process ([para 0023])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a pad configured as a bonding pad can also be configured as a testing pad in order to minimize the number of pads required for a structures.
Further, the limitation must distinguish from the prior art in terms of structure rather than function (bonding or testing), In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); See also In re Swinehart, 439 F.2d210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971). Claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Danly, 263 F. 2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F. 2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990).
Regarding claim 2
Shih in view of Chen teaches the electronic device of claim 1, further:
comprising a capacitor (fig 5:161; [para 0028]) disposed on the substrate (fig 5:10; [para 0023]).
Regarding claim 3.
Shih in view of Chen teaches the electronic device of claim 1, wherein:
wherein the conductive structure (fig 5:25,30; [para 0026]) further includes a plurality of patterned metal layers (fig 5:25; [para 0022]) and a dielectric structure (fig 5:24,36; [para 0022]),
wherein the test pad (fig 5:32; [para 0022]) is electrically connected to the plurality of patterned metal layers (fig 5:25; [para 0022]),
and the pad (fig 5:32; [para 0022]) and the plurality of patterned metal layers (fig 5:25; [para 0022]) are embedded in the dielectric structure (fig 5:24,36; [para 0022]);
Regarding claim 4.
Shih in view of Chen teaches the electronic device of claim 3,
Shih teaches:
the dielectric structure (fig 5:24,36; [para 0022]) defines an opening to expose a first portion (fig 5:32; [para 0022]) of the test pad (fig 5:30; [para 0022]) configured to be contacted by the probe;
;
wherein a vertical projection of the at least one external connector (fig 5:38,40; [para 0023]) overlaps a vertical projection of the opening;
wherein a vertical projection of the at least one external connector (fig 5:38,40; [para 0023]) is located outside a vertical projection of the opening.
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Chen teaches the first portion of the test pad (fig 1a:130a; [para 0023]) has a probe mark (fig 1a:132; [para 0023]) thereon.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a pad comprises a probe mark as a consequence of probing with a probe displacing material on the surface of the pad resulting in a probe marked pad.
Regarding claim 5.
Shih in view of Chen teaches the electronic device of claim 1.
Shih teaches:
the conductive via (fig 5:38; [para 0023]) extends through the substrate (fig 5:10; [para 0023])
Chen teaches:
the conductive via (fig 1j,1k:154; [para 0029]) extends through the substrate (fig 1j,1k:110; [para 0034]) and is exposed from a bottom surface of the electronic device (fig 1k:100; [para 0018]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to expose the via from the bottom surface of the device in order to avoid the step of forming an additional pad and thereby simplify the fabrication process. MPEP 2144.04.II.
Regarding claim 6.
Shih in vies of Chen teaches the electronic device of claim 5,
Chen teaches:
a bottom surface of the bottom passivation layer (fig 1k:190; [para 0034]) is substantially aligned with a bottom surface of the conductive via (fig 1k:154; [para 0032]).
Claim(s) 1, 7, 8, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0366856) in view of Chen (US 2021/0375721)
Regarding claim 1.
Kim teaches:
An electronic device (fig 10:200; [para 0028]), comprising:
a substrate (fig 10:210; [para 0044]);
a conductive structure (fig 10:231,232; [para 0052]) disposed on the substrate (fig 10:210; [para 0044]) and including a pad (fig 10:250; [para 0051]) ;
and at least one external connector (fig 10:220; [para 0053]) electrically connected to the conductive structure (fig 10:231,232; [para 0052]) and exposed from a surface (fig 10:220b; [para 0053]) of the electronic device (fig 10:200; [para 0028]) for an external electrical connection,
wherein a vertical projection of the at least one external connector (fig 10:220; [para 0053]) overlaps a vertical projection of the pad (fig 10:250; [para 0051]);
wherein the conductive structure (fig 10:231,232; [para 0052]) further includes a plurality of patterned metal layers (fig 10:231; [para 0052]) and a dielectric structure (fig 10:232; [para 0052]),
wherein the pad (fig 10:250; [para 0051]) is electrically connected to the plurality of patterned metal layers (fig 10:231; [para 0052]),
and the pad (fig 10:250; [para 0051]) and the plurality of patterned metal layers (fig 10:231; [para 0052]) are embedded in the dielectric structure (fig 10:232; [para 0052]);
wherein the at least one external connector (fig 10:220,260; [para 0053,0048]) includes a conductive via (fig 10:220; [para 0053]),
and a bottom passivation layer (fig 10:240; [para 0054]) disposed on a bottom surface of the substrate (fig 10:210; [para 0044]) and surrounding the conductive via (fig 10:220; [para 0053]).
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Kim does not teach the pad is a test pad.
Chen teaches:
An electronic structure (fig 6:600; [para 0045]), comprising:
a substrate (fig 1k:110; [para 0018]);
a conductive structure (fig 1k:114,130a; [para 0020,0023]) disposed over the substrate (fig 1k:110; [para 0018]) and including a test pad (fig 1k:130a; [para 0023]) configured to be contacted by a probe during a testing process ([para 0023]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the pad to be a test pad that the structure can be tested by the application of a probe and thereby determine the proper functioning of the device.
Regarding claim 7.
Kim teaches in view of Chen teaches the electronic device of claim 1, further:
Kim teaches:
the at least one external connector (fig 10:220,260; [para 0048,0053]) includes a connection via (fig 10:260; [para 0048]) connected to a second portion of the pad (fig 10:250; [para 0051]) and exposed from a top surface of the electronic device (fig 10:200; [para 0029]).
Chen teaches:
a test pad (fig 1k:130a; [para 0023])
Regarding claim 8.
Kim teaches in view of Chen teaches the electronic device of claim 7, further:
Kim teaches:
a top passivation layer (fig 10:280; [para 0045]) disposed on a top surface of the conductive structure (fig 10:231,232; [para 0052]) and surrounding the connection via (fig 10:260; [para 0048]);
wherein a top surface of the top passivation layer (fig 10:280; [para 0045]) is substantially aligned with a top surface of the connection via (fig 10:260; [para 0048]).
Regarding claim 9.
Kim teaches in view of Chen teaches the electronic device of claim 1, further:
Kim teaches:
the at least one external connector (fig 10:220,260; [para 0048,0053]) includes a connection via (fig 10:260; [para 0048]),
the conductive via (fig 10:220; [para 0053]) extends through the substrate (fig 10:210; [para 0044]) and is disposed under the conductive structure (fig 10:232,231; [para 0052]) the connection via (fig 10:260; [para 0048]) ,
wherein the pad (fig 10L250; [para 0051]) is disposed between the conductive via (fig 10:220; [para 0053]) and the connection via (fig 10:260; [para 0048]);
wherein a width of the connection via (fig 10:260; [para 0048]) is less than a width of the conductive via (fig 10:220; [para 0053]).
Chen teaches:
a test pad (fig 1k:130a; [para 0023])
the connection via (fig 1h:172; [para 0032]) extends through a portion of a dielectric structure (fig 1h:122; [para 0025]) of the conductive structure (fig 1h:122,130a,114c,114; [para 0020-0024]) on the test pad (fig 1k:130a; [para 0023]),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the connection via to extend through a portion of a dielectric structure in order to provide a layer of stress alleviation over the conductive material and to level the surface before bonding (Chen paragraph 25).
Claim(s) 10, 11, 12, 13, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0366856) in view of Chen (US 2021/0375721)
Regarding claim 10.
Kim teaches:
An electronic structure (fig 1:10; [para 0027]), comprising:
a first substrate (fig 1:110; [para 0031]);
a first conductive structure (fig 1:131,132; [para 0031]) disposed over the first substrate (fig 1:110; [para 0031]) and including a first pad (fig 1:150; [para 0031]) ;
a second conductive structure (fig 1:231,232; [para 0052]) disposed under the first substrate (fig 1:110; [para 0031]) and including a second pad (fig 1:250; [para 0043]) ,
wherein an electrical path between the first conductive structure (fig 1:131,132; [para 0031]) and the second conductive structure (fig 1:231,232; [para 0052]) is located between the first pad (fig 1:150; [para 0031]) and the second pad (fig 1:250; [para 0043]);
and an interconnection pillar (fig 1:120,260; [para 0031,0043]) electrically connecting the first conductive structure (fig 1:131,132; [para 0031]) and the second conductive structure (fig 1:231,232; [para 0052]),
wherein the interconnection pillar (fig 1:120,260; [para 0031,0043]) forms the electrical path;
wherein the electrical path includes a vertical electrical path,
and a projection of the vertical electrical path on the second pad (fig 1:250; [para 0043]) is within a projection of the first pad (fig 1:150; [para 0031]) on the second pad (fig 1:250; [para 0043]).
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Kim does not teach a first test pad configured to be contacted by a probe during a testing process; and a second test pad configured to be contacted by a probe during a testing process
Chen teaches:
An electronic structure (fig 6:600; [para 0045]), comprising:
a first substrate (fig 1k:110; [para 0018]);
a first conductive structure (fig 1k:114,130a; [para 0020,0023]) disposed over the first substrate (fig 1k:110; [para 0018]) and including a first test pad (fig 1k:130a; [para 0023]) configured to be contacted by a probe during a testing process ([para 0023]);
a second conductive structure (fig 1k:110; [para 0018]) disposed under the first substrate (fig 1k:110; [para 0018]) and including a second test pad (fig 1k:130a; [para 0023]) configured to be contacted by a probe during a testing process ([para 0023]),
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first pad to be a first test pad and the second pad to be a second test pad in order that the structures can be tested by the application of a probe and thereby determine the proper functioning of the device.
Regarding claim 11.
Kim in view of Chen teaches the electronic structure of claim 10,
Kim teaches:
the vertical electrical path passes through the first substrate (fig 1:110; [para 0031]).
Regarding claim 12
Kim in view of Chen teaches the electronic structure of claim 10,
Kim teaches:
the interconnection pillar (fig 1:120,260; [para 0034,0043])includes a conductive via (fig 1:120; [para 0034]) and a connection via (fig 1:260; [para 0043]),
and a width of the connection via (fig 1:260; [para 0043]) is less than a width of the conductive via (fig 1:120; [para 0034]);
wherein the conductive via (fig 1:120; [para 0034]) extends through the first substrate (fig 1:110; [para 0032]),
and the connection via (fig 1:260; [para 0043]) connects to the second pad (fig 1:250; [para 0043]).
Chen teaches:
a second test pad (fig 1k:130a; [para 0023])
Regarding claim 13.
Kim in view of Chen teaches the electronic structure of claim 10,
Kim teaches:
the interconnection pillar (fig 1:120,260; [para 0034,0043])includes a conductive via (fig 1:120; [para 0034]) and a plurality of connection vias,
and a width of each of the connection vias is less than a width of the conductive via (fig 1:120; [para 0034]).
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Regarding claim 14.
Kim in view of Chen teaches the electronic structure of claim 10,
Kim teaches:
a bonding layer (fig 1:140,280; [para 0045])bonding the first substrate (fig 1:110; [para 0045]) and the second conductive structure (fig 1:231,232; [para 0043]),
and the electrical path passes through the bonding layer (fig 1:140,280; [para 0045]).
Regarding claim 15.
Kim in view of Chen teaches the electronic structure of claim 10,
Chen teaches:
the second conductive structure defines an opening to expose a portion of the second test pad, (interpreted to mean the conductive structures comprises an opening, see 112 2nd rejection above)
and the bonding layer extends into the opening to contact the portion of the second test pad.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the conductive structure to comprise an opening over the test pad with bonding layer extending therethrough in order to provide a layer of stress alleviation over the conductive material and to level the surface before bonding (Chen paragraph 25).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/ Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 6, 2026