DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1 through 15 rejected
Present actions: claims 1 through 15 rejected
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7, 8, and 9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 7 recites “a connection via connected to the second portion of the test pad and exposed from a top surface of the electronic device” in lines 2 and 3. However, the specification as filed does not disclose this element in combination with “an opening to expose a first portion of a top surface of the test pad” recited in claim 4 line 2. Rather the specification and figures show that the surface of the test pad is covered by a dielectric material (27) and therefore no portion of the test pad is exposed in an embodiment comprising the connection via.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 through 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites “at least one external connector further comprises a connection via connected to the second portion of the test pad and exposed from a top surface of the electronic device” in lines 2 and 3. However, the specification as filed does no teach this element in combination with “an opening to expose a first portion of a top surface of the test pad” recited in claim 4 line 2. It is therefore unclear whether or not the surface of the test pad is exposed. For the purpose of examination the examiner will interpret the claim in view of the specification (fig 3), and will understand that the surface of the test pad is covered by passivation material through which the connection via penetrates.
Claim 8 recites “the top passivation layer is formed within the opening to cover the probe mark and the first portion of the top surface of the test pad” in lines 4 through 6. However, claim 4 recites “an opening to expose a first portion of a top surface of the test pad” in line 2. It is therefore unclear if the first portion is exposed as is required by claim 4, or covered as is required by claim 8.
Claim 9 depends from claim 9, this is unclear and improper. For the purpose of examination the examiner will assume that claim 9 depends from claim 7.
Claim 10 recites “a bonding layer not only bonding the first substrate on the second conductive structure but also enclosing the exposed top surface of the second test pad” in lines 11 and 12. The construction of the limitation makes it unclear whether or not the limitations are linked and dependent; is “enclosing” only claimed if a bonding layer is present. The examiner suggests “a bonding layer to the second conductive structure and enclosing the exposed top surface of the second test pad”.
Claim 10 recites “a second conductive structure disposed under the first substrate and including a second test pad having a covered top surface and an exposed top surface” in lines 5 and 6. When the second test pad is disposed under and bonded to the first substrate it is not exposed, when the second test pad is exposed it is not disposed under and bonded to the first substrate (see figure 1).
Claim 10 recites “a bonding layer not only bonding the first substrate on the second conductive structure but also enclosing the exposed top surface of the second test pad” in lines 11 and 12. When the bonding layer encloses the top surface of the test pad, the top surface is not exposed.
It is therefore unclear whether or not the top surface of the second test pad is exposed. For the purpose of examination, the examiner will interpret the top surface of the second test pad to be disposed under the first substrate, enclosed by the bonding layer, and not exposed.
Claim 13 recites the limitation "the connection vias" in line 5. There is insufficient antecedent basis for this limitation in the claim. The antecedent recites “a plurality of connection vias in line 2.
Claim 15 recites the limitation "the connection vias" in line 2. There is insufficient antecedent basis for this limitation in the claim. The antecedent recites “a plurality of connection vias in line 2.
Claims 11 through 15 depend from and incorporate claim 10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s) or interpreted by the examiner.
Claim(s) 1, 3, 4, 5, 6, 7, 8, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 2015/0228547) in view of Chen (US 2021/0375721)
Regarding claim 1.
Shih teaches:
An electronic device (fig 5:400; [para 0024]), comprising: a substrate (fig 5:10; [para 0023]);
a conductive structure (fig 5:21,18,24,25,30,36; [para 0026]) disposed on and in contact with a top surface of the substrate (fig 5:10; [para 0023]) and including a pad (fig 5:32; [para 0022]) configured to be contacted by a probe (fig 5:50; [para 0022]) during a testing process;
and at least one external connector (fig 5:38,40; [para 0023]) electrically connected to the conductive structure (fig 5:21,18,24,25,30,36; [para 0021,0026]) and exposed from a surface of the electronic device (fig 5:400; [para 0024]) for an external electrical connection, wherein a vertical projection of the at least one external connector (fig 5:38,40; [para 0023]) overlaps a vertical projection of the pad (fig 5:32; [para 0022]);
wherein the conductive structure (fig 5:21,24,18,25,30,36; [para 0021,0026]) further comprises a plurality of patterned metal layers (fig 5:25; [para 0026]) and a dielectric structure (fig 5:21,18,30,36; [para 0021,0026]), wherein the pad (fig 5:32; [para 0022]) is electrically connected to the plurality of patterned metal layers (fig 5:25; [para 0026]), and the pad (fig 5:32; [para 0022]) and the plurality of patterned metal layers (fig 5:25; [para 0026]) are embedded in the dielectric structure (fig 5:21,24,18,30,36; [para 0021,0026]);
wherein the at least one external connector (fig 5:38,40; [para 0023]) comprises a conductive via (fig 5:38; [para 0023]) extended from one of the patterned metal layers (fig 5:25; [para 0026]), and a bottom passivation layer (fig 5:46; [para 0023]) disposed on a bottom surface of the substrate (fig 5:10; [para 0023]), wherein a length of the conductive via (fig 5:38; [para 0023]) is larger than a thickness of the substrate (fig 5:10; [para 0023]), such that the conductive via (fig 5:38; [para 0023]) is extended through the substrate (fig 5:10; [para 0023]) to the passivation layer (fig 5:46; [para 0023]);
wherein the conductive via (fig 5:38; [para 0023]) has a first portion extended within the substrate (fig 5:10; [para 0023]) and surrounded by the dielectric structure (fig 5:21; [para 0021]),
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Shih does not teach that the bonding pad portion can be used for testing or the via extends to the bottom of the passivation.
Chen teaches:
A bonding pad (fig 1l:130a; [para 0023])configured to be contacted by a probe (fig 1l:132; [para 0023])during a testing process ([para 0023])
a length of the conductive via (fig 1I:154; [para 0032]) is larger than a thickness of the substrate (fig 1I:110; [para 0028]), such that the conductive via (fig 1I:154; [para 0032]) is extended through the substrate (fig 1I:110; [para 0028]) to the bottom passivation layer (fig 1I:190; [para 0034]);
wherein the conductive via (fig 1I:154; [para 0032]) has a first portion extended within the substrate (fig 1I:110; [para 0028]), and a second portion extended out of the substrate (fig 1I:110; [para 0028])and surrounded by the bottom passivation layer (fig 1I:190; [para 0034])
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the pad can be used for testing in order to minimize the number of pad structures formed, further extending the through silicon via to the bottom of the passivation layer enables a planar surface around at the bottom via surface to be provided thereby enable die stacking (fig 6).
Regarding claim 3.
Shih in view of Chen teaches the electronic device of Claim 1, further
Chen teaches:
a bottom surface of the conductive via (fig 1I:154; [para 0032]) is aligned with a bottom surface of the bottom passivation layer (fig 1I:190; [para 0034]).
Regarding claim 4.
Shih in view of Chen teaches the electronic device of Claim 3, further
Shih teaches:
the dielectric structure (fig 5:21,24,18,30,36; [para 0021,0026]) defines an opening to expose a first portion of a top surface of the pad (fig 5:32; [para 0022]) configured to be contacted by the probe (fig 5:50; [para 0022]);
;
wherein a vertical projection of the at least one external connector (fig 5:38,40; [para 0023]) overlaps a vertical projection of the opening;
wherein a vertical projection of the at least one external connector (fig 5:38,40; [para 0023]) is located outside a vertical projection of the opening;
wherein a size of the opening is less than a size of the test pad to expose the first portion of the top surface of the test pad through the opening and to cover a second portion of the top surface of the test pad.
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Chen teaches:
the first portion of the test pad (fig 1a:130a; [para 0023]) has a probe mark (fig 1a:132; [para 0023]) thereon
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a pad tested by a probe will have a probe mark thereon as a consequence of probing due to the displacement of material of the pad surface by impact with the probe tip
Regarding claim 5.
Shih in view of Chen teaches the electronic device of Claim 4, further
Chen teaches:
the probe mark (fig 1a:132; [para 0023]) is recessed (scratch or gouged surface; [para 0023]) on the top surface of the first portion of the test pad (fig 1a:130a; [para 0023]).
Regarding claim 6.
Shih in view of Chen teaches the electronic device of Claim 5, further
Shih teaches:
the conductive structure (fig 5:21,24,18,25,30,36; [para 0021,0026]) further comprises a plurality of inner vias (fig 5) embedded in the dielectric structure (fig 5:24; [para 0021,0026]), wherein the patterned metal layers (fig 5:24; [para 0026]) are electrically connected with each other by the inner vias.
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Regarding claim 7
Shih in view of Chen teaches the electronic device of Claim 4,
Chen teaches:
the at least one external connector further comprises a connection via (fig 1k:182; [para 0033]) connected to the second portion of the test pad (fig 1k:130a; [para 0023]) and exposed from a top surface of the electronic device, wherein the connection via (fig 1k:154,182; [para 0033]) is extended from the second portion the top surface of the test pad (fig 1k:130a; [para 0023]) through the dielectric structure (fig 1k:122; [para 0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a connection via over the test pad in order to enable the formation of a planar surface which will then facilitate the formation of stack devices.
Regarding claim 8
Shih in view of Chen teaches the electronic device of Claim 7,
Chen teaches:
a top passivation layer (fig 1k:180; [para 0033]) disposed on a top surface of the dielectric structure (fig 1k:122; [para 0025]) of the conductive structure (fig 1k:130a,102; [para 0023]) and surrounding the connection via (fig 1k:154,182; [para 0033]);
wherein a top surface of the top passivation layer (fig 1k:180; [para 0033]) is substantially aligned with a top surface of the connection via (fig 1k:154,182; [para 0033]), wherein the top passivation layer (fig 1k:180; [para 0033]) is formed within the opening to cover the probe mark (fig 1k:132; [para 0023]) and the first portion of the top surface of the test pad (fig 1k:130a; [para 0023]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a connection via over the test pad and surrounded by a passivation layer in order to enable the formation of a planar surface which will then facilitate the formation of stack devices.
Regarding claim 9
Shih in view of Chen teaches the electronic device of Claim [7],
Chen teaches:
a width of the connection via (fig 1k:154,182; [para 0033]) is less than a width of the conductive via (fig 1k; [para 0034]), wherein the connection via (fig 1k:154,182; [para 0033])has a first portion extended from the second portion of the top surface of the test pad (fig 1k:130a; [para 0023])and surrounded by the dielectric structure (fig 1k:122; [para 0025]), and a second portion extended out of the dielectric structure (fig 1k:122; [para 0025])and surrounded by the top passivation layer (fig 1k:180; [para 0033]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a connection via over the test pad and surrounded by a passivation layer in order to enable the formation of a planar surface which will then facilitate the formation of stack devices.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 2015/0228547) in view of Chen (US 2021/0375721) as applied to claim 1 and further in view of Huang (US 2021/0296283).
Regarding claim 2.
Shih in view of Chen teaches the electronic device of Claim 1, above
Shih teaches:
a capacitor (fig 5:161; [para 0028]) disposed on a top surface of the substrate (fig 5:10; [para 0023]).
Shih in view of Chen does not teach the capacitor is in contact with the top surface of the substrate.
Huang teaches:
a capacitor (fig 5a:102; [para 0048]) disposed on and in contact with a top surface (fig 5a:116; [para 0050]) of the substrate (fig 5a:110; [para 0049]).
It would have been obvious to one of ordinary skilling the art before the effective filing date of the claimed invention for the capacitor to be inContact with the top surface of the substate in order to decrease the size of the integrated passive device (paragraph 21).
Claim(s) 10, 11, 12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0366856) in view of Chen (US 2021/0375721).
Regarding claim 10.
Kim teaches:
An electronic structure, comprising:
a first substrate (fig 1:110; [para 0031]);
a first conductive structure (fig 1:131; [para 0031]) disposed over the first substrate (fig 1:110; [para 0031]) and including a first pad (fig 1:150,160; [para 0031]) configured to be contacted by a probe during a testing process;
a second conductive structure (fig 1:321; [para 0043]) disposed under the first substrate (fig 1:110; [para 0031]) and including a second test pad (fig 1:250; [para 0043]) having a covered top surface (see 112 2nd paragraph rejection above) configured to be contacted by a probe during a testing process, wherein an electrical path between the first conductive structure (fig 1:131; [para 0031]) and the second conductive structure (fig 1:321; [para 0043]) is located between the first pad (fig 1:150,160; [para 0031]) and the second test pad (fig 1:250; [para 0043]);
an interconnection pillar (fig 1:120,260; [para 0034,0043]) electrically connecting the first conductive structure (fig 1:131; [para 0031]) and the second conductive structure (fig 1:321; [para 0043]), wherein the interconnection pillar (fig 1:120,260; [para 0034,0043]) forms the electrical path;
and a bonding layer (fig 1:280,140; [para 0045]) not only bonding the first substrate (fig 1:110; [para 0031]) on the second conductive structure (fig 1:321; [para 0043]) but also enclosing the exposed top surface of the second pad (fig 1:250; [para 0043]);
wherein the electrical path includes a vertical electrical path, and a projection of the vertical electrical path on the second pad (fig 1:250; [para 0043]) is within a projection of the first pad (fig 1:150,160; [para 0031]) on the second pad (fig 1:250; [para 0043]) .
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Kim does not teach the pads can be tested.
Chen teaches:
A first test pad (fig 1k,6:130a; [para 0023])
And a second test pad (fig 1k,6:130a; [para 0023])
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the pad to be used as a test pad so that the internal circuitry of the die can be tested using a testing probe for the purpose of die evaluation.
Regarding claim 11.
Kim in view of Chen teaches the electronic structure of Claim 10, further
Kim teaches:
the vertical electrical path passes through the first substrate (fig 1:110; [para 0031]).
Regarding claim 12.
Kim in view of Chen teaches the electronic structure of Claim 10, further
Kim teaches:
The interconnection pillar (fig 1:120,260; [para 0034,0043]) includes a conductive via (fig 1:120; [para 0034,0043]) and a connection via (fig 1:260; [para 0034,0043]), and a width of the connection via (fig 1:260; [para 0034,0043]) is less than a width of the conductive via (fig 1:120; [para 0034,0043]);
wherein the conductive via (fig 1:120; [para 0034,0043]) extends through the first substrate (fig 1:110; [para 0031]) into the bonding layer (fig 1:140,280; [para 0045]), and the connection via (fig 1:260; [para 0034,0043]) connects to the covered top surface of the second test pad (fig 1:250; [para 0051]) and is surrounded by the bonding layer (fig 1:140,280; [para 0045]).
Regarding claim 14.
Kim in view of Chen teaches the electronic structure of Claim 12, further
Kim teaches:
the conductive via (fig 1:120; [para 0034,0043]) is in direct contact with the connection via (fig 1:260; [para 0034,0043]).
Claim(s) 13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0366856) in view of Chen (US 2021/0375721) as applied to claim 10 and further in view of Song (US 2024/0021553).
Regarding claim 13.
Kim in view of Chen teaches the electronic structure of Claim 10, above
Kim teaches:
interconnection pillar (fig 1:120,260; [para 0034,0043]) includes a conductive via (fig 1:120; [para 0034,0043]) and a connection vias (fig 1:260; [para 0034,0043]), and a width of each of the connection vias (fig 1:260; [para 0034,0043]) is less than a width of the conductive via (fig 1:120; [para 0034,0043]) wherein the conductive via (fig 1:120; [para 0034,0043]) extends through the first substrate (fig 1:110; [para 0032]) into the bonding layer (fig 1:140,280; [para 0045]), and the connection vias (fig 1:260; [para 0034,0043]) connect to the covered top surface of the second pad (fig 1:250; [para 0051]) and are surrounded by the bonding layer (fig 1:140,280; [para 0045]).
Chen teaches:
a second test pad (fig 1k,6:130a; [para 0023])
Song teaches:
The interconnection pillar (fig 1b:120S,130s,140,240; [para 0030]) includes a conductive via (fig 1b:220S,230s; [para 0030]) and a plurality of connection vias (fig 1b:140,240; [para 0030])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of connection pillars in order to control the resistance and capacitance in the connections between die (paragraph 34)
Regarding claim 15
Kim in view of Chen in view of song teaches the electronic structure of Claim 13
Kim teaches:
the conductive via (fig 1:120; [para 0034,0043]) is in direct contact with the connection via (fig 1:260; [para 0034,0043]).
Song teaches:
wherein the conductive via (fig 1b:220S,230s; [para 0030]) is in direct contact with the connection vias (fig 1b:140,240; [para 0030]).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any combination of references as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that Shih (US 2015/0228547) in view of Chen (US 2021/0375721) and Kim (US 2021/0366856) in view of Chen (US 2021/0375721) does not teach the elements of amended claims.
However, the references as newly applied in the rejection above teaches all elements of the claimed invention.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The applicant argues that Chen does not teach that the probe mark comprises a recess.
The applicant is incorrect. Chen explicitly states that the probe mark comprises a gouge (paragraph 23), a gouge is defined as a groove or cavity scooped out
The applicant argues that Shih does not teach the pad is embedded in the dielectric structure. The applicant is incorrect. Shih clearly and graphically teaches the pad (32,34) is embedded in the dielectric structure (24,36), see figure 5.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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