Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Currently, the title has been changed to:
“SEMICONDUCTOR DEVICE WITH ASYMMETRIC GATE DIELECTRIC LAYER AND METHOD FOR FABRICATING THE SAME”
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ohguro (Pub. No. US 2012/0205751 A1).
Regarding claim 1, Ohguro discloses a method for fabricating a semiconductor device, comprising: forming a gate structure 301-302-303/201-202 on a substrate 111 (Ohguro: paragraphs [0018]-[0019]); forming a first spacer 304 on the gate structure (Ohguro: paragraphs [0052]-[0053]); forming a patterned mask 311/312 on the gate structure and one side of the gate structure; removing the first spacer on another side of the gate structure (Ohguro: paragraphs [0054]-[0058]); and forming a source/drain region 121/122/124 adjacent to two sides of the gate structure (Ohguro: Figs. 3A-19B and paragraphs [0018]-[0024]).
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9-11, 13 and 15-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (Pub. No. US 2022/0367451 A1, herein Lin).
Regarding claim 9, Lin discloses a semiconductor device TR, comprising: a gate structure on a substrate, wherein the gate structure SKT comprises: a gate electrode MGT on the substrate; and a gate dielectric layer GOXT-HKT between the substrate and the gate electrode (Lin: Fig. 3M and paragraphs [0013]-[0015]), wherein the gate dielectric layer adjacent to one side of the gate electrode and the gate dielectric layer adjacent to another side of the gate electrode are asymmetrical; a first spacer ST adjacent to the gate structure; and a second spacer SPT adjacent to the first spacer (Lin: Figs. 2, 3M and paragraphs [0015]-[0017]).
Regarding claim 10, Lin discloses the semiconductor device of claim 9, wherein a width of the gate dielectric layer GOXT-HKT adjacent to one side of the gate structure and a width of the gate dielectric layer adjacent to another side of the gate structure are different (Lin: Figs. 2, 3M and paragraphs [0013]-[0015]).
Regarding claim 11, Lin discloses the semiconductor device of claim 9, wherein the first spacer ST adjacent to one side of the gate structure and the first spacer adjacent to another side of the gate structure are asymmetrical (Lin: Figs. 2, 3M and paragraphs [0013]-[0015]).
Regarding claim 13, Lin discloses the semiconductor device of claim 9, wherein the second spacer SPT adjacent to one side of the gate structure and the second spacer adjacent to another side of the gate structure are asymmetrical (Lin: Figs. 2, 3M and paragraphs [0013]-[0015]).
Regarding claim 15, Lin discloses the semiconductor device of claim 9, wherein the gate electrode comprises a metal gate (Lin: Figs. 2, 3M and paragraphs [0013]-[0015]).
Regarding claim 16, Lin discloses the semiconductor device of claim 9, wherein the gate electrode comprises: a high-k dielectric layer on the gate dielectric layer; a work function metal layer on the high-k dielectric layer; and a low resistance metal layer on the work function metal layer (Lin: Figs. 2, 3M and paragraphs [0050]-[0051).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ohguro in view of Wan et al. (Pub. No. US 2015/0214330 A1, herein Wan).
Regarding claim 8, Ohguro discloses the method of claim 1, further comprising: forming an interlayer dielectric (ILD) layer 211 around the gate structure (Ohguro: Figs. 3A-19B and paragraphs [0018]-[0024], [0032]), but does not specifically state performing a replacement metal gate (RMVG) process to transform the gate structure into a metal gate.
However, in the same field of endeavor, Wan discloses a method for fabricating a semiconductor device, comprising: forming a gate structure 103 on a substrate 102; forming a first spacer 110 on the gate structure, further comprising: forming an interlayer dielectric (ILD) layer around the gate structure; and performing a replacement metal gate (RMVG) process to transform the gate structure into a metal gate to reduce undesirable parasitic capacitance since such high capacitance can reduce a circuit speed and may cause slower ring oscillator (RO) speed and eventually lower circuit working frequency (Wan: paragraphs [0025], [0025]-[0026]).
Therefore, given the teachings of Wan, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Ohguro in view of Wan by employing the replacement metal gate process.
Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Kurjanowicz (Pub. No. US 2014/0209989 A1).
Regarding claims 12 and 14, Lin does not specifically show a width of the first spacer adjacent to one side of the gate structure and a width of the first spacer adjacent to another side of the gate structure are different, and a width of the second spacer adjacent to one side of the gate structure and a width of the second spacer adjacent to another side of the gate structure are different.
However, in the same field of endeavor, Kurjanowicz discloses a semiconductor device, comprising: a gate structure on a substrate, wherein the gate structure comprises: a gate electrode 106 on the substrate; and a gate dielectric layer 102 between the substrate and the gate electrode, wherein the gate dielectric layer adjacent to one side of the gate electrode and the gate dielectric layer adjacent to another side of the gate electrode are asymmetrical; a spacer 108 adjacent to the gate structure, wherein a width of the spacer adjacent to one side of the gate structure and a width of the first spacer adjacent to another side of the gate structure are different (Kurjanowicz: Fig. 4 and paragraphs [0065]-[0066]) providing high reliability, zero standby power, high temperature stability and no need for complex read schemes.
Therefore, given the teachings of Kurjanowicz, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Lin in view of Kurjanowicz by employing the width difference for the first and second spacers adjacent to the gate structure.
Allowable Subject Matter
Claims 2-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 2, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, further comprising: forming a gate dielectric layer on the substrate; forming a gate material layer on the gate dielectric layer; patterning the gate material layer to form the gate structure; forming the first spacer on the gate structure; forming a second spacer on the first spacer; forming a sacrificial layer on the second spacer; removing the sacrificial layer, the second spacer, and the first spacer on another side of the gate structure; forming a third spacer on the second spacer; and forming the source/drain region. Claims 3-7 are included likewise as they depend from claim 2.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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January 3, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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