DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Claims 1-10 in the reply filed on 1/12/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 8-10 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Moon et al (US 2022/0149132).
The applied reference has a common inventor with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
With respect to Claim 1, Moon et al discloses a display apparatus (Figures 1 and 11) comprising: a substrate (Figure 1, 100) including a display area (Figure 1, DA) and a peripheral area (Figure 1, PA) outside the display area; a pixel circuit (Figure 3 and Figure 11, paragraph 108) disposed in the display area (Figure 1, DA) and including a driving thin-film transistor (Figure 11, T1) and a switching thin-film transistor (Figure 11, T2) , wherein the driving thin-film transistor includes a driving semiconductor layer (Figure 11, A1), and the switching thin-film transistor includes a switching semiconductor layer (Figure 11, A2); a display element (Figure 11, OLED) connected to the pixel circuit (Figure 3 and Figure 11, paragraph 108)); and a built-in driving circuit portion (Figure 1A, 40) disposed in the peripheral area (Figure 1A, PA) and including a first peripheral thin-film transistor (Figure 11,Tp) including a first peripheral semiconductor layer (Figure 11, A3), where the driving semiconductor layer and the switching semiconductor layer include a same material (paragraph 9) and each have a mobility less than a mobility of the first peripheral semiconductor layer (paragraph 174). See Figures 1A, 3 and 11 and corresponding text, especially paragraphs 51-75 and 158-179.
With respect to Claim 2, Moon et al discloses wherein the driving semiconductor layer and the switching semiconductor layer are each thicker than the first peripheral semiconductor layer. See paragraph 10.
With respect to Claim 3, Moon et al discloses wherein a thickness of the driving semiconductor layer and a thickness of the switching semiconductor layer are the same. See Figure 11, A1 and A2, and paragraph 97.
With respect to Claim 8, Moon et al discloses wherein each of the driving semiconductor layer and the switching semiconductor layer includes indium-gallium-zinc-oxide (InGaZnO). See Figure 91 and 161.
With respect to Claim 9, Moon et al discloses wherein the first peripheral semiconductor layer includes indium-tin-gallium-zinc-oxide (InSnGaZnO). See paragraph 172.
With respect to Claim 10, Moon et al further discloses comprising a bias electrode disposed on the substrate to correspond to the driving thin-film transistor. See paragraph 75.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al (US 2022/0149132).
Moon et al is relied upon as discussed above.
Moreover, with respect to Claims 4-5, Moon et al discloses a gate insulating layer over the semiconductor layers in the transistors. See Figure 11, 113 and corresponding text.
However, with respect to Claims 4-5, Moon et al does not disclose the claimed first and second insulating layers.
It would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to use first and second gate insulating layers in the device of Moon et al, as the configuration of first and second gate insulating layers is well known in the art. The Examiner takes Official Notice that the use of the first and second gate insulating layers is notoriously well known in the art.
With respect to Claim 4, Moon et al makes obvious the limitation “ further comprising a first gate insulating layer disposed under the driving semiconductor layer and the switching semiconductor layer and disposed on the first peripheral semiconductor layer”, as the configuration of first and second insulating layers is well known in the art. The Examiner takes Official Notice that the use of the first and second gate insulating layers is notoriously well known in the art.
With respect to Claim 5, Moon et al discloses further comprising a second gate insulating layer disposed on the driving semiconductor layer and the switching semiconductor layer in the display area and disposed on the first gate insulating layer in the peripheral area. See Figure 11, 113 and corresponding text.
With respect to Claims 6-7, Moon et al differs from the Claims at hand in that Moon et al does not disclose “wherein the built-in driving circuit portion includes a second peripheral thin-film transistor including a second peripheral semiconductor layer, and the second peripheral semiconductor layer includes a same material as a material of the driving semiconductor layer and the switching semiconductor layer” and “wherein a thickness of the second peripheral semiconductor layer is the same as a thickness of the driving semiconductor layer and the switching semiconductor layer”.
It would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to form a second peripheral thin-film transistor having a semiconductor layer of the same thickness, as duplication of parts for their known benefit, would have been prima facie obvious in the absence of unobvious results. See In re Harza, 124 USPQ 378 (CCPA 1960).
With respect to Claim 6, Moon et al makes obvious the limitation “wherein the built-in driving circuit portion includes a second peripheral thin-film transistor including a second peripheral semiconductor layer, and the second peripheral semiconductor layer includes a same material as a material of the driving semiconductor layer and the switching semiconductor layer”, as duplication of parts for their known benefit, would have been prima facie obvious in the absence of unobvious results. See In re Harza, 124 USPQ 378 (CCPA 1960).
With respect to Claim 7, Moon et al makes obvious the limitation “wherein a thickness of the second peripheral semiconductor layer is the same as a thickness of the driving semiconductor layer and the switching semiconductor layer”, as duplication of parts for their known benefit, would have been prima facie obvious in the absence of unobvious results. See In re Harza, 124 USPQ 378 (CCPA 1960).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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AGG
February 24, 2026
/ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812