Prosecution Insights
Last updated: May 29, 2026
Application No. 18/373,853

PACKAGE STRUCTURE

Non-Final OA §102
Filed
Sep 27, 2023
Examiner
ULLAH, ELIAS
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Semiconductor Engineering Inc.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
709 granted / 838 resolved
+16.6% vs TC avg
Moderate +8% lift
Without
With
+8.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
14 currently pending
Career history
856
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.2%
+9.2% vs TC avg
§102
46.9%
+6.9% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 838 resolved cases

Office Action

§102
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sakamoto et al. (Sakamoto, US 6,562,660 B1). Regarding claim 1, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A), comprising: a substrate ( substrate 84 shown in FIG. 23A); a first electronic component ( chip 52A/ B in FIG. 8) disposed over the substrate (substrate 84); an interposer ( conductive element 59 in FIG. 23A) disposed over the substrate (substrate 84); a conductive wire (wire 55a) connecting the first electronic component ( chip 52A/B) to the interposer; and a conductive adhesive ( conductive element 51A in FGU. 23A) connecting the interposer to the substrate (substrate 84). Regarding claim 2, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A), comprising, wherein the conductive adhesive partially covers the interposer (see FIG. 23A). Regarding claim 3, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A), comprising, wherein the interposer (conductive element 59) comprises a first conductive pad connected to the conductive wire and at least partially exposed by the conductive adhesive (see FIG. 23A). Regarding claim 4, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A), comprising, wherein a height of the first electronic component (chip 52) is greater than a height of the interposer (conductive element 59). Regarding claim 5, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A), comprising, wherein the conductive adhesive (conductive element 51) comprises an anisotropic conductive adhesive (product by process). Regarding claim 6, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A), comprising: wherein the conductive adhesive extends continuously from a lateral sidewall of the first electronic component to a lateral sidewall of the interposer in a cross-sectional view perspective (see FIG. 23 with respect to FIG. 23B). Regarding claim 7, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A), comprising, wherein an elevation of a contact between the conductive wire and the first electronic component is higher than an elevation of a contact between the conductive wire and the interposer with respect to the substrate (see FIG. 23 with respect to FIG. 23B. Regarding claim 8, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A), comprising, wherein a second electronic component (chip 52B) disposed over the substrate and flip-chip bonded ( chip 52B in FGI. 13) to the substrate through the conductive adhesive (see FIG.13). Regarding claim 9, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A), comprising: a substrate (substrate 84); a first electronic component (chip 52) disposed over the substrate (substrate 84), the first electronic component having a first surface facing the substrate and a second surface opposite to the first surface (see FIG. 23A); a second electronic component disposed over the substrate, the second electronic component having a third surface facing the substrate and comprising a first electrode on the third surface (see FIG. 23A with respect to FIG. 13); a conductive wire electrically connecting the second surface to the substrate; a first conductive adhesive connecting the first surface to the substrate; and a second conductive adhesive connecting the first electrode on the third surface to the substrate (see FIG. 13 with respect to FIG. 23A). Regarding claim 10, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A),comprising an interposer electrically connecting the conductive wire to the substrate (see FIG. 13 with respect to FIG. 23A). Regarding claim 11, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A),comprising, wherein the first conductive adhesive is between the interposer and the substrate and connected to the interposer and the substrate (see FIG. 13 with respect to FIG. 23A). Regarding claim 12, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A),comprising, wherein the interposer has a lateral surface, the first conductive adhesive comprises an insulating structure and a conductive portion, and the conductive portion is protruded beyond the lateral surface of the interposer (see FIG. 13 with respect to FIG. 23A). Regarding claim 13, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A),comprising, wherein the second electronic component further comprises a second electrode connected to the substrate through the second conductive adhesive (see FIG. 13 with respect to FIG. 23A). Regarding claim 14, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A),comprising, wherein the first electronic component comprises an electrode on the first surface, and the electrode is connected to the substrate through the first conductive adhesive (see FIG. 13 with respect to FIG. 23A). Regarding claim 15, Sakamoto shows a package structure ( FIG. 2B and FIG. 23A),comprising, wherein the first conductive adhesive is spaced apart from the second conductive adhesive (see FIG. 13 with respect to FIG. 23A). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dubin ( US 8,933,473) Regarding claim 16, Dubin shows a package structure, comprising: a substrate; a light-emitting array disposed over the substrate, the light-emitting array comprising a plurality of first light-emitting elements flip-chip bonded to the substrate and a plurality of second light-emitting elements wire-bonded to the substrate; and a plurality of interposers disposed over the substrate, wherein the second light-emitting elements are wire-bonded to the substrate through the interposers (see FIG. 3D and related text). Regarding claim 17, Dubin shows a package structure, comprising wherein an elevation of a first light- emitting source of one of the first light-emitting elements is lower than an elevation of a second light-emitting source of one of the second light-emitting elements with respect to the substrate (see FIG. 3D and related text). Regarding claim 18, Dubin shows a package structure, comprising wherein the one of the first light-emitting elements comprises two electrodes on a same side of the first light-emitting source, and the one of the second light-emitting elements comprises two electrodes on opposite sides of the second light-emitting source see FIG. 3D and related text). Regarding claim 19, Dubin shows a package structure, comprising wherein one of the first light-emitting elements and one of the second light-emitting elements are adjacent to each other, and one of the interposers connected to the one of the second light-emitting elements is disposed between the one of the first light-emitting elements and the one of the second light-emitting elements from a top view perspective (see FIG. 3D and related text). Regarding claim 20, Dubin shows a package structure, comprising wherein the one of the second light- emitting elements is closer to the one of the interposers than to the one of the first light- emitting elements (see FIG. 3D and related text). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS ULLAH/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Sep 27, 2023
Application Filed
Feb 05, 2026
Non-Final Rejection mailed — §102
Apr 20, 2026
Interview Requested
Apr 28, 2026
Examiner Interview Summary
Apr 28, 2026
Applicant Interview (Telephonic)
May 05, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12642152
POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR PRODUCING A POWER SEMICONDUCTOR MODULE ARRANGEMENT
3y 0m to grant Granted May 26, 2026
Patent 12642145
SEMICONDUCTOR PACKAGE
2y 8m to grant Granted May 26, 2026
Patent 12642124
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
2y 9m to grant Granted May 26, 2026
Patent 12635580
SEMICONDUCTOR PACKAGES
3y 1m to grant Granted May 19, 2026
Patent 12635551
CHIP PACKAGE STRUCTURE
2y 9m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
93%
With Interview (+8.0%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 838 resolved cases by this examiner. Grant probability derived from career allowance rate.

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