DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: GATE ARRANGEMENT FOR QUANTUM DOT STRUCTURES
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Base claims 1, 13 and 20 each recite “spin qbit gates” and it is not clear from the disclosure what it means, as any gates in a spin-qubit device may be considered “spin qbit gates”. More specifically, t is not clear what makes a gate a "qubit gate", nor what makes a "qubit gate" a "spin qubit gate". For the same reason, it is also not clear what an “access gate” or “barrier gate” is and how their structure and/or function is different form a “spin qbit gate”. For the purposes of this office action, any gate can read on “spin qbit gates” or “barrier gate” or “access gate”.
Base claim 13 recites “self-aligned barrier gates”. However, the feature “self-aligned” of a gate is part of a manufacturing process, while claim 13 is a product claim. It is not clear how one would necessary recognize a gate that was manufactured with a self-alignment feature after it has been manufactured. For the purposes of this office action, any barrier gate that is capable of being manufactured using any self-alignment method to align to any structure would be considered to read on “self-aligned barrier gate”. Similar recitation is also in claim 2.
Claims 11 and 16 each recite “high-k metal” and it is not clear what this means. Typically, k refers to a high dielectric constant and high-k typically means a dielectric material, not a metal. For the purposes of this office action, the recitation “high-k metal gate” will be considered equivalent to a “high-k metal gate”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 8-9, 11, 13-14, 16-17 and 19-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kotlyar (US 20220190135), hereinafter Kotlyar.
Regarding claim 1, Kotlyar (refer to Figures 1-3) teaches a structure (100, described as " quantum dot device 100" in para 25) comprising:
a plurality of barrier gates (108, shown as 108-1, 108-2, 108-3, see para 31 and para 45; best seen in Figure 2);
a plurality of spin (see para 32) qubit gates (inner 106, such as 106-2 – best seen in Figure 2, described as " inner gates 106 in which quantum dots 142 may form" in para 40; also see para 45) interdigitated (i.e. meshed with each other – best seen in Figures 2 and 3) with the plurality of barrier gates (108) (see Figs, 2, 3); and
access gates (the outer gates 106, such as 106-1 and 106-3, see para 40, especially 1st sentence) on opposing sides of the plurality of barrier gates (108).
Regarding claim 2, Kotlyar (refer to Figures 1-3) teaches the structure of claim 1, wherein the plurality of barrier gates (108) are self-aligned (108 are self-aligned with the 106 - see the method in Figs. 17-22; also see 35 USC 112, 2nd paragraph rejection) barrier gates physically isolated (para 39, especially 2nd last sentence) from the plurality of spin qubit gates (106). Whereas claim 2 is a product claim, the claim recites a method of steps therein, i.e. “self-aligned” (also explained in 35 USC 112, 2nd paragraph rejection above). Therefore, the claim amounts to a product by process claim. "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113. This applies to all claims that recited “self-aligned”.
Regarding claim 3, Kotlyar (refer to Figures 1-3) teaches the structure of claim 1, wherein the plurality of barrier gates (108), the plurality of spin qubit gates (inner 106) and the access gates are contacted (i.e. gate contact or electrode) that is capable of being independently biased (such as through conductive vias 120, see para 46 and Figure 3).
Regarding claim 4, Kotlyar (refer to Figures 1-3) teaches the structure of claim 1, wherein the plurality of barrier gates (108) comprise metal material (described as “gate metal” in para 32) surrounded by insulator material, which isolates the plurality of barrier gates from the plurality of spin qubit gates (para 39, especially 2nd last sentence).
Regarding claim 6, Kotlyar (refer to Figures 1-3) teaches the structure of claim 1, further comprising a liner material (described as "intervening insulating material 130 " in para 39) provided between the plurality of barrier gates and the plurality of spin qubit gates and access gates (para 39, especially 2nd last sentence).
Regarding claim 8, Kotlyar (refer to Figures 1-3) teaches the structure of claim 1, further comprising source and drain regions (140 – best seen in figure 2) adjacent to the access gates (para 40).
Regarding claim 9, Kotlyar (refer to Figures 1-3) teaches the structure of claim 1, wherein the barrier gates (108) are symmetrically positioned (best seen in Figure 2 or 3) with respect to the plurality of spin qubit gates (inner 106) and the access gates (outer 106).
Regarding claim 11, Kotlyar (refer to Figures 1-3) teaches the structure of claim 1, wherein the plurality of spin qubit gates comprise high-k metal gate structures (see para 107 which discloses gate may comprise "high-k dielectric, such as hafnium oxide").
Regarding claim 13, Kotlyar (refer to Figures 1-3) teaches a structure comprises: spin qubit gates (inner 106, such as 106-2 – best seen in Figure 2, described as " inner gates 106 in which quantum dots 142 may form" in para 40; also see para 45); self-aligned (see note below) barrier gates (108, shown as 108-1, 108-2, 108-3, see para 31 and para 45; best seen in Figure 2) interdigitated (i.e. meshed with each other – best seen in Figures 2 and 3) with the plurality of spin qubit gates;
access gates (the outer gates 106, such as 106-1 and 106-3, see para 40, especially 1st sentence) on opposing sides of the barrier gates;
source and drain regions (140 – best seen in figure 2) adjacent to the access gates (para 40); and
a liner material (described as "intervening insulating material 130 " in para 39) separating the spin qubit gates, the self-aligned barrier gates and the access gates from one another, and the access gates from the source and drain regions (para 39).
Regarding the limitation “self-aligned”, note that108 are self-aligned with the 106 - see the method in Figs. 17-22; also see 35 USC 112, 2nd paragraph rejection).
Regarding claim 14, Kotlyar (refer to Figures 1-3) teaches the structure of claim 13, wherein the self-aligned (best seen in Figure 2 or 3) barrier gates (108) are symmetric about the plurality of qubit gates (106).
Regarding claim 16, it is substantially similar to claim 11, and hence the rejection is substantially similar.
Regarding claim 17, Kotlyar (refer to Figures 1-3) teaches the structure of claim 13, wherein the self-aligned barrier gates comprise metal material (described as “interface material 141 may be a metal” or silicide – see para 42) surrounded by insulator material (described as "intervening insulating material 130 " in para 39).
Regarding claim 19, it is substantially similar to claim 3, and hence the rejection is substantially similar.
Regarding claim 20, all limitations have been addressed in claim 1, as the claims are substantially similar.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5, 7, 10, 12, 15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kotlyar.
Regarding claim 5, Kotlyar (refer to Figures 1-3) teaches the structure of claim 1, wherein the plurality of barrier gates comprise a conductive material surrounded by insulator material, which isolates the plurality of barrier gates from the plurality of spin qubit gates (as explained for claim 4 where conductive material is metal; also see “intervening insulating material 130” described in para 39), but does not teach that the conductive material is “polysilicon”. However, use of polysilicon as gate electrode is well known as highly doped polysilicon is a good conductor while offering better match of coefficient of thermal expansion with other interfacing semiconductor materials. It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention so that the conductive material is “polysilicon”. The ordinary artisan would have been motivated to modify Kotlyar for at least the purpose of using a known alternate conductive material, which is a good conductor while offering the advantage of better match of coefficient of thermal expansion with other interfacing semiconductor materials, thus reducing stress in the device due to thermal cycling loads.
Regarding claim 7, Kotlyar (refer to Figures 1-3) teaches the structure of claim 1, but does not teach wherein the access gates are “larger than” the plurality of barrier gates and the plurality of spin qubit gates. However, use of larger gates is known for improved gate performance in terms of ability to handle larger current or for faster operation compared to smaller gates that have to be miniaturized. It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention so that he access gates are “larger than” the plurality of barrier gates and the plurality of spin qubit gates. The ordinary artisan would have been motivated to modify Kotlyar for at least the purpose of using a known alternate conductive material, which is a good conductor while offering the advantage of better match of coefficient of thermal expansion with other interfacing semiconductor materials, thus reducing stress in the device due to thermal cycling loads.
Regarding claim 10, Kotlyar (refer to Figures 1-3) teaches the structure of claim 1, but does not teach wherein the plurality of spin qubit gates comprise a conductive material such as metal or silicon based material (para 42) but does not teach that the conductive material is “polysilicon”. However, use of polysilicon as gate electrode is well known as highly doped polysilicon is a good conductor while offering better match of coefficient of thermal expansion with other interfacing semiconductor materials. It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention so that the conductive material is “polysilicon”. The ordinary artisan would have been motivated to modify Kotlyar for at least the purpose of using a known alternate conductive material, which is a good conductor while offering the advantage of better match of coefficient of thermal expansion with other interfacing semiconductor materials, thus reducing stress in the device due to thermal cycling loads.
Regarding claim 12, Kotlyar (refer to Figures 1-3) teaches the structure of claim 1, but does not teach wherein the plurality of spin qubit gates, the access gates and the plurality of barrier gates are provided “on a semiconductor-on-insulator (SOI)” substrate. Cheng (US 20070045697) teaches that for substrates, semiconductor-on-insulator (SOI) technology offers many advantages over counterpart devices built in bulk semiconductor substrates including, but not limited to, higher performance, absence of latch-up, higher packing density, and low voltage applications (see para 8 of Cheng). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention so that the plurality of spin qubit gates, the access gates and the plurality of barrier gates are provided “on a semiconductor-on-insulator (SOI)” substrate. The ordinary artisan would have been motivated to modify Kotlyar for at least the purpose of realizing known advantages of semiconductor-on-insulator (SOI) technology, such as higher performance, absence of latch-up, higher packing density, and low voltage applications (see para 8 of Cheng).
Regarding claim 15, Kotlyar (refer to Figures 1-3) teaches the structure of claim 13, wherein the spin qubit gates comprise a conductive material that may be metal or other material (para 42) with a silicide on top (such as “nickel silicide” – see para 42) of all the gates, but does not teach that the conductive material is “polysilicon”. However, use of polysilicon as gate electrode is well known as highly doped polysilicon is a good conductor while offering better match of coefficient of thermal expansion with other interfacing semiconductor materials. It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention so that the conductive material is “polysilicon”. The ordinary artisan would have been motivated to modify Kotlyar for at least the purpose of using a known alternate conductive material, which is a good conductor while offering the advantage of better match of coefficient of thermal expansion with other interfacing semiconductor materials, thus reducing stress in the device due to thermal cycling loads.
Regarding claim 18, Kotlyar (refer to Figures 1-3) teaches the structure of claim 13, wherein the self-aligned barrier gates comprise a conductive material (para 42) surrounded by insulator material (described as "intervening insulating material 130 " in para 39), but does not teach that the conductive material is “polysilicon”. However, use of polysilicon as gate electrode is well known as highly doped polysilicon is a good conductor while offering better match of coefficient of thermal expansion with other interfacing semiconductor materials. It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention so that the conductive material is “polysilicon”. The ordinary artisan would have been motivated to modify Kotlyar for at least the purpose of using a known alternate conductive material, which is a good conductor while offering the advantage of better match of coefficient of thermal expansion with other interfacing semiconductor materials, thus reducing stress in the device due to thermal cycling loads.
Conclusion
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/AJAY ARORA/Primary Examiner, Art Unit 2892