Prosecution Insights
Last updated: April 19, 2026
Application No. 18/374,284

DISPLAY DEVICE

Non-Final OA §102§103
Filed
Sep 28, 2023
Examiner
STEPHENSON, KENNETH STEPHEN
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
3y 1m
To Grant
99%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
4 granted / 5 resolved
+12.0% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
32 currently pending
Career history
37
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
39.6%
-0.4% vs TC avg
§102
24.8%
-15.2% vs TC avg
§112
26.7%
-13.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 5 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species I, Fig. 5 – 7 & 16F, in the reply filed on 9 December 2025 is acknowledged. Applicant’s withdrawal of Claims 9, 13, 18, & 20 pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9 December 2025. Examiner further withdraws Claims 10 – 12, 14, 19 & 21 pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9 December 2025. Regarding Claim 10, this claim recites the limitation “wherein each of the plurality of trace lines includes: a first sub-layer disposed in a same layer as the anode and including a same material as the anode; and a second sub-layer disposed under the first sub-layer and electrically connected with the first sub-layer, wherein the second sub-layer is included in the circuit layer”. This limitation does not describe the trace lines of the elected species (e.g. Fig. 7: TL2). This limitation does, however, describe the trace lines of another figure (Fig. 12: TLa), which may describe the trace lines of the nonelected Species II (Fig. 8B: TL2a), as both TLa and TL2a are under the under barrier wall PW where TL2 is not under barrier wall PW. Regarding Claim 11, this claim recites the limitation, “wherein the plurality of touch electrodes are disposed over the barrier wall and insulated from the barrier wall”. This limitation does not describe the relationship between the plurality of touch electrodes and the barrier wall for the elected Species I. In the elected Species I, “each of the plurality of touch electrodes TSP may include a corresponding barrier wall pattern among the plurality of barrier wall patterns PW1, PW2, PW3, PW4, and PW5” (Par. 155) where “the barrier wall PW may include the plurality of barrier wall patterns PW1, PW2, PW3, PW4, and PW5” (Par. 154). Regarding Claim 12, this claim is dependent upon Claim 11. Regarding Claim 14, this claim recites the limitation “a protrusion surrounding at least a portion of a hole defined in the base layer in a plan view”. This limitation is only portrayed in Fig. 13B, which also portrays trace line TL2 under barrier wall PW. The latter may describe trace line TL2a of the nonelected Species II (Fig. 8B), as both TL2a and TL2 are under barrier wall PW. However, this cannot be drawn to the elected Species I (Fig. 7) where trace line TL2 is not under barrier wall PW. Regarding Claim 19, this claim recites the limitation “wherein each of the plurality of trace lines includes: a first sub-layer disposed in a same layer as the plurality of anodes and including a same material as the plurality of anodes; and a second sub-layer disposed under the first sub-layer and electrically connected with the first sub-layer, wherein the second sub-layer is included in the circuit layer”. This limitation does not describe the trace lines of the elected species (e.g. Fig. 7: TL2). This limitation does, however, describe the trace lines of another figure (Fig. 12: TLa), which may describe the trace lines of the nonelected Species II (Fig. 8B: TL2a), as both TLa and TL2a are under the under a barrier wall PW where TL2 is not. Regarding Claim 21, this claim recites the limitation “a protrusion surrounding at least a portion of a hole defined in the base layer in a plan view”. This limitation is only portrayed in Fig. 13B, which also portrays trace line TL2 under barrier wall PW. The latter may describe trace line TL2a of the nonelected Species II (Fig. 8B), as both TL2a and TL2 are under barrier wall PW. However, this cannot be drawn to the elected Species I (Fig. 7) where trace line TL2 is not under barrier wall PW. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 28 September 2023 has been considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: TOUCH OLED DISPLAY WITH INDIVIDUAL SUBPIXEL CATHODES Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 4 – 8, & 15 – 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM (US 20210367015 A1). Regarding Claim 1, KIM discloses: A display device (Fig. 4: 1; Par. 78) comprising: a base layer (Fig. 4: 101; Par. 80); a circuit layer (Fig. 4: 111/112/113/114; Par. 82 – 89) disposed on the base layer; (Fig. 4: 111/112/113/114 is disposed on 101.) an anode (Fig. 4: A given 121; Par. 91) disposed on the circuit layer; (Fig. 4: A given 121 is disposed on 111/112/113/114.) a pixel defining layer (Fig. 4: CPL; Par. 93) disposed on the circuit layer, (Fig. 4: CPL is disposed on 111/112/113/114.) wherein a light emitting opening (Fig. 4: A given lateral gap in the CPL) is defined in the pixel defining layer to overlap the anode; (Fig. 4: A given lateral gap in the CPL is defined in the CPL to overlap a given corresponding 121.) a barrier wall (Fig. 4: Combined PDLs; Par. 93) disposed on the pixel defining layer, (Fig. 4: The combined PDLs are disposed on the CPL.) wherein a barrier opening (Fig. 4: A given lateral gap in the combined PDLs) is defined in the barrier wall to overlap the light emitting opening; (Fig. 4: A given lateral gap in the combined PDLs is defined in the combined PDLs to overlap a given corresponding lateral gap in the CPL.) a thin film encapsulation layer (Fig. 4: 116; Par. 111) disposed over the circuit layer to cover the anode, the pixel defining layer, and the barrier wall; (Fig. 4: 116 is disposed over 111/112/113/114 to cover a given 121, the CPL, and the combined PDLs.) and a plurality of touch electrodes (Fig. 4: Individual PDLs and 123, annotated hereafter as PDL/123. That is, the plurality of touch electrodes share a single cathode 123.) disposed between the circuit layer and the thin film encapsulation layer. (Fig. 4: The plurality of PDL/123 are disposed between 111/112/113/114 and 116.) Regarding Claim 2, KIM discloses: The display device of claim 1, further comprising: an emission pattern (Fig. 4: A given 122; Par. 73) disposed on the anode; (Fig. 4: A given 122 is disposed on a given corresponding 121.) and a cathode (Fig. 4: 123; Par. 108) disposed on the emission pattern and in contact with the barrier wall. (Fig. 4: 123 is disposed on a given 122 and in contact with the combined PDLs.) Regarding Claim 4, KIM discloses: The display device of claim 1, wherein the barrier wall includes a plurality of barrier wall patterns (Fig. 4: Individual PDLs) spaced apart from each other. (Fig. 4: The combined PDLs includes a plurality of individual PDLs spaced apart from each other.) Regarding Claim 5, KIM discloses: The display device of claim 4, wherein each of the plurality of touch electrodes includes a corresponding barrier wall pattern among the plurality of barrier wall patterns. (Fig. 4: Each of the plurality of PDL/123 includes a corresponding individual PDL among the plurality of individual PDLs.) Regarding Claim 6, KIM discloses: The display device of claim 1, wherein a common voltage is provided to the plurality of touch electrodes in a first mode, and a touch sensing signal is provided to the plurality of touch electrodes in a second mode different from the first mode. (This limitation is with respect to the manner in which the claimed device is intended to be used and does not differentiate the claimed device from the device disclosed by KIM, as KIM teaches all of the structural limitations of this claim, MPEP 2144 II.) Regarding Claim 7, KIM discloses: The display device of claim 6, wherein each of the plurality of touch electrodes is electrically connected with a first transistor and a second transistor, (Fig. 4: Each of the PDL/123 is electrically connected with 123, which is electrically connected with the plurality of 122s, which is electrically connected with the plurality of 121s, which is electrically connected with the plurality of transistors TR.) and the first transistor transfers the common voltage to the plurality of touch electrodes in the first mode and transfers the touch sensing signal to the plurality of touch electrodes in the second mode. (This limitation is with respect to the manner in which the claimed device is intended to be used and does not differentiate the claimed device from the device disclosed by KIM, as KIM teaches all of the structural limitations of this claim, MPEP 2144 II.) Regarding Claim 8, KIM discloses: The display device of claim 1, further comprising: a plurality of trace lines (Fig. 4: The filled vias electrically connecting a given DE and a corresponding given 121.) electrically connected with the plurality of touch electrodes. (Fig. 4: The plurality of trace lines is electrically connected with the plurality of 121s, which are electrically connected with the plurality of 122s, which are electrically connect with 123, which is electrically connected with the plurality of PDL/123.) Regarding Claim 15, KIM discloses: A display device (Fig. 4: 1; Par. 78) comprising: a base layer (Fig. 4: 101; Par. 80); a circuit layer (Fig. 4: 111/112/113/114; Par. 82 – 89) disposed on the base layer; (Fig. 4: 111/112/113/114 is disposed on 101.) a plurality of anodes (Fig. 4: 121s) disposed on the circuit layer; (Fig. 4: 121s are disposed on 111/112/113/114.) a pixel defining layer (Fig. 4: CPL; Par. 93) disposed on the circuit layer, (Fig. 4: CPL is disposed on 111/112/113/114.) wherein light emitting openings (Fig. 4: Lateral gaps in the CPL) are defined in the pixel defining layer to overlap the plurality of anodes; (Fig. 4: The lateral gaps in the CPL are defined in the CPL to overlap the 121s.) a barrier wall (Fig. 4: Combined PDLs; Par. 93) disposed on the pixel defining layer, (Fig. 4: The combined PDLs are disposed on the CPL.) wherein barrier openings (Fig. 4: Lateral gaps in the combined PDLs) are defined in the barrier wall to overlap the light emitting openings; (Fig. 4: The lateral gaps in the combined PDLs are defined in the combined PDLs to overlap the lateral gaps in the CPL.) a plurality of intermediate layers (Fig. 4: 122s) disposed on the plurality of anodes and accommodated in the light emitting openings; (Fig. 4: The 122s are disposed on the 121s and accommodated in the lateral gaps in the CPL.) and an electrode layer (Fig. 4: 123) disposed on the plurality of intermediate layers, (Fig. 4: 123 is disposed on the 122s.) wherein a common voltage is provided to the electrode layer in a first mode, and a touch sensing signal is provided to the electrode layer in a second mode different from the first mode. (This limitation is with respect to the manner in which the claimed device is intended to be used and does not differentiate the claimed device from the device disclosed by KIM, as KIM teaches all of the structural limitations of this claim, MPEP 2144 II.) Regarding Claim 16, KIM discloses: The display device of claim 15, wherein the barrier wall includes a plurality of barrier wall patterns (Fig. 4: Individual PDLs) spaced apart from each other, (Fig. 4: The combined PDLs includes a plurality of individual PDLs spaced apart from each other.) and wherein the electrode layer includes a plurality of touch electrodes (Fig. 4: Individual PDLs and 123, annotated hereafter as PDL/123. That is, the plurality of touch electrodes share a single cathode 123.), (Fig. 4: 123 includes a plurality of PDL/123) each of which is electrically connected with a corresponding barrier wall pattern among the plurality of barrier wall patterns. (Fig. 4: Each PDL/123 is electrically connected, Par. 100, with a corresponding individual PDL among the plurality of individual PDLs.) Regarding Claim 17, KIM discloses: The display device of claim 16, wherein each of the plurality of touch electrodes is electrically connected with a first transistor and a second transistor, (Fig. 4: Each of the PDL/123 is electrically connected with 123, which is electrically connected with the plurality of 122s, which is electrically connected with the plurality of 121s, which is electrically connected with the plurality of transistors TR.) and the first transistor transfers the common voltage to the plurality of touch electrodes in the first mode and transfers the touch sensing signal to the plurality of touch electrodes in the second mode. (This limitation is with respect to the manner in which the claimed device is intended to be used and does not differentiate the claimed device from the device disclosed by KIM, as KIM teaches all of the structural limitations of this claim, MPEP 2144 II.) Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of YOUNG (KR 20160137715 A). Regarding Claim 3, KIM does not discloses: The display device of claim 2, wherein the cathode includes a plurality of cathodes, and each of the plurality of touch electrodes includes a corresponding cathode among the plurality of cathodes. YOUNG, though, does disclose: wherein the cathode (Fig. 5: Combined 480s; Pag. 4 Par. 6) includes a plurality of cathodes (Fig. 5: Individual 480s), and each of the plurality of touch electrodes (Fig. 5: Individual 480s and corresponding individual 510/515a, hereinafter denoted as 480/510/515a, Pag. 5 Par. 6. Further, each touch electrode corresponds to a given subpixel, Pag. 5 Par. 6, each pixel comprises at least one subpixel, Pag. 3 last paragraph, and there are a plurality of pixels, Pag. 3 Par. 7. Therefore, there are a plurality of touch electrodes.) includes a corresponding cathode among the plurality of cathodes. (Fig. 5: Each 480/510/510a includes a corresponding 480 among the plurality of 480s.) Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of KIM with those of YOUNG to enable the cathode to include a plurality of cathodes, and each of the plurality of touch electrodes to include a corresponding cathode among the plurality of cathodes in KIM according to the teachings of YOUNG for the further advantage of avoiding “a voltage drop due to the specific resistance of the cathode”, particularly as the size of the display device increases (YOUNG Pag. 3 Par. 2). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST).. Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview—preferably at 4 P.M. (EST)—applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Sep 28, 2023
Application Filed
Mar 05, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604712
METHOD OF FORMING ACTIVE REGION OF SEMICONDUCTOR DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12604713
METHOD OF FORMING MASK WITH REDUCED FEATURE SIZES
2y 5m to grant Granted Apr 14, 2026
Patent 12599012
Free Configurable Power Semiconductor Module
2y 5m to grant Granted Apr 07, 2026
Patent 12593468
SELF-ALIGNED BACKSIDE CONTACT WITH INCREASED CONTACT AREA
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 4 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
99%
With Interview (+33.3%)
3y 1m
Median Time to Grant
Low
PTA Risk
Based on 5 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month