DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
(Text within parentheses is either a missing or a corrected information to character(s) in bold.)
[0028] … Embodiments of the present disclosure describe systems, methods, and apparatuses for low-latency aligned data st(r)eams between chiplets through UCIe interface modules, while also supporting certain specialized protocols (e.g., high-speed transceiver protocols).
[00114] … Also, data from the third and fourth GTs is aligned by the alignment module 476 before they(it) is provided to the UCIe interface modules 425C and 425D.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 8-11, 16-18, and 20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Anwar Kashem et. al. (US 20230205252 A1) hereinafter Kashem.
Regarding claim 1
Kashem discloses
A system, comprising
(Kashem, p. 1, [0010] “Systems and methods are provided for clock delay compensation in a multi-chip system.”)
a first chiplet comprising a first transceiver and a first chiplet-to-chiplet (C2C) interface module
(Kashem, p. 3, [0021] “… Furthermore, when a logic unit interfaces with another logic unit that is integrated into another chip 360, clock signals arriving at sink points, associated with interfaces between the logic units, have to be aligned (synchronized). That is, the time delays associated with inter-chip interface 360 also have to be controlled, as further described in reference to FIG. 4.”)
(Kashem, p. 4, [0026] “FIG. 5 is a block diagram of an example system 500 for clock delay compensation, based on which one or more features of the disclosure can be implemented. The system 500 demonstrates clock delay compensation with respect to two paths through which a clock signal, generated by the clock generator 530 (e.g., 410), is distributed in two neighboring chiplets, chiplet A 540 and chiplet B 550. As illustrated, associated with chiplet A 540 are a clock receiver 541 and a programable delay unit 542 (parts of chiplet A’s clock unit 480), and a clock distribution path 544 that ends at a sink point 545. Likewise, associated with chiplet B 550 are a clock receiver 551 and a programable delay unit 552 (parts of chiplet B’s clock unit 480), and a clock distribution path 554 that ends at a sink point 555.”)
and a second chiplet comprising a second C2C interface module,
(Kashem, p. 4, [0026] “… Initially, chiplet A is configured to receive 541 the clock signal, and, then, to delay 542 the clock signal by an initial delay offset (e.g., equal zero). Likewise, chiplet B is configured to receive 551 the clock signal, and, then, to delay 552 the clock signal by an initial delay offset (e.g., equal zero). As discussed, due to manufacturing variations in circuitry and wires through which the clock signal propagates, a clock signal that originates in the clock generator 530 splits into clock signals that arrive at the sink points 545, 555 of chiplet A and of chiplet B at different times. “)
(Kashem, p. 1, [0001] “The propagation of data across cascading logic units is typically controlled by clock signals. When interfacing logic units are integrated into two chips, data have to be exchanged over wires across the chips. Due to physical limitations in the density of connecting wires (e.g., 100 wires per millimeter), a physical layer interface is used to drive the data between the logic units.”)
wherein the first transceiver is configured to generate a clock,
(Kashem, p. 2, [0018] “To carry out pipelined processing, as described above, each logic unit should be informed when it can begin launching its operation, that is, when input data are ready in its input register for the logic circuitry to operate on. To that end, a clock signal, generated by a clock generator 230, can be distributed to the registers 205.1-3, 215.1-3.”)
and wherein the clock is transmitted from the first C2C interface module to the second C2C interface module, via a clock transmission wire,
(Kashem, p. 4, [0026] “… Initially, chiplet A is configured to receive 541 the clock signal, and, then, to delay 542 the clock signal by an initial delay offset (e.g., equal zero). Likewise, chiplet B is configured to receive 551 the clock signal, and, then, to delay 552 the clock signal by an initial delay offset (e.g., equal zero). As discussed, due to manufacturing variations in circuitry and wires through which the clock signal propagates, a clock signal that originates in the clock generator 530 splits into clock signals that arrive at the sink points 545, 555 of chiplet A and of chiplet B at different times. “)
for data transfer between the first chiplet and the second chiplet.
(Kashem, p. 3, [0020] “FIG. 3 is a diagram of an example clock distribution tree across a chip 300, based on which one or more features of the disclosure can be implemented. FIG. 3 shows a chip (e.g., of 20 square millimeter 305), including logic units 340 that interface through their registers (e.g., the logic units 220.1-3, illustrated in FIG. 2). The chip also includes a clock distribution tree 320, that is fed at its root with a clock signal, generated by a clock generator 310.”)
(Kashem, p. 4, [0026] “… Initially, chiplet A is configured to receive 541 the clock signal, and, then, to delay 542 the clock signal by an initial delay offset (e.g., equal zero). Likewise, chiplet B is configured to receive 551 the clock signal, and, then, to delay 552 the clock signal by an initial delay offset (e.g., equal zero). As discussed, due to manufacturing variations in circuitry and wires through which the clock signal propagates, a clock signal that originates in the clock generator 530 splits into clock signals that arrive at the sink points 545, 555 of chiplet A and of chiplet B at different times. “)
Regarding claim 2
Kashem teaches all features of claim 1 as disclosed above and further discloses
The system of claim 1, wherein: the second chiplet further comprises programmable logic circuitry,
(Kashem, p. 3, [0025] “… If phase measurements, received from any of the phase detectors associated with a pair of chiplets, is above a tolerance value (a maximum clock skew), the microcontroller 420 can instruct the clock unit 480 of the chiplet with the faster clock signal (out of the pair) to adjust its programmable delay so that the skew is decreased.”)
(Kashem, p. 2, [0017] “… An input (or launching) register 205.1 can hold the input data to be operated on by the first logic unit’s circuitry 210.1, the result of which is stored in an output (or capturing) register 215.1. The captured data may be transferred from that output register 215.1 to an input register 205.2 of the second logic unit 220.2 in the pipeline. Upon completion of its computations, the second logic unit’s circuitry 210.2 outputs the resulting data into its output register 215.2, to be transferred to the input register 205.3 of the third logic unit 220.3. Likewise, upon completion of its computations, the third logic unit’s circuitry 210.3 outputs the resulting data into its output register 215.3, to be transferred down the pipeline to the input register of a subsequent logic unit.”)
and the clock is used by a transceiver protocol implemented in the programmable logic circuitry
(Kashem, p. 2, [0018] To carry out pipelined processing, as described above, each logic unit should be informed when it can begin launching its operation, that is, when input data are ready in its input register for the logic circuitry to operate on. To that end, a clock signal, generated by a clock generator 230, can be distributed to the registers 205.1-3, 215.1-3. To secure proper operation of the cascading logic units, the distributed clock signal, as measured at the clock inputs of the circuitry that require it (referred to herein as sink points), have to be aligned, as illustrated by clock signals 240.1 and 240.2. For example, logic unit 220.1 can be configured to start its operation based on data stored in input register 205.1 at the rise of the clock pulse 242 measured at sink point 230.1 and to store the resulting data in its output register 215.1. Then, the data stored in output register 215.1 can be released (transferred) into input register 205.2 of logic unit 220.2 at the rise of the clock pulse 244 measured at sink point 230.2. As long as the arrival times of the clock signal to sink point 230.1 and to sink point 230.2 are sufficiently the same, the logic 210.1, once it receives the input data, will be able to complete its computation and store the resulting data in its output register 215.1 prior to the rise of the clock pulse 244 at sink point 230.2 (a pulse rise 244 that triggers a transfer of data between output register 215.1 and input register 205.2).”)
(Kashem, p. 3, [0022] “… and logic circuitry (e.g., the logic units 220.1-3, 340 discussed in reference to FIGS. 2-3) are integrated into the other chiplets 430.2-430.16. … Each clock unit 480 further distribute the received (and potentially delayed) clock signal through its chiplet’s clock distribution tree 440 that propagates the clock signal to various sink points - e.g., points of interface 460, 470 between logic units.”)
for the data transfer between the first chiplet and the second chiplet.
(Kashem, p. 2, [0017] “… An input (or launching) register 205.1 can hold the input data to be operated on by the first logic unit’s circuitry 210.1, the result of which is stored in an output (or capturing) register 215.1. The captured data may be transferred from that output register 215.1 to an input register 205.2 of the second logic unit 220.2 in the pipeline. Upon completion of its computations, the second logic unit’s circuitry 210.2 outputs the resulting data into its output register 215.2, to be transferred to the input register 205.3 of the third logic unit 220.3. Likewise, upon completion of its computations, the third logic unit’s circuitry 210.3 outputs the resulting data into its output register 215.3, to be transferred down the pipeline to the input register of a subsequent logic unit.”)
(Kashem, p. 2, [0018] To carry out pipelined processing, as described above, each logic unit should be informed when it can begin launching its operation, that is, when input data are ready in its input register for the logic circuitry to operate on. To that end, a clock signal, generated by a clock generator 230, can be distributed to the registers 205.1-3, 215.1-3. To secure proper operation of the cascading logic units, the distributed clock signal, as measured at the clock inputs of the circuitry that require it (referred to herein as sink points), have to be aligned, as illustrated by clock signals 240.1 and 240.2. For example, logic unit 220.1 can be configured to start its operation based on data stored in input register 205.1 at the rise of the clock pulse 242 measured at sink point 230.1 and to store the resulting data in its output register 215.1. Then, the data stored in output register 215.1 can be released (transferred) into input register 205.2 of logic unit 220.2 at the rise of the clock pulse 244 measured at sink point 230.2. As long as the arrival times of the clock signal to sink point 230.1 and to sink point 230.2 are sufficiently the same, the logic 210.1, once it receives the input data, will be able to complete its computation and store the resulting data in its output register 215.1 prior to the rise of the clock pulse 244 at sink point 230.2 (a pulse rise 244 that triggers a transfer of data between output register 215.1 and input register 205.2).”)
Regarding claim 3
Kashem teaches all features of claim 1 as disclosed above and further discloses
The system of claim 1, wherein: the clock is a transmit (TX) clock generated by the first transceiver when the first transceiver is in a TX mode
(Kashem, p. 3, [0022] “FIG. 4 is a diagram of an example multi-chiplet system 400, based on which one or more features of the disclosure can be implemented. The system 400 include multiple chiplets 430.1-16 packaged in a four by four array. A clock generator 410 and a micro-controller 420 are integrated into the first chiplet 430.1, and logic circuitry (e.g., the logic units 220.1-3, 340 discussed in reference to FIGS. 2-3) are integrated into the other chiplets 430.2-430.16. The clock signal from the clock generator 410 is distributed to clock units 480, positioned at the center of each chiplet, via wires that may be integrated into a carrier that holds the chiplets (e.g., a packaging such as an interposer, a layer of silicon, or an organic substrate).”)
and the TX clock is transmitted back from the second C2C interface module of the second chiplet to the first C2C interface module of the first chiplet through another clock transmission wire.
(Kashem, p. 3, [0022] “… The clock signal from the clock generator 410 is distributed to clock units 480, positioned at the center of each chiplet, via wires that may be integrated into a carrier that holds the chiplets (e.g., a packaging such as an interposer, a layer of silicon, or an organic substrate). A clock unit includes a clock receiver that receives the clock signal and a delay unit that can introduce a programable delay offset to the received clock signal (as further described in reference to FIG. 5). Each clock unit 480 further distribute the received (and potentially delayed) clock signal through its chiplet’s clock distribution tree 440 that propagates the clock signal to various sink points - e.g., points of interface 460, 470 between logic units.”)
Regarding claim 8
Kashem teaches all features of claim 1 as disclosed above and further discloses
The system of claim 1, wherein: the first chiplet further comprises a second transceiver and alignment circuitry
(Kashem, p. 3, [0023] “… Since, the output of the one logic unit is the input of the other logic unit, the latter should be signaled when the former concluded its operation. To that end, as explained above, the clock signals, as measured at the logic units’ respective sink points 460, 470, should be aligned (synchronized). Such alignment can be done based on the phase between these clock signals that, as disclosed herein, can be measured by a pair of phase detectors 450.1.”)
(Kashem, p. 2, [0018] “To carry out pipelined processing, as described above, each logic unit should be informed when it can begin launching its operation, that is, when input data are ready in its input register for the logic circuitry to operate on. To that end, a clock signal, generated by a clock generator 230, can be distributed to the registers 205.1-3, 215.1-3. To secure proper operation of the cascading logic units, the distributed clock signal, as measured at the clock inputs of the circuitry that require it (referred to herein as sink points), have to be aligned, as illustrated by clock signals 240.1 and 240.2.”)
and the alignment circuitry is configured to align data from the first transceiver and the second transceiver
(Kashem, p. 2, [0018] “To carry out pipelined processing, as described above, each logic unit should be informed when it can begin launching its operation, that is, when input data are ready in its input register for the logic circuitry to operate on. To that end, a clock signal, generated by a clock generator 230, can be distributed to the registers 205.1-3, 215.1-3. To secure proper operation of the cascading logic units, the distributed clock signal, as measured at the clock inputs of the circuitry that require it (referred to herein as sink points), have to be aligned, as illustrated by clock signals 240.1 and 240.2. For example, logic unit 220.1 can be configured to start its operation based on data stored in input register 205.1 at the rise of the clock pulse 242 measured at sink point 230.1 and to store the resulting data in its output register 215.1. Then, the data stored in output register 215.1 can be released (transferred) into input register 205.2 of logic unit 220.2 at the rise of the clock pulse 244 measured at sink point 230.2. As long as the arrival times of the clock signal to sink point 230.1 and to sink point 230.2 are sufficiently the same, the logic 210.1, once it receives the input data, will be able to complete its computation and store the resulting data in its output register 215.1 prior to the rise of the clock pulse 244 at sink point 230.2 (a pulse rise 244 that triggers a transfer of data between output register 215.1 and input register 205.2). Therefore, when clock signals (measured at sink points) are synchronized, the processed data will properly propagate through the pipeline if each logic unit will complete its operation within a computation time 246 that is within the clock cycle. In another example, where two logic units, e.g., 220.2 and 220.3, are integrated into different chips, the transfer of data from output register 215.2 to input register 205.3 can be triggered by a rise of a clock pulse at sink point 230.3 and a rise of a clock pulse at sink point 230.4, respectively. In such a case too, the clock signals, measured at sink points 230.3 and 230.4, should be synchronized to allow the processed data to properly propagate across the chips.”)
before transmitting the data to the first C2C interface module.
(Kashem, p. 2, [0018] “To carry out pipelined processing, as described above, each logic unit should be informed when it can begin launching its operation, that is, when input data are ready in its input register for the logic circuitry to operate on. To that end, a clock signal, generated by a clock generator 230, can be distributed to the registers 205.1-3, 215.1-3. To secure proper operation of the cascading logic units, the distributed clock signal, as measured at the clock inputs of the circuitry that require it (referred to herein as sink points), have to be aligned, as illustrated by clock signals 240.1 and 240.2. For example, logic unit 220.1 can be configured to start its operation based on data stored in input register 205.1 at the rise of the clock pulse 242 measured at sink point 230.1 and to store the resulting data in its output register 215.1. Then, the data stored in output register 215.1 can be released (transferred) into input register 205.2 of logic unit 220.2 at the rise of the clock pulse 244 measured at sink point 230.2. As long as the arrival times of the clock signal to sink point 230.1 and to sink point 230.2 are sufficiently the same, the logic 210.1, once it receives the input data, will be able to complete its computation and store the resulting data in its output register 215.1 prior to the rise of the clock pulse 244 at sink point 230.2 (a pulse rise 244 that triggers a transfer of data between output register 215.1 and input register 205.2). Therefore, when clock signals (measured at sink points) are synchronized, the processed data will properly propagate through the pipeline if each logic unit will complete its operation within a computation time 246 that is within the clock cycle. In another example, where two logic units, e.g., 220.2 and 220.3, are integrated into different chips, the transfer of data from output register 215.2 to input register 205.3 can be triggered by a rise of a clock pulse at sink point 230.3 and a rise of a clock pulse at sink point 230.4, respectively. In such a case too, the clock signals, measured at sink points 230.3 and 230.4, should be synchronized to allow the processed data to properly propagate across the chips.”)
(Kashem, p. 3, [0023] “… Since, the output of the one logic unit is the input of the other logic unit, the latter should be signaled when the former concluded its operation. To that end, as explained above, the clock signals, as measured at the logic units’ respective sink points 460, 470, should be aligned (synchronized). Such alignment can be done based on the phase between these clock signals that, as disclosed herein, can be measured by a pair of phase detectors 450.1.”)
Regarding claim 9
Kashem teaches all features of claim 1 as disclosed above and further discloses
The system of claim 1, wherein: the first chiplet further comprises a second transceiver
(Kashem, p. 3, [0022] “FIG. 4 is a diagram of an example multi-chiplet system 400, based on which one or more features of the disclosure can be implemented. The system 400 include multiple chiplets 430.1-16 packaged in a four by four array. A clock generator 410 and a micro-controller 420 are integrated into the first chiplet 430.1, and logic circuitry (e.g., the logic units 220.1-3, 340 discussed in reference to FIGS. 2-3) are integrated into the other chiplets 430.2-430.16. The clock signal from the clock generator 410 is distributed to clock units 480, positioned at the center of each chiplet, via wires that may be integrated into a carrier that holds the chiplets (e.g., a packaging such as an interposer, a layer of silicon, or an organic substrate).”)
the second chiplet further comprises programmable logic circuitry and alignment circuitry
(Kashem, p. 1, [0005] “FIG. 2 is a diagram of an example clock distribution to logic units, based on which one or more features of the disclosure can be implemented;”)
(Kashem, p. 2, [0018] “To carry out pipelined processing, as described above, each logic unit should be informed when it can begin launching its operation, that is, when input data are ready in its input register for the logic circuitry to operate on. To that end, a clock signal, generated by a clock generator 230, can be distributed to the registers 205.1-3, 215.1-3. To secure proper operation of the cascading logic units, the distributed clock signal, as measured at the clock inputs of the circuitry that require it (referred to herein as sink points), have to be aligned, as illustrated by clock signals 240.1 and 240.2.”)
and the alignment circuitry is configured to align data from the first and second transceivers before transmitting the data to the programmable logic circuitry.
(Kashem, p. 2, [0018] “… For example, logic unit 220.1 can be configured to start its operation based on data stored in input register 205.1 at the rise of the clock pulse 242 measured at sink point 230.1 and to store the resulting data in its output register 215.1. Then, the data stored in output register 215.1 can be released (transferred) into input register 205.2 of logic unit 220.2 at the rise of the clock pulse 244 measured at sink point 230.2. As long as the arrival times of the clock signal to sink point 230.1 and to sink point 230.2 are sufficiently the same, the logic 210.1, once it receives the input data, will be able to complete its computation and store the resulting data in its output register 215.1 prior to the rise of the clock pulse 244 at sink point 230.2 (a pulse rise 244 that triggers a transfer of data between output register 215.1 and input register 205.2).”)
Regarding claim 10
Kashem discloses
A method performed by a system comprising a first chiplet and a second chiplet, the method comprising
(Kashem, p. 1, [0010] “Systems and methods are provided for clock delay compensation in a multi-chip system.”)
generating a clock by a first transceiver on the first chiplet
(Kashem, p. 3, [0020] “FIG. 3 is a diagram of an example clock distribution tree across a chip 300, based on which one or more features of the disclosure can be implemented. FIG. 3 shows a chip (e.g., of 20 square millimeter 305), including logic units 340 that interface through their registers (e.g., the logic units 220.1-3, illustrated in FIG. 2). The chip also includes a clock distribution tree 320, that is fed at its root with a clock signal, generated by a clock generator 310.”)
transmitting the clock from a first chiplet-to-chiplet (C2C) interface module on the first chiplet to a second C2C interface module on the second chiplet
(Kashem, p. 3, [0022] “FIG. 4 is a diagram of an example multi-chiplet system 400, based on which one or more features of the disclosure can be implemented. The system 400 include multiple chiplets 430.1-16 packaged in a four by four array. A clock generator 410 and a micro-controller 420 are integrated into the first chiplet 430.1, and logic circuitry (e.g., the logic units 220.1-3, 340 discussed in reference to FIGS. 2-3) are integrated into the other chiplets 430.2-430.16. The clock signal from the clock generator 410 is distributed to clock units 480, positioned at the center of each chiplet, via wires that may be integrated into a carrier that holds the chiplets (e.g., a packaging such as an interposer, a layer of silicon, or an organic substrate).”)
and using the clock by the second chiplet for data transfer between the first chiplet and the second chiplet.
(Kashem, p. 2, [0018] “To carry out pipelined processing, as described above, each logic unit should be informed when it can begin launching its operation, that is, when input data are ready in its input register for the logic circuitry to operate on. To that end, a clock signal, generated by a clock generator 230, can be distributed to the registers 205.1-3, 215.1-3. To secure proper operation of the cascading logic units, the distributed clock signal, as measured at the clock inputs of the circuitry that require it (referred to herein as sink points), have to be aligned, as illustrated by clock signals 240.1 and 240.2.”)
Regarding claim 11
Kashem teaches all features of claim 10 as disclosed above and further discloses
The method of claim 10, further comprising:
transmitting the clock back from the second C2C interface module of the second chiplet to the first C2C interface module of the first chiplet,
(Kashem, p. 2, [0017] “… The captured data may be transferred from that output register 215.1 to an input register 205.2 of the second logic unit 220.2 in the pipeline.”)
(Kashem, p. 3, [0022] “… The clock signal from the clock generator 410 is distributed to clock units 480, positioned at the center of each chiplet, via wires that may be integrated into a carrier that holds the chiplets (e.g., a packaging such as an interposer, a layer of silicon, or an organic substrate). A clock unit includes a clock receiver that receives the clock signal and a delay unit that can introduce a programable delay offset to the received clock signal (as further described in reference to FIG. 5). Each clock unit 480 further distribute the received (and potentially delayed) clock signal through its chiplet’s clock distribution tree 440 that propagates the clock signal to various sink points - e.g., points of interface 460, 470 between logic units.”)
when the first transceiver is in a transmit (TX) mode and wherein the clock is a TX clock generated by the first transceiver when the first transceiver is in the TX mode.
(Kashem, p. 2, [0018] “To carry out pipelined processing, as described above, each logic unit should be informed when it can begin launching its operation, that is, when input data are ready in its input register for the logic circuitry to operate on. To that end, a clock signal, generated by a clock generator 230, can be distributed to the registers 205.1-3, 215.1-3. To secure proper operation of the cascading logic units, the distributed clock signal, as measured at the clock inputs of the circuitry that require it (referred to herein as sink points), have to be aligned, as illustrated by clock signals 240.1 and 240.2.”)
Regarding claim 16
Kashem teaches all features of claim 10 as disclosed above and further discloses
The method of claim 10, further comprising:
aligning data from the first transceiver and a second transceiver of the first chiplet before transmitting the data to the first C2C interface module.
(Kashem, p. 2, [0018] To carry out pipelined processing, as described above, each logic unit should be informed when it can begin launching its operation, that is, when input data are ready in its input register for the logic circuitry to operate on. To that end, a clock signal, generated by a clock generator 230, can be distributed to the registers 205.1-3, 215.1-3. To secure proper operation of the cascading logic units, the distributed clock signal, as measured at the clock inputs of the circuitry that require it (referred to herein as sink points), have to be aligned, as illustrated by clock signals 240.1 and 240.2. For example, logic unit 220.1 can be configured to start its operation based on data stored in input register 205.1 at the rise of the clock pulse 242 measured at sink point 230.1 and to store the resulting data in its output register 215.1. Then, the data stored in output register 215.1 can be released (transferred) into input register 205.2 of logic unit 220.2 at the rise of the clock pulse 244 measured at sink point 230.2. As long as the arrival times of the clock signal to sink point 230.1 and to sink point 230.2 are sufficiently the same, the logic 210.1, once it receives the input data, will be able to complete its computation and store the resulting data in its output register 215.1 prior to the rise of the clock pulse 244 at sink point 230.2 (a pulse rise 244 that triggers a transfer of data between output register 215.1 and input register 205.2).”)
Regarding claim 17
Kashem teaches all features of claim 10 as disclosed above and further discloses
The method of claim 10, further comprising:
aligning data from the first transceiver and a second transceiver of the first chiplet before transmitting the data to programmable logic circuitry on the second chiplet.
(Kashem, p. 1, [0010] “Systems and methods are provided for clock delay compensation in a multi-chip system. Clock signals, propagating through clock distribution trees of the system’s chiplets, are used to control synchronized operation of cascading logic units.”)
(Kashem, p. 2, [0017] “FIG. 2 is a diagram of an example clock distribution to logic units 200, based on which one or more features of the disclosure can be implemented. Current integrated circuit technologies enable the integration of cascading logic units, so that each logic unit performs computational operations on data provided to it from a previous logic unit, and then feeding the next logic unit with its processed data. For example, three logic units 220.1-3 can be designed to implement pipelined computations, as illustrated in FIG. 2. An input (or launching) register 205.1 can hold the input data to be operated on by the first logic unit’s circuitry 210.1, the result of which is stored in an output (or capturing) register 215.1. The captured data may be transferred from that output register 215.1 to an input register 205.2 of the second logic unit 220.2 in the pipeline. Upon completion of its computations, the second logic unit’s circuitry 210.2 outputs the resulting data into its output register 215.2, to be transferred to the input register 205.3 of the third logic unit 220.3. Likewise, upon completion of its computations, the third logic unit’s circuitry 210.3 outputs the resulting data into its output register 215.3, to be transferred down the pipeline to the input register of a subsequent logic unit.”)
Regarding claim 18
Kashem discloses
A chiplet, comprising:
a transceiver; and a chiplet-to-chiplet (C2C) interface module, wherein the transceiver is configured to transmit a transceiver-generated clock to another chiplet through the C2C interface module for data transfer.
(Kashem, p. 3, [0021] “… Furthermore, when a logic unit interfaces with another logic unit that is integrated into another chip 360, clock signals arriving at sink points, associated with interfaces between the logic units, have to be aligned (synchronized). That is, the time delays associated with inter-chip interface 360 also have to be controlled, as further described in reference to FIG. 4.”)
(Kashem, p. 4, [0026] “FIG. 5 is a block diagram of an example system 500 for clock delay compensation, based on which one or more features of the disclosure can be implemented. The system 500 demonstrates clock delay compensation with respect to two paths through which a clock signal, generated by the clock generator 530 (e.g., 410), is distributed in two neighboring chiplets, chiplet A 540 and chiplet B 550. As illustrated, associated with chiplet A 540 are a clock receiver 541 and a programable delay unit 542 (parts of chiplet A’s clock unit 480), and a clock distribution path 544 that ends at a sink point 545. Likewise, associated with chiplet B 550 are a clock receiver 551 and a programable delay unit 552 (parts of chiplet B’s clock unit 480), and a clock distribution path 554 that ends at a sink point 555.”)
Regarding claim 20
Kashem teaches all features of claim 18 as disclosed above and further discloses
The chiplet of claim 18, further comprising:
another transceiver and alignment circuitry,
(Kashem, p. 2, [0018] To carry out pipelined processing, as described above, each logic unit should be informed when it can begin launching its operation, that is, when input data are ready in its input register for the logic circuitry to operate on. To that end, a clock signal, generated by a clock generator 230, can be distributed to the registers 205.1-3, 215.1-3. To secure proper operation of the cascading logic units, the distributed clock signal, as measured at the clock inputs of the circuitry that require it (referred to herein as sink points), have to be aligned, as illustrated by clock signals 240.1 and 240.2. For example, logic unit 220.1 can be configured to start its operation based on data stored in input register 205.1 at the rise of the clock pulse 242 measured at sink point 230.1 and to store the resulting data in its output register 215.1. Then, the data stored in output register 215.1 can be released (transferred) into input register 205.2 of logic unit 220.2 at the rise of the clock pulse 244 measured at sink point 230.2. As long as the arrival times of the clock signal to sink point 230.1 and to sink point 230.2 are sufficiently the same, the logic 210.1, once it receives the input data, will be able to complete its computation and store the resulting data in its output register 215.1 prior to the rise of the clock pulse 244 at sink point 230.2 (a pulse rise 244 that triggers a transfer of data between output register 215.1 and input register 205.2).”)
wherein the alignment circuitry is configured to align data from the transceiver and the another transceiver before transmitting the data to the C2C interface module.
(Kashem, p. 2, [0018] To carry out pipelined processing, as described above, each logic unit should be informed when it can begin launching its operation, that is, when input data are ready in its input register for the logic circuitry to operate on. To that end, a clock signal, generated by a clock generator 230, can be distributed to the registers 205.1-3, 215.1-3. To secure proper operation of the cascading logic units, the distributed clock signal, as measured at the clock inputs of the circuitry that require it (referred to herein as sink points), have to be aligned, as illustrated by clock signals 240.1 and 240.2. For example, logic unit 220.1 can be configured to start its operation based on data stored in input register 205.1 at the rise of the clock pulse 242 measured at sink point 230.1 and to store the resulting data in its output register 215.1. Then, the data stored in output register 215.1 can be released (transferred) into input register 205.2 of logic unit 220.2 at the rise of the clock pulse 244 measured at sink point 230.2. As long as the arrival times of the clock signal to sink point 230.1 and to sink point 230.2 are sufficiently the same, the logic 210.1, once it receives the input data, will be able to complete its computation and store the resulting data in its output register 215.1 prior to the rise of the clock pulse 244 at sink point 230.2 (a pulse rise 244 that triggers a transfer of data between output register 215.1 and input register 205.2).”)
(Kashem, p. 2, [0018] “… For example, logic unit 220.1 can be configured to start its operation based on data stored in input register 205.1 at the rise of the clock pulse 242 measured at sink point 230.1 and to store the resulting data in its output register 215.1. Then, the data stored in output register 215.1 can be released (transferred) into input register 205.2 of logic unit 220.2 at the rise of the clock pulse 244 measured at sink point 230.2. As long as the arrival times of the clock signal to sink point 230.1 and to sink point 230.2 are sufficiently the same, the logic 210.1, once it receives the input data, will be able to complete its computation and store the resulting data in its output register 215.1 prior to the rise of the clock pulse 244 at sink point 230.2 (a pulse rise 244 that triggers a transfer of data between output register 215.1 and input register 205.2).”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7, 12-15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Krishnan SRINIVASAN et. al. (US 20230141709 A1) as applied to claims 1, 10, 11, and 18 above, and further in view of Swadesh Choudhary et. al. (US 20220342841 A1), hereinafter Choudhary.
Regarding claim 4
Kashem teaches all features of claim 1 as disclosed above.
Kashem does not explicitly teach
The system of claim 1, wherein the second chiplet further comprises programmable logic circuitry configured to transmit data in a datapath to a physical (PHY) layer of the second C2C interface module,
the datapath bypassing a C2C protocol layer and at least a portion of a die-to-die (D2D) adapter layer of the second C2C interface module.
However, SRINIVASAN discloses
The system of claim 1, wherein the second chiplet further comprises programmable logic circuitry configured to transmit data in a datapath to a physical (PHY) layer of the second C2C interface module, the datapath bypassing a C2C protocol layer
(SRINIVASAN. p. 4, [0039] “Within different interface options, various operation modes may be supported by the C2C interfaces (and thus, the anchor or chiplet). For example, the C2C interface may comprise a physical (PHY) layer (Low-level/analog+digital), a link (LINK) layer (Digital, Single DW Functions), and a protocol (PROTOCOL) layer (Digital, Multi-DW). Each layer may have particular specifications and/or functions. This delineation allows the C2C interface to implement different modes of operation that are most suitable to a specific layer, providing additional flexibility when implemented with the aspects described herein.”)
(SRINIVASAN. p. 5, [0044] “… Each of the anchor 305 and the chiplet 310 may have its own C2C interface that comprises a plurality of words, each configurable to be receiving or transmitting, and programmable registers used to configure the plurality of words.”)
(SRINIVASAN. p. 5, [0047] “In the architecture 300a, when the chiplet 310a is provided with the orientation as shown, the anchor 305a can be programmed, via the programming interface and using the programmable registers of the C2C interface, to appropriately route data to and from the chiplet 310a with the depicted orientation. The chiplet 310a has an orientation of a first (top) row including G and H, a second row including F and E, a third row including D and C. and a fourth (bottom) row including A and B. To accommodate such an orientation, the programming interface programs the registers of the C2C interface such that a first (top) row of registers are receive registers, a second row of registers are transmit registers, a third row of registers are receive registers, and a fourth row of registers are transmit registers. Thus, the anchor 305a can receive data from and provide data to the chiplet 310a.”)
(SRINIVASAN. p. 3, [0029] “FIG. 2 depicts a block diagram of a hierarchy 200 of data flow options supported by a C2C interface, employed in a multi-chip IC, such as the multi-chip IC 100 of FIG. 1, according to an example embodiment. Thus, the hierarchy 200 identifies interface options available between an anchor IC and corresponding chiplet ICs of the multi-chip IC. Broadly, three categories of C2C interface options are supported—streaming (node 210), an Advanced eXtensible Interface (AXI-MM) (node 220), and Pass-through (node 230). Within each category, multiple sub-categories of options are supported. For example, the streaming protocol enables selection of an Advanced eXtensible Interface streaming (AXI-S) based streaming protocol (node 211a), a Credited eXtensible Stream (CXS) streaming protocol (node 211b), or just use a collection of wires (COW) streaming protocol (node 211c) without attaching any protocol semantics to the wires. Within each protocol, the user may choose different aggregation options, such as, aggregate multiple incoming flows into one outgoing flow, or vice versa.”)
(SRINIVASAN. p. 3, [0030] “In some embodiments, the C2C interface can be configured into an AXI-MM based interface (node 220) or a pass-through interface (node 230) that does not perform any protocol specific operation, or the AXI-MM based interface can be configured for a NoC packet protocol (NPP) (node 221). The C2C interface may have many flows and be configured into a combination of one or more options described in FIG. 2.”)
Kashem and SRINIVASAN do not teach
the datapath bypassing a C2C protocol layer and at least a portion of a die-to-die (D2D) adapter layer of the second C2C interface module.
However Choudhary discloses
the datapath bypassing a C2C protocol layer and at least a portion of a die-to-die (D2D) adapter layer of the second C2C interface module.
(Choudhary, p. 11, [0089] “… In some examples, data transmitted from a UCIe retimer to a UCIe die may not be flow controlled at the D2D adapter level. The UCIe retimer, instead, may have its independent flow-control with the other UCIe retimer if needed, among other example implementations.”)
(Choudhary, p. 25, [0132] “… It is permitted for NOP flits to bypass the Retry buffer, as long as the D2D adapter guarantees that it is not sending consecutive flits for any of the Protocol Layers. On the receiving side, the D2D adapter is not to forward these NOP flits to the Protocol Layer. The receiving Protocol Layer is capable of sinking at the same rate, in that it can receive consecutive chunks of the same flit at the maximum link speed but does not receive consecutive Flits.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Kashem, SRINIVASAN and of Choudhary to yield predictable result of highly minimized latency by choosing the appropriate data path and improve the performance of multi-chiplet system.
Regarding claim 5
Kashem, SRINIVASAN, and Choudhary teach all features of claim 4 as disclosed above.
Kashem does not teach
The system of claim 4, wherein a PHY layer of the first C2C interface module is configured to receive the data in the datapath from the PHY layer of the second C2C interface module, and to transmit the data to the first transceiver, the datapath bypassing a C2C protocol layer and at least a portion of a D2D adapter layer of the first C2C interface module.
However SRINIVASAN discloses
The system of claim 4, wherein a PHY layer of the first C2C interface module is configured to receive the data in the datapath from the PHY layer of the second C2C interface module, and to transmit the data to the first transceiver,
(SRINIVASAN. p. 4, [0039] “Within different interface options, various operation modes may be supported by the C2C interfaces (and thus, the anchor or chiplet). For example, the C2C interface may comprise a physical (PHY) layer (Low-level/analog+digital), a link (LINK) layer (Digital, Single DW Functions), and a protocol (PROTOCOL) layer (Digital, Multi-DW). Each layer may have particular specifications and/or functions. This delineation allows the C2C interface to implement different modes of operation that are most suitable to a specific layer, providing additional flexibility when implemented with the aspects described herein.”)
(SRINIVASAN. p. 6, [0053] “FIG. 4 depicts an example C2C interface architecture 400 that can exist between a chiplet and an anchor, according to an example embodiment. The architecture 400 includes each of the PHY, LINK, and PROTOCOL layers introduced above. As shown, in the PROTOCOL layer, various blocks are present that enable different data flow protocols, as described or introduced above. For example, based on a selected or identified protocol for a particular chiplet, the C2C interface can be employed to route and/or map traffic according to the protocol for the particular chiplet. Thus, dependent upon the protocol selected, different paths may be used to route data through the PROTOCOL layer.”)
Kashem and SRINIVASAN do not explicitly teach
the datapath bypassing a C2C protocol layer and at least a portion of a D2D adapter layer of the first C2C interface module.
However Choudhary discloses
the datapath bypassing a C2C protocol layer and at least a portion of a D2D adapter layer of the first C2C interface module.
(Choudhary, p. 11, [0089] “… In some examples, data transmitted from a UCIe retimer to a UCIe die may not be flow controlled at the D2D adapter level. The UCIe retimer, instead, may have its independent flow-control with the other UCIe retimer if needed, among other example implementations.”)
(Choudhary, p. 25, [0132] “… It is permitted for NOP flits to bypass the Retry buffer, as long as the D2D adapter guarantees that it is not sending consecutive flits for any of the Protocol Layers. On the receiving side, the D2D adapter is not to forward these NOP flits to the Protocol Layer. The receiving Protocol Layer is capable of sinking at the same rate, in that it can receive consecutive chunks of the same flit at the maximum link speed but does not receive consecutive Flits.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Kashem, SRINIVASAN and of Choudhary to yield predictable result of highly minimized latency by choosing the appropriate data path and improve the performance of multi-chiplet system.
Regarding claim 6
Kashem teaches all features of claim 1 as disclosed above and Kashem further discloses
The system of claim 1, wherein
the clock is a receive (RX) clock generated by the first transceiver when the first transceiver is in an RX mode
(Kashem, p. 4, [0026] “… As illustrated, associated with chiplet A 540 are a clock receiver 541 and a programable delay unit 542 (parts of chiplet A’s clock unit 480), and a clock distribution path 544 that ends at a sink point 545. Likewise, associated with chiplet B 550 are a clock receiver 551 and a programable delay unit 552 (parts of chiplet B’s clock unit 480), and a clock distribution path 554 that ends at a sink point 555. These sink points 545, 555 feed the clock signals (distributed via respective distribution path 544, 554) into respective logic units, in chiplet A and in chiplet B, that interface with each other. Accordingly, the clock signals that are measured at these sink points should be aligned. Initially, chiplet A is configured to receive 541 the clock signal, and, then, to delay 542 the clock signal by an initial delay offset (e.g., equal zero). Likewise, chiplet B is configured to receive 551 the clock signal, and, then, to delay 552 the clock signal by an initial delay offset (e.g., equal zero).”)
(Kashem, p. 4, [0030] “… Accordingly, the receivers 541, 551 and the delay units 542, 552 of clock units 480 associated with chiplets are configured to receive the clock signal from the clock generator 410, split the received signal into multiple clock signals, and apply different delay offsets to each clock signal before propagating the differently delayed signals through respective paths of the clock distribution tree of the chiplet.”)
Kashem does not explicitly teach
and a physical (PHY) layer of the first C2C interface module is configured to receive data in a datapath from the first transceiver
However SRINIVASAN discloses
and a physical (PHY) layer of the first C2C interface module is configured to receive data in a datapath from the first transceiver
(SRINIVASAN. p. 4, [0039] “Within different interface options, various operation modes may be supported by the C2C interfaces (and thus, the anchor or chiplet). For example, the C2C interface may comprise a physical (PHY) layer (Low-level/analog+digital), a link (LINK) layer (Digital, Single DW Functions), and a protocol (PROTOCOL) layer (Digital, Multi-DW). Each layer may have particular specifications and/or functions. This delineation allows the C2C interface to implement different modes of operation that are most suitable to a specific layer, providing additional flexibility when implemented with the aspects described herein.”)
(SRINIVASAN. p. 6, [0053] “FIG. 4 depicts an example C2C interface architecture 400 that can exist between a chiplet and an anchor, according to an example embodiment. The architecture 400 includes each of the PHY, LINK, and PROTOCOL layers introduced above. As shown, in the PROTOCOL layer, various blocks are present that enable different data flow protocols, as described or introduced above. For example, based on a selected or identified protocol for a particular chiplet, the C2C interface can be employed to route and/or map traffic according to the protocol for the particular chiplet. Thus, dependent upon the protocol selected, different paths may be used to route data through the PROTOCOL layer.”)
(SRINIVASAN. p. 6, [0054] “The C2C interface architecture 400 may correspond to a protocol handling unit (PHU), which comprises 4 transmit DWs and 4 receive DWs as shown in the PHY layer.”)
Kashem and SRINIVASAN do not teach
the datapath bypassing a C2C protocol layer and at least a portion of a die-to-die (D2D) adapter layer of the first C2C interface module.
However Choudhary discloses
the datapath bypassing a C2C protocol layer and at least a portion of a die-to-die (D2D) adapter layer of the first C2C interface module.
(Choudhary, p. 11, [0089] “… In some examples, data transmitted from a UCIe retimer to a UCIe die may not be flow controlled at the D2D adapter level. The UCIe retimer, instead, may have its independent flow-control with the other UCIe retimer if needed, among other example implementations.”)
(Choudhary, p. 25, [0132] “… It is permitted for NOP flits to bypass the Retry buffer, as long as the D2D adapter guarantees that it is not sending consecutive flits for any of the Protocol Layers. On the receiving side, the D2D adapter is not to forward these NOP flits to the Protocol Layer. The receiving Protocol Layer is capable of sinking at the same rate, in that it can receive consecutive chunks of the same flit at the maximum link speed but does not receive consecutive Flits.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Kashem, SRINIVASAN and of Choudhary to yield predictable result of highly minimized latency by choosing the appropriate data path and improve the performance of multi-chiplet system.
Regarding claim 7
Kashem, SRINIVASAN, and Choudhary teaches all features of claim 6 as disclosed above.
Kashem does not explicitly teach
The system of claim 6, wherein: the second chiplet further comprises programmable logic circuitry
and a PHY layer of the second C2C interface module is configured to receive the data in the datapath from the PHY layer of the first C2C interface module, and to transmit the data to the programmable logic circuitry,
the datapath bypassing a C2C protocol layer and at least a portion of a D2D adapter layer of the second C2C interface module.
However SRINIVASAN discloses
The system of claim 6, wherein: the second chiplet further comprises programmable logic circuitry
(SRINIVASAN, p. 2, [0017] “FIG. 7A is a block diagram depicting a programmable device, according to an example.”)
(SRINIVASAN, p. 2, [0018] “FIG. 7B illustrates a field programmable gate array (FPGA) implementation of the PL, according to an example.”)
(SRINIVASAN, p. 2, [0019] “FIG. 7C is a block diagram depicting a multi-die programmable device, according to an example.”)
and a PHY layer of the second C2C interface module is configured to receive the data in the datapath from the PHY layer of the first C2C interface module, and to transmit the data to the programmable logic circuitry,
(SRINIVASAN. p. 4, [0039] “Within different interface options, various operation modes may be supported by the C2C interfaces (and thus, the anchor or chiplet). For example, the C2C interface may comprise a physical (PHY) layer (Low-level/analog+digital), a link (LINK) layer (Digital, Single DW Functions), and a protocol (PROTOCOL) layer (Digital, Multi-DW). Each layer may have particular specifications and/or functions. This delineation allows the C2C interface to implement different modes of operation that are most suitable to a specific layer, providing additional flexibility when implemented with the aspects described herein.”)
(SRINIVASAN. p. 6, [0053] “FIG. 4 depicts an example C2C interface architecture 400 that can exist between a chiplet and an anchor, according to an example embodiment. The architecture 400 includes each of the PHY, LINK, and PROTOCOL layers introduced above. As shown, in the PROTOCOL layer, various blocks are present that enable different data flow protocols, as described or introduced above. For example, based on a selected or identified protocol for a particular chiplet, the C2C interface can be employed to route and/or map traffic according to the protocol for the particular chiplet. Thus, dependent upon the protocol selected, different paths may be used to route data through the PROTOCOL layer.”)
(SRINIVASAN. p. 3, [0033] “The embodiments described herein allow for different combinations or configurations of chiplets to be connected to an anchor without changing an architecture of the anchor or the chiplets. Instead, the anchor or the chiplet comprises one or more programmable registers as part of the C2C interface used to seamlessly connect the chiplet to the anchor.”)
(SRINIVASAN. p. 3, [0034] “As introduced above, the interface that connects the chiplets to the anchor supports multiple types of data flows. For example, a chiplet may be programmed to operate with a particular data flow, such as an AXI-S (AXI streaming) data flow, a CXS data flow, an NPP data flow, and so forth, as indicated in FIG. 2. The C2C interface, whether at the chiplet or the anchor, thus, may enable the chiplet having the programmed data flow to transmit and receive data with one or more data words of the anchor.”)
(SRINIVASAN. p. 7, [0066] “… The serial transceivers 767 include high-speed transmit/receive circuitries configured to provide an external IO interface for the programmable device 701.”)
Kashem and SRINIVASAN do not teach
the datapath bypassing a C2C protocol layer and at least a portion of a D2D adapter layer of the second C2C interface module.
However Choudhary discloses
the datapath bypassing a C2C protocol layer and at least a portion of a D2D adapter layer of the second C2C interface module.
(Choudhary, p. 11, [0089] “… In some examples, data transmitted from a UCIe retimer to a UCIe die may not be flow controlled at the D2D adapter level. The UCIe retimer, instead, may have its independent flow-control with the other UCIe retimer if needed, among other example implementations.”)
(Choudhary, p. 25, [0132] “… It is permitted for NOP flits to bypass the Retry buffer, as long as the D2D adapter guarantees that it is not sending consecutive flits for any of the Protocol Layers. On the receiving side, the D2D adapter is not to forward these NOP flits to the Protocol Layer. The receiving Protocol Layer is capable of sinking at the same rate, in that it can receive consecutive chunks of the same flit at the maximum link speed but does not receive consecutive Flits.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Kashem, SRINIVASAN and of Choudhary to yield predictable result of highly minimized latency by choosing the appropriate data path and improve the performance of multi-chiplet system.
Regarding claim 12
Kashem teaches all features of claim 11 as disclosed above.
Kashem does not explicitly teach
The method of claim 11, further comprising:
transmitting, by programmable logic circuitry on the second chiplet, data in a datapath to a physical (PHY) layer of the second C2C interface module,
the datapath bypassing a C2C protocol layer and at least a portion of a die-to-die (D2D) adapter layer of the second C2C interface module.
However SRINIVASAN discloses
The method of claim 11, further comprising:
transmitting, by programmable logic circuitry on the second chiplet, data in a datapath to a physical (PHY) layer of the second C2C interface module
(SRINIVASAN, p. 2, [0017] “FIG. 7A is a block diagram depicting a programmable device, according to an example.”)
(SRINIVASAN, p. 2, [0018] “FIG. 7B illustrates a field programmable gate array (FPGA) implementation of the PL, according to an example.”)
(SRINIVASAN, p. 2, [0019] “FIG. 7C is a block diagram depicting a multi-die programmable device, according to an example.”)
(SRINIVASAN, p. 2, [0023] “… The anchor 105 includes circuitry comprising one or more data processing blocks, such as a processing system or subsystem (PS), a memory system (for example, including a memory controller), and the like that the anchor 105 uses to handle data provided by or to one or more of the plurality of chiplet 110.”)
(SRINIVASAN, p. 2, [0024] “Each chiplet 110 includes circuitry that may comprise a dedicated logic device or device type configured to serve a particular purpose or provide particular functionality, such as an data processing engine (DPE) chiplet 110a configured to provide artificial intelligence (AI) or machine learning (ML) functionality.”)
(SRINIVASAN, p. 3, [0034] “… The C2C interface, whether at the chiplet or the anchor, thus, may enable the chiplet having the programmed data flow to transmit and receive data with one or more data words of the anchor.”)
(SRINIVASAN. p. 4, [0039] “Within different interface options, various operation modes may be supported by the C2C interfaces (and thus, the anchor or chiplet). For example, the C2C interface may comprise a physical (PHY) layer (Low-level/analog+digital), a link (LINK) layer (Digital, Single DW Functions), and a protocol (PROTOCOL) layer (Digital, Multi-DW). Each layer may have particular specifications and/or functions. This delineation allows the C2C interface to implement different modes of operation that are most suitable to a specific layer, providing additional flexibility when implemented with the aspects described herein.”)
(SRINIVASAN. p. 6, [0053] “FIG. 4 depicts an example C2C interface architecture 400 that can exist between a chiplet and an anchor, according to an example embodiment. The architecture 400 includes each of the PHY, LINK, and PROTOCOL layers introduced above. As shown, in the PROTOCOL layer, various blocks are present that enable different data flow protocols, as described or introduced above. For example, based on a selected or identified protocol for a particular chiplet, the C2C interface can be employed to route and/or map traffic according to the protocol for the particular chiplet. Thus, dependent upon the protocol selected, different paths may be used to route data through the PROTOCOL layer.”)
(SRINIVASAN. p. 3, [0033] “The embodiments described herein allow for different combinations or configurations of chiplets to be connected to an anchor without changing an architecture of the anchor or the chiplets. Instead, the anchor or the chiplet comprises one or more programmable registers as part of the C2C interface used to seamlessly connect the chiplet to the anchor.”)
(SRINIVASAN. p. 3, [0034] “As introduced above, the interface that connects the chiplets to the anchor supports multiple types of data flows. For example, a chiplet may be programmed to operate with a particular data flow, such as an AXI-S (AXI streaming) data flow, a CXS data flow, an NPP data flow, and so forth, as indicated in FIG. 2. The C2C interface, whether at the chiplet or the anchor, thus, may enable the chiplet having the programmed data flow to transmit and receive data with one or more data words of the anchor.”)
(SRINIVASAN. p. 7, [0066] “… The serial transceivers 767 include high-speed transmit/receive circuitries configured to provide an external IO interface for the programmable device 701.”)
Kashem and SRINIVASAN do not teach
the datapath bypassing a C2C protocol layer and at least a portion of a die-to-die (D2D) adapter layer of the second C2C interface module.
However Choudhary discloses
the datapath bypassing a C2C protocol layer and at least a portion of a die-to-die (D2D) adapter layer of the second C2C interface module.
(Choudhary, p. 11, [0089] “… In some examples, data transmitted from a UCIe retimer to a UCIe die may not be flow controlled at the D2D adapter level. The UCIe retimer, instead, may have its independent flow-control with the other UCIe retimer if needed, among other example implementations.”)
(Choudhary, p. 25, [0132] “… It is permitted for NOP flits to bypass the Retry buffer, as long as the D2D adapter guarantees that it is not sending consecutive flits for any of the Protocol Layers. On the receiving side, the D2D adapter is not to forward these NOP flits to the Protocol Layer. The receiving Protocol Layer is capable of sinking at the same rate, in that it can receive consecutive chunks of the same flit at the maximum link speed but does not receive consecutive Flits.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Kashem, SRINIVASAN and of Choudhary to yield predictable result of highly minimized latency by choosing the appropriate data path and improve the performance of multi-chiplet system.
Regarding claim 13
Kashem, SRINIVASAN, and Choudhary teaches all features of claim 6 as disclosed above.
Kashem does not explicitly teach
The method of claim 12, further comprising:
receiving, by a PHY layer of the first C2C interface module, the data in the datapath from the PHY layer of the second C2C interface module
However SRINIVASAN discloses
receiving, by a PHY layer of the first C2C interface module, the data in the datapath from the PHY layer of the second C2C interface module
(SRINIVASAN. p. 5, [0044] “… Each of the anchor 305 and the chiplet 310 may have its own C2C interface that comprises a plurality of words, each configurable to be receiving or transmitting, and programmable registers used to configure the plurality of words.”)
(SRINIVASAN. p. 4, [0039] “Within different interface options, various operation modes may be supported by the C2C interfaces (and thus, the anchor or chiplet). For example, the C2C interface may comprise a physical (PHY) layer (Low-level/analog+digital), a link (LINK) layer (Digital, Single DW Functions), and a protocol (PROTOCOL) layer (Digital, Multi-DW).”)
(SRINIVASAN. p. 1, [0012] “FIG. 2 depicts a block diagram of a hierarchy of data flow options supported by a chip-to-chip (C2C) interface employed in the multi-chip IC of FIG. 1, according to an example embodiment.”)
and transmitting, by the PHY layer of the first C2C interface module, the data in the datapath to the first transceiver,
(SRINIVASAN. p. 5, [0047] “…To accommodate such an orientation, the programming interface programs the registers of the C2C interface such that a first (top) row of registers are receive registers, a second row of registers are transmit registers, a third row of registers are receive registers, and a fourth row of registers are transmit registers. Thus, the anchor 305a can receive data from and provide data to the chiplet 310a.”)
Kashem and SRINIVASAN do not teach
the datapath bypassing a C2C protocol layer and at least a portion of a D2D adapter layer of the first C2C interface module.
However Choudhary discloses
the datapath bypassing a C2C protocol layer and at least a portion of a D2D adapter layer of the first C2C interface module.
(Choudhary, p. 11, [0089] “… In some examples, data transmitted from a UCIe retimer to a UCIe die may not be flow controlled at the D2D adapter level. The UCIe retimer, instead, may have its independent flow-control with the other UCIe retimer if needed, among other example implementations.”)
(Choudhary, p. 25, [0132] “… It is permitted for NOP flits to bypass the Retry buffer, as long as the D2D adapter guarantees that it is not sending consecutive flits for any of the Protocol Layers. On the receiving side, the D2D adapter is not to forward these NOP flits to the Protocol Layer. The receiving Protocol Layer is capable of sinking at the same rate, in that it can receive consecutive chunks of the same flit at the maximum link speed but does not receive consecutive Flits.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Kashem, SRINIVASAN and of Choudhary to yield predictable result of highly minimized latency by choosing the appropriate data path and improve the performance of multi-chiplet system.
Regarding claim 14
Kashem teaches all features of claim 10 as disclosed above.
Kashem further discloses
The method of claim 10, further comprising: …
wherein the clock is an RX clock generated by the first transceiver when the first transceiver is in the RX mode.
(Kashem. P. 3, [0022] “FIG. 4 is a diagram of an example multi-chiplet system 400, based on which one or more features of the disclosure can be implemented. The system 400 include multiple chiplets 430.1-16 packaged in a four by four array. A clock generator 410 and a micro-controller 420 are integrated into the first chiplet 430.1, and logic circuitry (e.g., the logic units 220.1-3, 340 discussed in reference to FIGS. 2-3) are integrated into the other chiplets 430.2-430.16. The clock signal from the clock generator 410 is distributed to clock units 480, positioned at the center of each chiplet, via wires that may be integrated into a carrier that holds the chiplets (e.g., a packaging such as an interposer, a layer of silicon, or an organic substrate). A clock unit includes a clock receiver that receives the clock signal and a delay unit that can introduce a programable delay offset to the received clock signal (as further described in reference to FIG. 5). Each clock unit 480 further distribute the received (and potentially delayed) clock signal through its chiplet’s clock distribution tree 440 that propagates the clock signal to various sink points - e.g., points of interface 460, 470 between logic units.”)
(Kashem. P. 3, [0023] “… As shown in FIG. 4, pairs of phase detectors 450 are placed at locations of interface between pairs of chiplets. The phase detectors 450 are configured to measure the phase (delay) between two clock signals, as further described in reference to FIG. 5. For example, one logic unit that is integrated into a region within a chiplet 430.2 may be interfacing with another logic unit that is integrated into a neighboring region within another chiplet 430.3. Since, the output of the one logic unit is the input of the other logic unit, the latter should be signaled when the former concluded its operation. To that end, as explained above, the clock signals, as measured at the logic units’ respective sink points 460, 470, should be aligned (synchronized). Such alignment can be done based on the phase between these clock signals that, as disclosed herein, can be measured by a pair of phase detectors 450.1.”)
Kashem does not explicitly teach
The method of claim 10, further comprising:
receiving, by a physical (PHY) layer of the first C2C interface module, data in a datapath from the first transceiver when the first transceiver is in a receive (RX) mode,
the datapath bypassing a C2C protocol layer and at least a portion of a die-to-die (D2D) adapter layer of the first C2C interface module,
However SRINIVASAN discloses
receiving, by a physical (PHY) layer of the first C2C interface module, data in a datapath from the first transceiver when the first transceiver is in a receive (RX) mode
(SRINIVASAN. p. 5, [0044] “… Each of the anchor 305 and the chiplet 310 may have its own C2C interface that comprises a plurality of words, each configurable to be receiving or transmitting, and programmable registers used to configure the plurality of words.”)
(SRINIVASAN. p. 4, [0039] “Within different interface options, various operation modes may be supported by the C2C interfaces (and thus, the anchor or chiplet). For example, the C2C interface may comprise a physical (PHY) layer (Low-level/analog+digital), a link (LINK) layer (Digital, Single DW Functions), and a protocol (PROTOCOL) layer (Digital, Multi-DW). Each layer may have particular specifications and/or functions. This delineation allows the C2C interface to implement different modes of operation that are most suitable to a specific layer, providing additional flexibility when implemented with the aspects described herein.”)
(SRINIVASAN. p. 1, [0012] “FIG. 2 depicts a block diagram of a hierarchy of data flow options supported by a chip-to-chip (C2C) interface employed in the multi-chip IC of FIG. 1, according to an example embodiment.”)
(SRINIVASAN. p. 6, [0059] “… For example, the transmit (TX) block at the top-left of the chiplet in FIG. 5 becomes a receive (RX) block at the top-left of the chiplet in FIG. 6. To handle such configurations, a lane-steering block that steers the DW from the chiplet (or to the chiplet) is provided such that, regardless of the orientation of the chiplet, the anchor sees a consistent connection with respect to the chiplet.”)
Kashem and SRINIVASAN do not explicitly teach
the datapath bypassing a C2C protocol layer and at least a portion of a die-to-die (D2D) adapter layer of the first C2C interface module
However Choudhary discloses
the datapath bypassing a C2C protocol layer and at least a portion of a die-to-die (D2D) adapter layer of the first C2C interface module
(Choudhary, p. 11, [0089] “… In some examples, data transmitted from a UCIe retimer to a UCIe die may not be flow controlled at the D2D adapter level. The UCIe retimer, instead, may have its independent flow-control with the other UCIe retimer if needed, among other example implementations.”)
(Choudhary, p. 25, [0132] “… It is permitted for NOP flits to bypass the Retry buffer, as long as the D2D adapter guarantees that it is not sending consecutive flits for any of the Protocol Layers. On the receiving side, the D2D adapter is not to forward these NOP flits to the Protocol Layer. The receiving Protocol Layer is capable of sinking at the same rate, in that it can receive consecutive chunks of the same flit at the maximum link speed but does not receive consecutive Flits.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Kashem, SRINIVASAN and of Choudhary to yield predictable result of highly minimized latency by choosing the appropriate data path and improve the performance of multi-chiplet system.
Regarding claim 15
Kashem, SRINIVASAN, and Choudhary teach all features of claim 14 as disclosed above.
Kashem does not explicitly teach
The method of claim 14, further comprising:
receiving, by a PHY layer of the second C2C interface module, the data in the datapath from the PHY layer of the first C2C interface module; and transmitting, by the PHY layer of the second C2C interface module, the data in the datapath to programmable logic circuitry on the second chiplet, the datapath bypassing a C2C protocol layer and at least a portion of a D2D adapter layer of the second C2C interface module.
However SRINIVASAN discloses
receiving, by a PHY layer of the second C2C interface module, the data in the datapath from the PHY layer of the first C2C interface module
(SRINIVASAN, p. 3, [0034] “… The C2C interface, whether at the chiplet or the anchor, thus, may enable the chiplet having the programmed data flow to transmit and receive data with one or more data words of the anchor.”)
(SRINIVASAN. p. 4, [0039] “Within different interface options, various operation modes may be supported by the C2C interfaces (and thus, the anchor or chiplet). For example, the C2C interface may comprise a physical (PHY) layer (Low-level/analog+digital), a link (LINK) layer (Digital, Single DW Functions), and a protocol (PROTOCOL) layer (Digital, Multi-DW). Each layer may have particular specifications and/or functions. This delineation allows the C2C interface to implement different modes of operation that are most suitable to a specific layer, providing additional flexibility when implemented with the aspects described herein.”)
and transmitting, by the PHY layer of the second C2C interface module, the data in the datapath to programmable logic circuitry on the second chiplet
(SRINIVASAN, p. 3, [0034] “… The C2C interface, whether at the chiplet or the anchor, thus, may enable the chiplet having the programmed data flow to transmit and receive data with one or more data words of the anchor.”)
(SRINIVASAN. p. 5, [0044] “… Each of the anchor 305 and the chiplet 310 may have its own C2C interface that comprises a plurality of words, each configurable to be receiving or transmitting, and programmable registers used to configure the plurality of words.”)
(SRINIVASAN, p. 2, [0023] “… The anchor 105 includes circuitry comprising one or more data processing blocks, such as a processing system or subsystem (PS), a memory system (for example, including a memory controller), and the like that the anchor 105 uses to handle data provided by or to one or more of the plurality of chiplet 110.”)
Kashem and SRINIVASAN do not explicitly teach
the datapath bypassing a C2C protocol layer and at least a portion of a D2D adapter layer of the second C2C interface module.
However Choudhary discloses
the datapath bypassing a C2C protocol layer and at least a portion of a D2D adapter layer of the second C2C interface module.
(Choudhary, p. 11, [0089] “… In some examples, data transmitted from a UCIe retimer to a UCIe die may not be flow controlled at the D2D adapter level. The UCIe retimer, instead, may have its independent flow-control with the other UCIe retimer if needed, among other example implementations.”)
(Choudhary, p. 25, [0132] “… It is permitted for NOP flits to bypass the Retry buffer, as long as the D2D adapter guarantees that it is not sending consecutive flits for any of the Protocol Layers. On the receiving side, the D2D adapter is not to forward these NOP flits to the Protocol Layer. The receiving Protocol Layer is capable of sinking at the same rate, in that it can receive consecutive chunks of the same flit at the maximum link speed but does not receive consecutive Flits.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Kashem, SRINIVASAN and of Choudhary to yield predictable result of highly minimized latency by choosing the appropriate data path and improve the performance of multi-chiplet system.
Regarding claim 19
Kashem teaches all features of claim 18 as disclosed above.
Kashem does not teach
The chiplet of claim 18, wherein:
the C2C interface module comprises a physical (PHY) layer, a die-to-die (D2D) adapter layer, and a C2C protocol layer; and the transceiver is configured to transmit or receive data in a datapath between the transceiver and the PHY layer of the C2C interface module, the datapath bypassing the C2C protocol layer and at least a portion of the D2D adapter layer.
However SRINIVASAN discloses
the C2C interface module comprises a physical (PHY) layer, a die-to-die (D2D) adapter layer, and a C2C protocol layer; and the transceiver is configured to transmit or receive data in a datapath between the transceiver and the PHY layer of the C2C interface module
(SRINIVASAN. p. 4, [0039] “Within different interface options, various operation modes may be supported by the C2C interfaces (and thus, the anchor or chiplet). For example, the C2C interface may comprise a physical (PHY) layer (Low-level/analog+digital), a link (LINK) layer (Digital, Single DW Functions), and a protocol (PROTOCOL) layer (Digital, Multi-DW). Each layer may have particular specifications and/or functions. This delineation allows the C2C interface to implement different modes of operation that are most suitable to a specific layer, providing additional flexibility when implemented with the aspects described herein.”)
(SRINIVASAN, p. 3, [0034] “… The C2C interface, whether at the chiplet or the anchor, thus, may enable the chiplet having the programmed data flow to transmit and receive data with one or more data words of the anchor.”)
(SRINIVASAN. p. 5, [0044] “… Each of the anchor 305 and the chiplet 310 may have its own C2C interface that comprises a plurality of words, each configurable to be receiving or transmitting, and programmable registers used to configure the plurality of words.”)
(SRINIVASAN. p. 5, [0047] “…To accommodate such an orientation, the programming interface programs the registers of the C2C interface such that a first (top) row of registers are receive registers, a second row of registers are transmit registers, a third row of registers are receive registers, and a fourth row of registers are transmit registers. Thus, the anchor 305a can receive data from and provide data to the chiplet 310a.”)
Kashem and SRINIVASAN do not explicitly teach
the datapath bypassing the C2C protocol layer and at least a portion of the D2D adapter layer.
However Choudhary discloses
the datapath bypassing the C2C protocol layer and at least a portion of the D2D adapter layer.
(Choudhary, p. 11, [0089] “… In some examples, data transmitted from a UCIe retimer to a UCIe die may not be flow controlled at the D2D adapter level. The UCIe retimer, instead, may have its independent flow-control with the other UCIe retimer if needed, among other example implementations.”)
(Choudhary, p. 25, [0132] “… It is permitted for NOP flits to bypass the Retry buffer, as long as the D2D adapter guarantees that it is not sending consecutive flits for any of the Protocol Layers. On the receiving side, the D2D adapter is not to forward these NOP flits to the Protocol Layer. The receiving Protocol Layer is capable of sinking at the same rate, in that it can receive consecutive chunks of the same flit at the maximum link speed but does not receive consecutive Flits.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Kashem, SRINIVASAN and of Choudhary to yield predictable result of highly minimized latency by choosing the appropriate data path and improve the performance of multi-chiplet system.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAYAPPU SOUNDRANAYAGAM whose telephone number is (571)272-0629. The examiner can normally be reached Mon-Fri:8:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/R.S./Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
Prosecution Insights