Prosecution Insights
Last updated: April 18, 2026
Application No. 18/375,343

SEMICONDUCTOR PACKAGE

Non-Final OA §103
Filed
Sep 29, 2023
Examiner
LOPEZ, JORGE ANDRES
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Littelfuse Semiconductor (Wuxi) Co. Ltd.
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
4y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
14 granted / 14 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
4y 4m
Avg Prosecution
28 currently pending
Career history
42
Total Applications
across all art units

Statute-Specific Performance

§103
70.3%
+30.3% vs TC avg
§102
19.8%
-20.2% vs TC avg
§112
9.9%
-30.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 14 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in the COUNTRY OF CHINA on 09/30/2022. Election/Restrictions Applicant's election without traverse of “Group I (Claims 1-19)” in the reply filed on February 02, 2026, is acknowledged. Claims 20-21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-16 and 18-19 are rejected under 35 U.S.C. 103 as being obvious over US 2021/0287969 A1; Sato et al.; 09/2021; (“969”) in view of US 2019/0326204 A1; Miura; 10/2019; (“204”). Regarding Claim 1. 969 teaches in Fig. 1 about an apparatus, comprising: a housing (item 170); a chip assembly pad (item 181) being encapsulated by the housing (item 181 encapsulated by item 170), the chip assembly pad being configured for coupling to a semiconductor chip (item 181 configured to couple to semiconductor chip item 140); one or more leads (items 120 and 130), at least partially encapsulated by the housing (items 120 and 130 are at least partially encapsulated by item 170); a clip (items 150 or 160) including one or more terminals (items 152 or 162) and a chip linker (items 151 or 161), the one or more terminals being configured for coupling to the one or more leads (items 152 or 162 are configured for coupling to items 120 or 130); and 969 does not teach about an apparatus, comprising: a heat dissipation block, wherein the chip linker being coupled between the semiconductor chip and the heat dissipation block, the heat dissipation block being configured for removing heat from the semiconductor chip during operation. 204 teaches in Fig. 7 about an apparatus, comprising: a heat dissipation block (item 31), wherein the chip linker (item 61) being coupled between the semiconductor chip (item 1) and the heat dissipation block (item 61 is coupled between items 1 and 31), the heat dissipation block being configured for removing heat from the semiconductor chip during operation (“semiconductor element 1 generates heat and the heat generated from the semiconductor element 1 is transferred to the first pad part 31”, [0102], Ln. 2-4). Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the invention was made, to consider utilizing the heat dissipation block of 204 to provide heat dissipation away from the semiconductor chip in 969 therefore “heat generated from the semiconductor element 1 is transferred to the first pad part 31” as taught by 204 in [0102], Ln. 3-4. Regarding Claim 2. 969 teaches in Fig. 3 about an apparatus, comprising: a heatsink (item 111) coupled to a first surface of the chip assembly pad (item 111 is coupled to the bottom-surface of item 181), wherein the semiconductor chip is being coupled to a second surface of the chip assembly pad (item 140 is coupled to the top-surface of item 181), the second surface being opposite of the first surface (top and bottom surfaces of item 181 are opposite to each other). Regarding Claim 3. 969 teaches in Fig. 3 about an apparatus, wherein upon coupling of the semiconductor chip to the chip assembly pad, the heatsink does not contact the semiconductor chip (semiconductor chip item 140 does not contact heatsink item 111). Regarding Claim 4. 969 teaches in Fig. 3 about an apparatus, wherein the heatsink does not include a flange being positioned between the heatsink and the chip assembly pad. 969 does not teach about an apparatus, wherein the heatsink includes a flange being positioned between the heatsink and the chip assembly pad. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have added a flange or any other type of edge shape to any side of the chip assembly pad, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04. Regarding Claim 5. 969 teaches in Fig. 3 about an apparatus, wherein at least a portion of the heatsink is coupled to the housing (at least a portion of the top and the side surfaces of item 111 are coupled to item 170). Regarding Claim 6. 969 teaches in Fig. 3 about an apparatus, wherein the one or more leads include a first lead being coupled to a first terminal (lead item 120 coupled to terminal item 152) in the one or more terminals of the clip; a second lead being coupled to a second terminal (lead item 130 coupled to terminal item 162) in the one or more terminals of the dip; and a third lead being coupled to the chip assembly pad (lead item 112d at least electrically coupled to item 181 through item 111). Regarding Claim 7. 969 teaches in Fig. 3 about an apparatus, wherein the first lead and second lead being configured to extend outside of the housing (lead item 120 and 130 extend outside of item 170), and the third lead being encapsulated by the housing (lead item 112d is at least partially encapsulated by item 170). Regarding Claim 8. 204 teaches in Fig. 7 about an apparatus, wherein the heat dissipation block is manufactured from a conductive material (“first binders 61 bonds the first pad part 31 and the source electrode 12 and electrically connects them”, [0084], Ln. 1-3; therefore, the heat dissipation block must be manufactured from a conductive material to achieve electrical connectivity). Regarding Claim 9. 204 teaches in Fig. 7 about an apparatus, wherein the conductive material or any combination thereof is not disclosed. 204 does not teach about an apparatus, wherein the conductive material includes at least one of the following· a copper, a copper alloy, a metal a metal alloy, and any combination thereof. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a conductive material including at least one a copper, a copper alloy, a metal a metal alloy, and any combination thereof, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416. Regarding Claim 10. 204 teaches in Fig. 7 about an apparatus, wherein the heat dissipation block has a predetermined thickness (item 31 has at least a predetermined thickness which has to be less that the thickness of the housing material item 2). Regarding Claim 11. 204 teaches in Fig. 7 about an apparatus, wherein the heat dissipation block is configured to remove heat from the semiconductor chip at least during and after application of a load dump pulse to the semiconductor chip (any type of “heat generated from the semiconductor element 1 is transferred to the first pad part 31” as taught by 204 in [0102], Ln. 3-4). Regarding Claim 12. 204 teaches in Fig. 7 about an apparatus, wherein the semiconductor chip includes a working area (area of item 1 between main and rear surface items 10a and 10b). Regarding Claim 13. 969 teaches in Fig. 1 about an apparatus, wherein the clip is configured to be coupled to the semiconductor chip working area (item 150 is configured to couple to the working area item 141). Regarding Claim 14. 204 teaches in Fig. 7 about an apparatus, wherein the heat dissipation block is configured to be positioned over the working area of the semiconductor chip (item 31 is positioned over the working area of item 1). Regarding Claim 15. 969 teaches in Fig. 2 about an apparatus, wherein the one or more clip terminals do not include one or more support protrusions extending laterally away from one or more edges of the one or more clip terminals. 969 does not teach about an apparatus, wherein the one or more clip terminals are configured to include one or more support protrusions extending laterally away from one or more edges of the one or more clip terminals. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have included one or more support protrusions extending laterally away from one or more edges of the one or more clip terminals, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04. Regarding Claim 16. 969 teaches in Fig. 1 about an apparatus, wherein the clip is configured to have a sharp-angled structure (sharp-angled structures joining items 151,152 and 153), wherein at least a portion of the sharp-angled structure of the clip is configured to extend away from the semiconductor (at least portion item 153 extends away from the semiconductor). 969 does not teach about an apparatus, wherein the clip is configured to have a curved structure. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have experimented with different degrees of curvature for the transitioning part of the clip between clip sub-section items 151,152 and 153, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04. Regarding Claim 18. 204 teaches in Fig. 7 about an apparatus, wherein the housing (item 2) is manufactured from at least one of the following: an epoxy compound, a plastic, and any combination thereof (“sealing resin 2 is formed as, for example, a black epoxy resin”, [0053], Ln. 3-4). Regarding Claim 19. 204 teaches in [0046] about an apparatus, further comprising a transient voltage suppression device (Zener diodes when connected across a voltage supply are well known in the art to be useful as transient voltage suppressors; therefore “the semiconductor element 1 … may be a two-terminal element such as a diode”, [0046], Ln. 5-7) Allowable Subject Matter Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897 /JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Sep 29, 2023
Application Filed
Apr 01, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604762
METHODS AND APPARATUS TO REDUCE THICKNESS OF ON-PACKAGE MEMORY ARCHITECTURES
2y 5m to grant Granted Apr 14, 2026
Patent 12598997
INDUCTOR WITH INTEGRATED MAGNETICS
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 2 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
4y 4m
Median Time to Grant
Low
PTA Risk
Based on 14 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month