DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of “Group II (Claims 8-15)” in the reply filed on February 10, 2026, is acknowledged. Applicant’s arguments regarding the restriction of “Group I (Claims 1-7)” are persuasive; therefore, restriction of Group I is hereby withdrawn.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Status of Claims
As of the amendment filed 02/10/2026. New claims 21-25 have been added all of which depend either directly or indirectly on independent claim 21. Claims 2 and 13 have been amended. Therefore, claims 1-26 remain pending, with claims 1, 8 and 21 being independent. All new matter was originally described in the specification, drawings, or claims as filed; therefore, no new matter has been added.
Claim Rejections - 35 USC § 102
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8-9,21-23 and 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2020/0266218 A1; Lilak et al.; 08/2020; (“218”).
Regarding Claim 8. 218 teaches in Figs. 3A,7B and 8B about a method comprising:
etching a first recess (Fig. 7B, left-side item 148) and a second recess (Fig. 7B, right-side item 148) in a fin-shaped multilayer semiconductor stack (Fig. 3A, fin item 146), each of the first recess and second recess segmenting the fin-shaped multilayer semiconductor stack into a plurality of nanostructures (Fig. 7B, items 148 segmented fin item 146 into a plurality of nanostructures);
growing (Fig. 8B, “the S/D material 118 may be formed by epitaxial growth”, [0038], Ln. 10-11) a first source/drain region (Fig. 8B, left-side item 118-1) in the first recess from an exposed end of a first nanostructure of the plurality of nanostructures (Fig. 7B, fin sidewalls of item 130-1 within left-side item 148), the first source/ drain region having a first conductivity type (Fig. 8B, “S/D material 118-1”, [0038], Ln. 4);
growing a second source/drain region (Fig. 8B, right-side item 118-1) in the second recess from an exposed end of a second nanostructure of the plurality of nanostructures (Fig. 7B, fin sidewalls of item 130-1 within right-side item 148), the second source/drain region having the first conductivity type (Fig. 8B, “S/D material 118-1”, [0038], Ln. 4);
growing a third source/drain region (Fig. 8B, left-side item 118-2) in the first recess from an exposed end of a third nanostructure of the plurality of nanostructures (Fig. 7B, fin sidewalls of item 130-2 within left-side item 148), the third source/drain region having the first conductivity type (Fig. 8B, “the material composition of the S/D material 118 used in different ones of the device strata 130 may be different”, [0021], Ln. 8-10), the third source/drain region disposed directly over the first source/drain region (Fig. 8B, left-side item 118-2 disposed directly over left-side item 118-1); and
growing a fourth source/drain region (Fig. 8B, right-side item 118-2) in the second recess from an exposed end of a fourth nanostructure of the plurality of nanostructures (Fig. 7B, fin sidewalls of item 130-2 within right-side item 148), the fourth source/drain region having a second conductivity type opposite the first conductivity type (Fig. 8B, “the material composition of the S/D material 118 used in different ones of the device strata 130 may be different”, [0021], Ln. 8-10), the fourth source/drain region disposed directly over the second source/drain region (Fig. 8B, right-side item 118-2 disposed directly over right-side item 118-1).
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Fig. 8B, annotated by Examiner regarding independent claim 8, from Lilak et al., “218”
Regarding Claim 9. 218 teaches in Fig. 8B about a method comprising:
wherein growing the first source/drain region and the second source/drain region occurs simultaneously (“forming S/D material 118-1 in the open volumes 148 in the device strata 130-1”, [0038], Ln. 2-3).
Regarding Claim 21. 218 teaches in Figs. 7A,7B,8B and 11A about a method comprising:
forming a first isolation structure (Fig. 7A, item 108 within left-side fin item 146) between a first semiconductor nanostructure (Fig. 7A, item 130-1 within left-side fin item 146) and a second semiconductor nanostructure (Fig. 7A, item 130-2 within left-side fin item 146);
growing (Fig. 8B, “the S/D material 118 may be formed by epitaxial growth”, [0038], Ln. 10-11) a first source/drain region (Fig. 8B, left-side item 118-1) that extends laterally from an end of the first semiconductor nanostructure (Fig. 7B, first source/drain region extends laterally from fin sidewalls of item 130-1 within left-side item 148), the first source/drain region having a first conductivity type (Fig. 8B, “S/D material 118-1”, [0038], Ln. 4);
growing a second source/drain region (Fig. 8B, left-side item 118-2) that extends laterally from an end of the second semiconductor nanostructure (Fig. 7B, second source/drain region extends laterally from fin sidewalls of item 130-2 within left-side item 148), the second source/drain region having the first conductivity type (Fig. 8B, “the material composition of the S/D material 118 used in different ones of the device strata 130 may be different”, [0021], Ln. 8-10), the second source/drain region aligned vertically with the first source/drain region (Fig. 8B, left-side items 118-2 and 118-1 are aligned vertically); and
forming a first gate structure around the first semiconductor nanostructure and the second semiconductor nanostructure (Fig. 11A, gate structure composed of items 124-1 and 124-2 are around items 130-1 and 130-2 within left-side fin item 146).
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Fig. 8B, annotated by Examiner regarding independent claim 21, from Lilak et al., “218”
Regarding Claim 22. 218 teaches in Fig. 11A about a method comprising:
wherein the first gate structure comprises a first region surrounding the first semiconductor nanostructure (Fig. 11A, region of gate sub-structure item 124-1 surrounding item 130-1 within left-side fin item 146) and a second region surrounding the second semiconductor nanostructure (Fig. 11A, region of gate sub-structure item 124-2 surrounding item 130-2 within left-side fin item 146), the first region and the second region each being formed of a work function tuning metal configured for the first conductivity type (“the material composition of the gate metal 124 used in different ones of the device strata 130 may be the same”, [0024], Ln. 13-15).
Regarding Claim 23. 218 teaches in Figs. 7A,7B,8B and 11A about a method comprising:
forming a second isolation structure (Fig. 7A, item 108 within middle fin item 146) between a third semiconductor nanostructure (Fig. 7A, item 130-1 within middle fin item 146) and a fourth semiconductor nanostructure (Fig. 7A, item 130-2 within middle fin item 146);
growing a third source/drain region (Fig. 8B, right-side item 118-1) that extends laterally from an end of the third semiconductor nanostructure (Fig. 7B, third source/drain region extends laterally from fin sidewalls of item 130-1 within right-side item 148), the third source/drain region having the first conductivity type (Fig. 8B, “S/D material 118-1”, [0038], Ln. 4);
growing a fourth source/drain region (Fig. 8B, right-side item 118-2) that extends laterally from an end of the fourth semiconductor nanostructure (Fig. 7B, fourth source/drain region extends laterally from fin sidewalls of item 130-2 within right-side item 148), the fourth source/drain region having a second conductivity type opposite the first conductivity type (Fig. 8B, “S/D material 118-2”, [0038], Ln. 5), the fourth source/drain region aligned vertically with the third source/drain region (Fig. 8B, right-side items 118-2 and 118-1 are aligned vertically); and
forming a second gate structure around the third semiconductor nanostructure and the fourth semiconductor nanostructure (Fig. 11A, gate structure composed of items 124-1 and 124-2 are around items 130-1 and 130-2 within middle fin item 146), wherein the second gate structure comprises a third region surrounding the third semiconductor nanostructure (Fig. 11A, region of gate sub-structure item 124-1 surrounding item 130-1 within middle fin item 146) and a fourth region surrounding the fourth semiconductor nanostructure (Fig. 11A, region of gate sub-structure item 124-2 surrounding item 130-2 within middle fin item 146), the third region being formed of a first work function tuning metal configured for the first conductivity type, the fourth region being formed of a second work function tuning metal configured for the second conductivity type (“the material composition of the gate metal 124 used in different ones of the device strata 130 may be different”, [0024], Ln. 9-11).
Regarding Claim 25. 218 teaches in Fig. 8B about a method comprising:
wherein the first source/drain region and the second source/drain region are grown in different growth processes (“forming an insulating material 120 on the S/D material 118-1, and then forming S/D material 118-2”, [0038], Ln. 3-5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being obvious over US 2020/0266218 A1; Lilak et al.; 08/2020; (“218”) in view of US 11,177,258 B2; Xie et al.; 11/2021; (“258”).
Regarding Claim 1. 218 teaches in Figs. 3A,7B and 8B about a method comprising:
forming a fin (Fig. 3A, item 146) extending vertically from a substrate (Fig. 3A, item 102), the fin including a lower semiconductor nanostructure (Fig. 3A, item 130-1), an upper semiconductor nanostructure (Fig. 3A, item 130-2), and a dummy semiconductor nanostructure (Fig. 3A, item 108) disposed between the lower semiconductor nanostructure and the upper semiconductor nanostructure (Fig. 3A, item 108 is disposed between items 130-1 and 130-2);
etching a first recess (Fig. 7B, left-side item 148) and a second recess (Fig. 7B, right-side item 148) in the fin through the upper semiconductor nanostructure, the dummy semiconductor nanostructure, and the lower semiconductor nanostructure (Fig. 7B, left-side and right-side items 148 are etched in the fin item 146 through items 130-2,130-1 and 108), the etching forming first sidewalls of the upper semiconductor nanostructure in the first recess (Fig. 7B, fin sidewalls of item 130-2 within left-side item 148) and second sidewalls of the lower semiconductor nanostructure in the first recess (Fig. 7B, fin sidewalls of item 130-1 within left-side item 148), the etching forming third sidewalls of the upper semiconductor nanostructure in the second recess (Fig. 7B, fin sidewalls of item 130-2 within right-side item 148) and fourth sidewalls of the lower semiconductor nanostructure in the second recess (Fig. 7B, fin sidewalls of item 130-1 within right-side item 148);
growing (Fig. 8B, “the S/D material 118 may be formed by epitaxial growth”, [0038], Ln. 10-11) a first lower semiconductor structure (Fig. 8B, left-side item 118-1) from the second sidewalls and a second lower semiconductor structure (Fig. 8B, right-side item 118-1) from the fourth sidewalls, the first lower semiconductor structure and second lower semiconductor structure having a first conductivity type (Fig. 8B, “S/D material 118-1”, [0038], Ln. 4); and
growing a first upper semiconductor structure (Fig. 8B, left-side item 118-2) from the first sidewalls and a second upper semiconductor structure (Fig. 8B, right-side item 118-2) from the third sidewalls, the first upper semiconductor structure having a second conductivity type opposite the first conductivity type (Fig. 8B, “the material composition of the S/D material 118 used in different ones of the device strata 130 may be different”, [0021], Ln. 8-10), the second upper semiconductor structure having the first conductivity type (Fig. 8B, “the material composition of the S/D material 118 used in different ones of the device strata 130 may be different”, [0021], Ln. 8-10).
218 does not teach about a method comprising:
replacing the dummy semiconductor nanostructure with a first isolation structure.
258 teaches in Figs. 11 and 15 about a method comprising:
replacing the dummy semiconductor nanostructure (Fig. 11, item 218’) with a first isolation structure (Fig. 15, “sacrificial nanosheets 218' … can be selectively removed … Dielectric spacers 1502 are then formed”, Col. 11, Ln. 13-17).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the replacement of a dummy semiconductor nanostructure with an isolation structure of 258 to provide a dielectric structure between the upper and lower semiconductor nanostructures in 218 in order to electrically isolate the upper and lower semiconductor nanostructures as taught by 258 in Figs. 13-15 and Col. 11, Ln. 13-17.
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Fig. 8B, annotated by Examiner regarding independent claim 1, from Lilak et al., “218”
Allowable Subject Matter
Claims 2-7,10-15 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
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