DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/23/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (20100055898) in view of Park et al. (20200105578) further in view of Srivastava et al. (20190237356)
Regarding Claim 1, in Figs 1-8 and paragraph 0013-0025 and especially Fig. 8 and paragraph 0025, Chang et al. discloses a semiconductor device, comprising: a substrate 10; a first dielectric layer,14 disposed on the substrate; a conductive layer 12a/12b, disposed on the first dielectric layer, wherein the conductive layer comprises a plurality of conductive wires 12a/12b; and an insulating capping layer 18, disposed on the conductive layer, and configured to enclose a plurality of first gaps between the conductive wires to form a plurality of air spacers 30. Chang et al. fails to disclose the newly added limitation of an insulating capping layer, disposed on and in contact with top surfaces of the conductive wires of the conductive layer, and configured to enclose a plurality of first gaps between the conductive wires to form a plurality of air spacers, wherein top openings of the air spacers are coplanar with the top surfaces of the conductive wires. However, Park et al. discloses a semiconductor device where in Figs. 1B and 16 and in paragraph 0029, the required limitation of an insulating capping layer, disposed on and in contact with top surfaces of the conductive wires of the conductive layer, and configured to enclose a plurality of first gaps between the conductive wires to form a plurality of air spacers, wherein top openings of the air spacers are coplanar with the top surfaces of the conductive wires (with elements 150, 130a, 130b and AG) are disclosed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the required limitation in Chang et al. as taught by Park et al. in order to reduce parasitic capacitance of the device (see paragraphs 0031 and 0062 of Park et al.)
Chang and Park et al. combination fails to disclose the newly added limitations of
“wherein the conductive layer comprises a plurality of conductive wires disposed on an in contact with a top surface of the first dielectric layer; wherein top openings of the air spacers are coplanar with the top surfaces of the conductive wires and are enclosed by the insulating capping layer.” However, Srivastava et al. discloses a semiconductor device where in Figs.9 and 15 with elements 10/12, 40 and 35, the required added limitations are disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required limitation with respect to contact and enclosing in Chang et al. and Park et al. as taught by Srivastava et al. in order to have interconnect/metallization/wiring configuration with increase performance.
Regarding Claim 2, in Chang et al, first insulating layer, disposed on the conductive wires. Furthermore, Srivastava et al. discloses the added limitation.
Regarding Claim 3, in Chang et al., second dielectric layer, disposed on the first insulating layer. Furthermore, Srivastava et al. discloses the added limitation.
Regarding Claim 4, in Chang et al, second insulating layer disposed on the second dielectric, and filling a plurality of second gaps of the second dielectric layer along lateral directions. Furthermore, Srivastava et al. discloses the added limitation.
Regarding Claim 5, in Chang et al, the second insulating layer, the first insulating layer, and the second dielectric layer above a first top surface of the conductive layer 12 are polished, so that a remaining first insulating layer and a remaining second dielectric layer are exposed. Furthermore, Srivastava et al. discloses the added limitation.
Regarding Claim 6, in Chang et al. the first top surface of the conductive layer 12 is coplanar with a second top surface of a remaining second insulating layer, a third top surface of the remaining first insulating layer, and a fourth top surface of the remaining second dielectric layer. Furthermore, Srivastava et al. discloses the added limitation.
Regarding Claim 7, in Chang et al. the second insulating layer, the first insulating layer, and the second dielectric layer are polished using a chemical mechanical polishing process.
Regarding Claim 8, in Chang et al. the remaining second dielectric layer is etched to form the plurality of first gaps.
Regarding Claim 9, in Chang et al. the remaining second dielectric layer is etched using a vapor etching process.
Regarding Claim 10, in Chang et al, the second dielectric layer comprises silicon oxide.
Regarding Claim 11, in Chang et al. the insulating capping layer 18, the first insulating layer, and the second insulating layer are made of a first insulating material.
Regarding Claim 12, in Chang et al., the first insulating material comprises silicon nitride.
Regarding Claim 13, in Chang et al. each air spacer is surrounded by the insulating capping layer, the remaining first insulating layer, the remaining second dielectric layer, and the remaining second insulating layer. With respect to the newly added directly limitation, Figs. 1B and 16 of Park et al. disclose this limitation. Furthermore, Srivastava et al. discloses the added limitation.
Regarding Claim 14, in Figs 1-8 and paragraph 0013-0025 and especially Fig. 8 and paragraph 0025, Chang et al. discloses a semiconductor structure, comprising: a substrate; a first dielectric layer, disposed on the substrate; a plurality of conductive wires, disposed on the first dielectric layer; and a plurality of air spacers, disposed at a plurality of first gaps between the conductive wires along lateral directions of the conductive wires. Chang et al. fails to disclose the required limitation of wherein top openings of the air spacers are coplanar with first top surfaces of the conductive wires.
However, Park et al. discloses a semiconductor device where in Figs. 1B and 16 and in paragraph 0029, the required newly added limitation, with elements 150, 130a, 130b and AG, is disclosed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the required limitation in Chang et al. as taught by Park et al. in order to reduce parasitic capacitance of the device (see paragraphs 0031 and 0062 of Park et al.)
Chang and Park et al. combination fails to disclose the newly added limitations with respect to contact. However, Srivastava et al. discloses a semiconductor device where in Figs.9 and 15 with elements 10/12, 40 and 35, the required added limitation with respect to contact is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required limitation with respect to contact in Chang et al. and Park et al. as taught by Srivastava et al. in order to have interconnect/metallization/wiring configuration with increase performance.
Regarding Claim 15, in Chang et al: a first insulating layer, disposed on the conductive wires. Furthermore, Srivastava et al. discloses the added limitation.
Regarding Claim 16, in Chang et al.: a second dielectric layer, disposed on the first insulating layer. Furthermore, Srivastava et al. discloses the added limitation.
Regarding Claim 17, in Chang et al.: a second insulating layer, disposed on the second dielectric layer, and fills a plurality of second gaps of the second dielectric layer along lateral directions. Furthermore, Srivastava et al. discloses the added limitation.
Regarding Claim 18, in Chang et al. the second insulating layer, the first insulating layer, and the second dielectric layer above first top surfaces of the conductive wires are polished, so that a remaining first insulating layer and a remaining second dielectric layer are exposed. Furthermore, Srivastava et al. discloses the added limitation.
Regarding Claim 19, in Chang et al. the remaining second dielectric layer is etched to form a plurality of second gaps.
Regarding Claim 20, in Chang et al, an insulating capping layer, disposed on the first top surfaces of the conductive wires to enclose the second gaps to form the air spacers. With respect to the newly added limitation of enclose top openings limitation, Figs. 1B and 16 of Park et al disclose this limitation. Furthermore, Srivastava et al. discloses the added limitation.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 1/29/2026