DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-2 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group (I), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 23 December 2025. Applicant’s election without traverse of Group II in the reply filed on 23 December 2025 is acknowledged. Claim and Specification Status The Examiner acknowledges the cancellation of claims 1-2 in the Applicant’s response dated 23 December 2025. The Examiner acknowledges the addition of new claims 21-22 in the Applicant’s response dated 23 December 2025. The new claims have been addressed below. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 3 -5 and 7-10 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ping-Wei Wang et al. (CN 113205844 A relying upon US 2023/0164971 A1 for English translation; herein “Wang”) . Regarding Claim 3 , Wang teaches a manufacturing method for a semiconductor device, comprising: forming an etching stop layer material (704, Fig. 7A and Fig. 8 , para [0054] describes wherein semiconductor layer 704 may provide an etch stop during a thinning process) a plurality of sheet layers (706 and 802, Fig. 7A and Fig. 8, para [0049] describes a semiconductor layer 706 that may include a plurality of stack layers such as suitable for forming nanowire channel regions in a gate all around device wherein said embodiment i s found in the plurality of channel layers 802 of Fig. 8) and a plurality of spacer layers (706 and 804, Fig. 7A and Fig. 8, para [0049] describes a semiconductor layer 706 that may include a plurality of stack layers such as suitable for forming nanowire channel regions in a gate all around device wherein said embodiment i s found in the plurality of spacer layers 80 4 of Fig. 8 describes in para [0059] ) on a substrate (702, Fig. 7A, para [0049] describes a substrate 702), wherein the sheet layers and the spacer layers are stacked to each other (802 and 804, Fig. 8, para [0059] describes a gate all around transistor including the plurality of sheet layers 802 and spacer layers 804 stacked to each other); forming a trench passing through the etching stop layer material, the sheet layers and the spacer layers (710 and 710a, Fig. 7B and Fig. 7C, para [0051] describes forming recesses 710 and 710a passing through sheet and spacer layers 706 and etching stop layer material 704) to form a plurality of etching stop layers (704, Fig. 7C depicts a plurality of etching stop layers 704 on each side of recess 710a), a first active structure (FAS, annotated Fig. 8 depicts a first active structure FAS of an embodiment of Fig. 7A-7G comprising stacked sheet layers 802 and spacer layers 804) and a second active structure (SAS, annotated Fig. 8 depicts a second active structure SAS of an embodiment of Fig. 7A-7G comprising stacked sheet layers 802 and spacer layers 804), wherein the first active structure comprises a plurality of first sheets and a plurality of first spacers, the first sheets and the first spacers are stacked to each other (FAS, 802 and 804, annotated Fig. 8 depicts the first active structure FAS of an embodiment of Fig. 7A-7G comprising sheet layers 802 and spacer layers 804 stacked to each other), the second active structure comprises a plurality of second sheets and a plurality of second spacers, the second sheets and the second spacers are stacked to each other (SAS, 802 and 804, annotated Fig. 8 depicts the second active structure SAS of an embodiment of Fig. 7A-7G comprising sheet layers 802 and spacer layers 804 stacked to each other); forming an epitaxy within the trench (714, Fig. 7E and Fig. 8, para [0053] describes forming source/drain epitaxial features in the trenches 710 and 710a); and forming a conductive via to connect with the epitaxy, wherein the conductive via has a height equal to or less than 35 nm ( 716, Fig. 7F and Fig. 8, para [0055] describes forming a contact or via to connect with the epitaxy 714 wherein the formed backside contact feature has a thickness in a range between 10 nm and 30 nm ). Regarding Claim 4 , Wang teaches the manufacturing method as claimed in claim 3, wherein in forming the etching stop layer material, the sheet layers and the spacer layers on the substrate, the substrate has a front side (F, annotated Fig. 7A depicts a front side F of the substrate 702) and back side opposite to the front side (B, annotated Fig. 7A depicts a back side B of the substrate 702 opposite of the front side F), and the front side faces up (F, annotated Fig. 7A depicts wherein the front side F faces up); before forming the conductive via, the manufacturing method further comprises: inverting the substrate, wherein the back side faces up (Fig. 7E, para [0053] describes flipping the substrate for backside processing before forming the back side conductive via 716 wherein flipping the substrate results in the back side B facing up). Regarding Claim 5 , Wang teaches the manufacturing method as claimed in claim 3, wherein in forming the etching stop layer material, the sheet layers and the spacer layers on the substrate, the etching stop layer material is formed of silicon germanium (704, Fig. 7A-7G and Fig. 8, para [0055] describes wherein the etching stop layer 704 is comprised of silicon germanium ( SiGe )). Regarding Claim 7 , Wang teaches the manufacturing method as claimed in claim 3, wherein before forming the epitaxy within the trench, the manufacturing method further comprising: removing a portion of the substrate to expose the etching stop layers (710a, Fig. 7C, para [0051] describes forming recess 710a removing a portion of the substrate 702 to expose etch stop layers 704). Regarding Claim 8 , Wang teaches the manufacturing method as claimed in claim 3, wherein before forming the epitaxy within the trench, the manufacturing method further comprising: etching a portion of the substrate by an etchant, wherein the etchant stops at the etching stop layers (710a, Fig. 7C, para [0051] describes forming recess 710a by a suitable selective etching process that stops at the backside of the etching stop layers 704 as shown in Fig. 7C). Regarding Claim 9 , Wang teaches the manufacturing method as claimed in claim 3, further comprising: removing the etching stop layers to expose the first active structure and the second active structure (710a, Fig. 7C and Fig. 8, para [0051] describes forming recesses 710a resulting in removing of etch stop layers 704 further exposing the first active structure FAS and second active structure SAS as shown in Fig. 7C and annotated Fig. 8). Regarding Claim 10 , Wang teaches the manufacturing method as claimed in claim 9, further comprising: planarizing the first active structure and the second active structure (para [0054] describes a backside grinding process of the active regions wherein the backside grinding process includes a chemical mechanical polishing process result ing in planarizing the first active structure FAS and second active structure SAS as shown in annotated Fig. 8). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 11, 13 , 15-17 and 19-2 1 are rejected under 35 U.S.C. 103 as being unpatentable over Ping-Wei Wang et al. (CN 113205844 A relying upon US 2023/0164971 A1 for English translation; herein “Wang”) in view of the following arguments: Regarding Claim 11 , Wang discloses all the limitations of claim 3. Wang discloses the manufacturing method as claimed in claim 3, further comprising: planarizing the first active structure and the second active structure by a second CMP (Fig. 7E and Fig. 8, para [0054] describes a chemical mechanical polishing process with a high polishing rate result ing compared to a first process involving a lower polishing rate in a process of planarizing the first active structure FAS and second active structure SAS as shown in annotated Fig. 8 ). Wang fails to explicitly disclose planarizing the first active structure and the second active structure by a first Chemical mechanical polishing (CMP) . However, Wang teaches planarizing the first active structure and the second active structure by a first Chemical mechanical polishing (CMP) (Fig. 7E and Fig. 8, para [0054] describes a grinding process of a polishing process wherein the polishing process is a CMP process further wherein the grinding process is a polishing process, such as a CMP process, with a lower polishing rate than a second CMP process in order to thin down the substrate comprising first active structure FAS and second active structures SAS) ; Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to disclose a manufacturing method comprising a first CMP process that describes a grinding process with a lower polishing rate in order to remove a larger portion of a substrate comprising first and second active structures at a faster rate and then following the bulk grinding process up with a second CMP process at a higher polishing rate resulting in a surface with enhanced flatness to provide the well-known advantage of shortening the duration of a manufacturing process by applying two separate CMP processes with different polishing rates to achieve a desired thickness and flatness. Regarding Claim 13 , Wang teaches a manufacturing method of a semiconductor device, comprising: forming an etching stop layer material (704, Fig. 7A, para [0054] describes wherein semiconductor layer 704 may provide an etch stop during a thinning process), a plurality of sheet layers (706 and 802, Fig. 7A and Fig. 8, para [0049] describes a semiconductor layer 706 that may include a plurality of stack layers such as suitable for forming nanowire channel regions in a gate all around device such as found in the plurality of channel layers 802 of Fig. 8) and a plurality of spacer layers (706 and 804, Fig. 7A and Fig. 8, para [0059] describes spacer layers in an embodiment of Fig. 7A as shown in Fig. 8) on a substrate (702, Fig. 7A, para [0049] describes a substrate 702), wherein the sheet layers and the spacer layers are stacked to each other (802 and 804, Fig. 8, para [0059] describes a gate all around transistor including the plurality of sheet layers 802 and spacer layers 804 stacked to each other); forming a trench passing through the etching stop layer material, the sheet layers and the spacer layers (710 and 710a, Fig. 7B and Fig. 7C, para [0051] describes forming recesses 710 and 710a passing through sheet and spacer layers 706 and etching stop layer material 704) to form a plurality of etching stop layers (704, Fig. 7C depicts a plurality of etching stop layers 704 on each side of recess 710a), a first active structure (FAS, annotated Fig. 8 depicts a first active structure FAS of an embodiment of Fig. 7A-7G comprising stacked sheet layers 802 and spacer layers 804) and a second active structure (SAS, annotated Fig. 8 depicts a second active structure SAS of an embodiment of Fig. 7A-7G comprising stacked sheet layers 802 and spacer layers 804), wherein the first active structure comprises a plurality of first sheets and a plurality of first spacers, the first sheets and the first spacers are stacked to each other (FAS, 802 and 804, annotated Fig. 8 depicts the first active structure FAS of an embodiment of Fig. 7A-7G comprising sheet layers 802 and spacer layers 804 stacked to each other), the second active structure comprises a plurality of second sheets and a plurality of second spacers, the second sheets and the second spacers are stacked to each other (SAS, 802 and 804, annotated Fig. 8 depicts the second active structure SAS of an embodiment of Fig. 7A-7G comprising sheet layers 802 and spacer layers 804 stacked to each other); forming an epitaxy within the trench (714, Fig. 7E and Fig. 8, para [0053] describes forming source/drain epitaxial features in the trenches 710 and 710a); and planarizing the first active structure and the second active structure by a second CMP , wherein the semiconductor device forms a planarized surface comprising the first active structure and the second active structure (Fig. 7E and Fig. 8, para [0054] describes a chemical mechanical polishing process with a high polishing rate result ing compared to a first process involving a lower polishing rate in a process of planarizing the first active structure FAS and second active structure SAS as shown in annotated Fig. 8 ). Wang fails to explicitly disclose planarizing the first active structure and the second active structure by a first CMP; and planarizing the first active structure and the second active structure by a second CMP, wherein the semiconductor device forms a planarized surface comprising the first active structure and the second active structure, and the planarized surface has a flatness less than 10 nm. However, Wang teaches planarizing the first active structure and the second active structure by a first CMP (Fig. 7E and Fig. 8, para [0054] describes a grinding process of a polishing process wherein the polishing process is a CMP process further wherein the grinding process is a polishing process, such as a CMP process, with a lower polishing rate than a second CMP process in order to thin down the substrate comprising first active structure FAS and second active structures SAS ) ; and planarizing the first active structure and the second active structure by a second CMP, wherein the semiconductor device forms a planarized surface comprising the first active structure and the second active structure (Fig. 7E and Fig. 8, para [0054] describes a chemical mechanical polishing process with a high polishing rate than a first polishing process result ing in a process of planarizing the first active structure FAS and second active structure SAS as shown in annotated Fig. 8 ) , and the planarized surface has a flatness less than 10 nm (Fig. 7E and Fig. 8, para [0054] describes a first grinding process that comprises a first lower polishing rate wherein the first grinding process may be a CMP process and a second CMP process with a higher polishing rate than the first CMP process , please see MPEP 2112.02 (I) wherein the process as recited by Lee is substantially identical to that of the claims therefore claimed properties, such as the structure of the resulting device comprising a planarized surface that has a flatness less than 10 nm, or functions are presumed to be present ). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to disclose a manufacturing method comprising a first CMP process that describes a grinding process with a lower polishing rate in order to remove a larger portion of a substrate comprising first and second active structures at a faster rate and then following the bulk grinding process up with a second CMP process at a higher polishing rate resulting in a surface with enhanced flatness to provide the well-known advantage of shortening the duration of a manufacturing process by applying two separate CMP processes with different polishing rates to achieve a desired thickness and flatness. Regarding Claim 15 , Wang teaches the manufacturing method as claimed in claim 13, further comprising: forming a conductive via to connect with the epitaxy, wherein the conductive via has a height equal to or less than 35 nm (716, Fig. 7F and Fig. 8, para [0055] describes forming a contact or via to connect with the epitaxy 714 wherein the formed backside contact feature has a thickness in a range between 10 nm and 30 nm). Regarding Claim 16 , Wang teaches the teaches the manufacturing method as claimed in claim 15 , wherein in forming the etching stop layer material, the sheet layers and the spacer layers on the substrate, the substrate has a front side (F, annotated Fig. 7A depicts a front side F of the substrate 702) and back side opposite to the front side (B, annotated Fig. 7A depicts a back side B of the substrate 702 opposite of the front side F), and the front side faces up (F, annotated Fig. 7A depicts wherein the front side F faces up); before forming the conductive via, the manufacturing method further comprises: inverting the substrate, wherein the back side faces up (Fig. 7E, para [0053] describes flipping the substrate for backside processing before forming the back side conductive via 716 wherein flipping the substrate results in the back side B facing up). Regarding Claim 17 , Wang teaches the manufacturing method as claimed in claim 1 3, wherein in forming the etching stop layer material, the sheet layers and the spacer layers on the substrate, the etching stop layer material is formed of silicon germanium (704, Fig. 7A-7G and Fig. 8, para [0055] describes wherein the etching stop layer 704 is comprised of silicon germanium ( SiGe )). Regarding Claim 19 , Wang teaches the manufacturing method as claimed in claim 1 3, wherein before forming the epitaxy within the trench, the manufacturing method further comprising: removing a portion of the substrate to expose the etching stop layers (710a, Fig. 7C, para [0051] describes forming recess 710a removing a portion of the substrate 702 to expose etch stop layers 704). Regarding Claim 20 , Wang teaches the manufacturing method as claimed in claim 13, wherein before forming the epitaxy within the trench, the manufacturing method further comprising: etching a portion of the substrate by an etchant, wherein the etchant stops at the etching stop layers (710a, Fig. 7C, para [0051] describes forming recess 710a by a suitable selective etching process that stops at the backside of the etching stop layers 704 as shown in Fig. 7C); and removing the etching stop layers to expose the first active structure and the second active structure (710a, Fig. 7C and Fig. 8, para [0051] describes forming recesses 710a resulting in removing of etch stop layers 704 further exposing the first active structure FAS and second active structure SAS as shown in Fig. 7C and annotated Fig. 8). Regarding Claim 21 , Wang teaches a manufacturing method of a semiconductor device, comprising: forming an etching stop layer material (704, Fig. 7A, para [0054] describes wherein semiconductor layer 704 may provide an etch stop during a thinning process), a plurality of sheet layers (706 and 802, Fig. 7A and Fig. 8, para [0049] describes a semiconductor layer 706 that may include a plurality of stack layers such as suitable for forming nanowire channel regions in a gate all around device such as found in the plurality of channel layers 802 of Fig. 8) and a plurality of spacer layers (706 and 804, Fig. 7A and Fig. 8, para [0059] describes spacer layers in an embodiment of Fig. 7A as shown in Fig. 8) on a substrate (702, Fig. 7A, para [0049] describes a substrate 702), wherein the sheet layers and the spacer layers are stacked to each other (802 and 804, Fig. 8, para [0059] describes a gate all around transistor including the plurality of sheet layers 802 and spacer layers 804 stacked to each other) and the etching stop layer material is closer the substrate than the sheet layers and the spacer layers (702, 704 and 706, Fig. 7A, para [0049] describes wherein the etching stop layer material 704 is formed over the substrate 702 and semiconductor layer 706 comprising the sheet layers 802 and spacer layers 804 as shown in Fig. 8, are formed over the etching stop layer material 704 resulting in etching stop layer material 704 being closer to the substrate 704 than the sheet layers 802/706 and spacer layers 804/706) ; forming a trench passing through the etching stop layer material, the sheet layers and the spacer layers (710 and 710a, Fig. 7B and Fig. 7C, para [0051] describes forming recesses 710 and 710a passing through sheet and spacer layers 706 and etching stop layer material 704) to form a plurality of etching stop layers (704, Fig. 7C depicts a plurality of etching stop layers 704 on each side of recess 710a), a first active structure (FAS, annotated Fig. 8 depicts a first active structure FAS of an embodiment of Fig. 7A-7G comprising stacked sheet layers 802 and spacer layers 804) and a second active structure (SAS, annotated Fig. 8 depicts a second active structure SAS of an embodiment of Fig. 7A-7G comprising stacked sheet layers 802 and spacer layers 804), wherein the first active structure comprises a plurality of first sheets and a plurality of first spacers, the first sheets and the first spacers are stacked to each other (FAS, 802 and 804, annotated Fig. 8 depicts the first active structure FAS of an embodiment of Fig. 7A-7G comprising sheet layers 802 and spacer layers 804 stacked to each other), the second active structure comprises a plurality of second sheets and a plurality of second spacers, the second sheets and the second spacers are stacked to each other (SAS, 802 and 804, annotated Fig. 8 depicts the second active structure SAS of an embodiment of Fig. 7A-7G comprising sheet layers 802 and spacer layers 804 stacked to each other); forming an epitaxy within the trench (714, Fig. 7E and Fig. 8, para [0053] describes forming source/drain epitaxial features in the trenches 710 and 710a); and planarizing the first active structure and the second active structure by a second CMP , wherein the semiconductor device forms a planarized surface comprising the first active structure and the second active structure ( Fig. 7E and Fig. 8, para [0054] describes a chemical mechanical polishing process with a high polishing rate result ing compared to a first process involving a lower polishing rate in a process of planarizing the first active structure FAS and second active structure SAS as shown in annotated Fig. 8 ) . Wang fails to explicitly disclose planarizing the first active structure and the second active structure by a first CMP; and planarizing the first active structure and the second active structure by a second CMP, wherein the semiconductor device forms a planarized surface comprising the first active structure and the second active structure, and the planarized surface has a flatness less than 10 nm. However, Wang teaches planarizing the first active structure and the second active structure by a first CMP (Fig. 7E and Fig. 8, para [0054] describes a grinding process of a polishing process wherein the polishing process is a CMP process further wherein the grinding process is a polishing process, such as a CMP process, with a lower polishing rate than a second CMP process in order to thin down the substrate comprising first active structure FAS and second active structures SAS) ; and planarizing the first active structure and the second active structure by a second CMP, wherein the semiconductor device forms a planarized surface comprising the first active structure and the second active structure (Fig. 7E and Fig. 8, para [0054] describes a chemical mechanical polishing process with a high polishing rate than a first polishing process result ing in a process of planarizing the first active structure FAS and second active structure SAS as shown in annotated Fig. 8 ) , and the planarized surface has a flatness less than 10 nm (Fig. 7E and Fig. 8, para [0054] describes a first grinding process that comprises a first lower polishing rate wherein the first grinding process may be a CMP process and a second CMP process with a higher polishing rate than the first CMP process, please see MPEP 2112.02 (I) wherein the process as recited by Lee is substantially identical to that of the claims therefore claimed properties, such as the structure of the resulting device comprising a planarized surface that has a flatness less than 10 nm, or functions are presumed to be present). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to disclose a manufacturing method comprising a first CMP process that describes a grinding process with a lower polishing rate in order to remove a larger portion of a substrate comprising first and second active structures at a faster rate and then following the bulk grinding process up with a second CMP process at a higher polishing rate resulting in a surface with enhanced flatness to provide the well-known advantage of shortening the duration of a manufacturing process by applying two separate CMP processes with different polishing rates to achieve a desired thickness and flatness. Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ping-Wei Wang et al. (CN 113205844 A relying upon US 2023/0164971 A1 for English translation; herein “Wang”) in view of Chung-Liang Cheng et al. (US 2022/0310638 A1; hereinafter “Cheng”). Regarding Claim 6 , Wang discloses all the limitations of claim 3. Wang fails to explicitly disclose the manufacturing method as claimed in claim 3, wherein in forming the etching stop layer material, the sheet layers and the spacer layers on the substrate, the etching stop layer material and each spacer layer are formed of the same material. However, Cheng teaches a similar manufacturing method, wherein in forming the etching stop layer material, the sheet layers and the spacer layers on the substrate, the etching stop layer material ( 304, Fig. 3B, para [0021] describes a buried layer 304 comprised of SiGe in the substrate 302 wherein buried layer 304 is used as an etching stop layer material in a grinding process as described in para [0048] ) and each spacer layer are formed of the same material (322, Fig. 3B, para [0023] describes a nanostructure spacer layer 322 comprised of a same SiGe material as etching stop layer material 304) . Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Wang with Cheng to further disclose a manufacturing method wherein an etching stop layer material and a plurality of spacer layers are formed of a same material in order to provide the well-known advantage of simplifying the manufacturing process through using similar etch selective materials throughout a device requiring fewer etchant or chemicals used in the removal of sacrificial layers in a manufacturing process resulting in lower costs and reduced manufacturing times. Regarding Claim 18 , Wang discloses all the limitations of claim 13. Wang fails to explicitly disclose the manufacturing method as claimed in claim 1 3, wherein in forming the etching stop layer material, the sheet layers and the spacer layers on the substrate, the etching stop layer material and each spacer layer are formed of the same material. However, Cheng teaches a similar manufacturing method, wherein in forming the etching stop layer material, the sheet layers and the spacer layers on the substrate, the etching stop layer material ( 304, Fig. 3B, para [0021] describes a buried layer 304 comprised of SiGe in the substrate 302 wherein buried layer 304 is used as an etching stop layer material in a grinding process as described in para [0048] ) and each spacer layer are formed of the same material (322, Fig. 3B, para [0023] describes a nanostructure spacer layer 322 comprised of a same SiGe material as etching stop layer material 304) . Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Wang with Cheng to further disclose a manufacturing method wherein an etching stop layer material and a plurality of spacer layers are formed of a same material in order to provide the well-known advantage of simplifying the manufacturing process through using similar etch selective materials throughout a device requiring fewer etchant or chemicals used in the removal of sacrificial layers in a manufacturing process resulting in lower costs and reduced manufacturing times. Claims 12, 14 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Ping-Wei Wang et al. (CN 113205844 A relying upon US 2023/0164971 A1 for English translation; herein “Wang”) in view of Krishna Chetry et al. (US 2023 / 0005756 A1; hereinafter “ Chetry ”). Regarding Claim 12 , Wang discloses all the limitations of claim 11. Wang discloses the manufacturing method as claimed in claim 11, wherein in planarizing the first active structure and the second active structure by the second CMP (Fig. 7E and Fig. 8, para [0054] describes a chemical mechanical polishing process with a high polishing rate resulting compared to a first process involving a lower polishing rate in a process of planarizing the first active structure FAS and second active structure SAS as shown in annotated Fig. 8), a second planarized surface is formed, and a second distance between the second planarized surface and the epitaxy is equal to or less than 35 nm (716, Fig. 7F and Fig. 8, para [0055] describes forming a contact or via to connect with the epitaxy 714 wherein the formed backside contact feature has a thickness in a range between 10 nm and 30 nm further wherein an upper surface of the formed backside contact feature comprises an upper second planarized surface resulting in a second distance between the second planarized surface and the epitaxy being equal to or less than 35 nm). Wang fails to explicitly disclose wherein in planarizing the first active structure and the second active structure by the first CMP, a first planarized surface is formed, and a first distance between the first planarized surface and the epitaxy ranges 40 nm and 45 nm . However, Chetry discloses a similar substrate backside removal CMP process, wherein in planarizing the first active structure and the second active structure by the first CMP (204, Fig. 2, para [0047] describes a first CMP process used to thin a device wafer from a particular thickness to a reduced thickness) , a first planarized surface is formed (para [0048] describes reducing a thickness of a backside of a device wafer until it reaches a particular thickness at any given point along a surface, resulting in a first planarized surface). Chetry fails to explicitly disclose wherein in planarizing the first active structure and the second active structure by the first CMP, a first distance between the first planarized surface and the epitaxy ranges 40 nm and 45 nm . However, Chetry discloses reducing a thickness of a device wafer to a non-limiting nonexclusive example of approximately 250 nm (para [0049]). Chetry further describes wherein one or more CMP parameters, such as a thickness profile of the resulting device wafer, may be adjusted before or during the CMP process which may provide the advantage of reducing or eliminating the formation of defects in the thinner regions of the post-ground device wafer (para [0048]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different thicknesses of a resulting substrate comprising a first and second active region and to further reduce the thickness of said resulting substrate to a range between 40 nm and 45 nm in order to provide the advantage of achieving a thickness close to a desired final thickness resulting from a second CMP process so that a second CMP process with a higher polishing rate does not have to polish a bulk portion of the substrate that may have been achieved in the first CMP process reducing the manufacturing time and cost associated with the first and second CMP processes. Furthermore, Chetry describes wherein the resulting thickness of the first CMP process may be approximately 1.66 times the resulting thickness of a second CMP process (para [0049] and para [0052] see MPEP 2144.04 (IV)(A) and MPEP 2144.05 (II)(A)(B) ) wherein Lee discloses a second thickness may be in a range of 10 nm to 30 nm wherein a second thickness from Lee being 25 nm keeping a same aspect ratio with the first and second thickness of Chetry would result in a first thickness of 41.5 nm from a first CMP process. Regarding Claim 14 , Wang discloses all the limitations of claim 13. Wang discloses the manufacturing method as claimed in claim 1 3 , wherein in planarizing the first active structure and the second active structure by the second CMP (Fig. 7E and Fig. 8, para [0054] describes a chemical mechanical polishing process with a high polishing rate resulting compared to a first process involving a lower polishing rate in a process of planarizing the first active structure FAS and second active structure SAS as shown in annotated Fig. 8), a second planarized surface is formed, and a second distance between the second planarized surface and the epitaxy is equal to or less than 35 nm (716, Fig. 7F and Fig. 8, para [0055] describes forming a contact or via to connect with the epitaxy 714 wherein the formed backside contact feature has a thickness in a range between 10 nm and 30 nm further wherein an upper surface of the formed backside contact feature comprises an upper second planarized surface resulting in a second distance between the second planarized surface and the epitaxy being equal to or less than 35 nm). Wang fails to explicitly disclose wherein in planarizing the first active structure and the second active structure by the first CMP, a first planarized surface is formed, and a first distance between the first planarized surface and the epitaxy ranges 40 nm and 45 nm . However, Chetry discloses a similar substrate backside removal CMP process, wherein in planarizing the first active structure and the second active structure by the first CMP (204, Fig. 2, para [0047] describes a first CMP process used to thin a device wafer from a particular thickness to a reduced thickness) , a first planarized surface is formed (para [0048] describes reducing a thickness of a backside of a device wafer until it reaches a particular thickness at any given point along a surface, resulting in a first planarized surface). Chetry fails to explicitly disclose wherein in planarizing the first active structure and the second active structure by the first CMP, a first distance between the first planarized surface and the epitaxy ranges 40 nm and 45 nm . However, Chetry discloses reducing a thickness of a device wafer to a non-limiting nonexclusive example of approximately 250 nm (para [0049]). Chetry further describes wherein one or more CMP parameters, such as a thickness profile of the resulting device wafer, may be adjusted before or during the CMP process which may provide the advantage of reducing or eliminating the formation of defects in the thinner regions of the post-ground device wafer (para [0048]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different thicknesses of a resulting substrate comprising a first and second active region and to further reduce the thickness of said resulting substrate to a range between 40 nm and 45 nm in order to provide the advantage of achieving a thickness close to a desired final thickness resulting from a second CMP process so that a second CMP process with a higher polishing rate does not have to polish a bulk portion of the substrate that may have been achieved in the first CMP process reducing the manufacturing time and cost associated with the first and second CMP processes. Furthermore, Chetry describes wherein the resulting thickness of the first CMP process may be approximately 1.66 times the resulting thickness of a second CMP process (para [0049] and para [0052] see MPEP 2144.04 (IV)(A) and MPEP 2144.05 (II)(A)(B) ) wherein Lee discloses a second thickness may be in a range of 10 nm to 30 nm wherein a second thickness from Lee being 25 nm keeping a same aspect ratio with the first and second thickness of Chetry would result in a first thickness of 41.5 nm from a first CMP process. Regarding Claim 22 , Wang discloses all the limitations of claim 21. Wang discloses the manufacturing method as claimed in claim 21 , wherein in planarizing the first active structure and the second active structure by the second CMP (Fig. 7E and Fig. 8, para [0054] describes a chemical mechanical polishing process with a high polishing rate resulting compared to a first process involving a lower polishing rate in a process of planarizing the first active structure FAS and second active structure SAS as shown in annotated Fig. 8), a second planarized surface is formed, and a second distance between the second planarized surface and the epitaxy is equal to or less than 35 nm (716, Fig. 7F and Fig. 8, para [0055] describes forming a contact or via to connect with the epitaxy 714 wherein the formed backside contact feature has a thickness in a range between 10 nm and 30 nm further wherein an upper surface of the formed backside contact feature comprises an upper second planarized surface resulting in a second distance between the second planarized surface and the epitaxy being equal to or less than 35 nm). Wang fails to explicitly disclose wherein in planarizing the first active structure and the second active structure by the first CMP, a first planarized surface is formed, and a first distance between the first planarized surface and the epitaxy ranges 40 nm and 45 nm . However, Chetry discloses a similar substrate backside removal CMP process, wherein in planarizing the first active structure and the second active structure by the first CMP (204, Fig. 2, para [0047] describes a first CMP process used to thin a device wafer from a particular thickness to a reduced thickness) , a first planarized surface is formed (para [0048] describes reducing a thickness of a backside of a device wafer until it reaches a particular thickness at any given point along a surface, resulting in a first planarized surface). Chetry fails to explicitly disclose wherein in planarizing the first active structure and the second active structure by the first CMP, a first distance between the first planarized surface and the epitaxy ranges 40 nm and 45 nm . However, Chetry discloses reducing a thickness of a device wafer to a non-limiting nonexclusive example of approximately 250 nm (para [0049]). Chetry further describes wherein one or more CMP parameters, such as a thickness profile of the resulting device wafer, may be adjusted before or during the CMP process which may provide the advantage of reducing or eliminating the formation of defects in the thinner regions of the post-ground device wafer (para [0048]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different thicknesses of a resulting substrate comprising a first and second active region and to further reduce the thickness of said resulting substrate to a range between 40 nm and 45 nm in order to provide the advantage of achieving a thickness close to a desired final thickness resulting from a second CMP process so that a second CMP process with a higher polishing rate does not have to polish a bulk portion of the substrate that may have been achieved in the first CMP process reducing the manufacturing time and cost associated with the first and second CMP processes. Furthermore, Chetry describes wherein the resulting thickness of the first CMP process may be approximately 1.66 times the resulting thickness of a second CMP process (para [0049] and para [0052] see MPEP 2144.04 (IV)(A) and MPEP 2144.05 (II)(A)(B) ) wherein Lee discloses a second thickness may be in a range of 10 nm to 30 nm wherein a second thickness from Lee being 25 nm keeping a same aspect ratio with the first and second thickness of Chetry would result in a first thickness of 41.5 nm from a first CMP process. Claims 13 , 15-17 and 19- 21 are rejected under 35 U.S.C. 103 as being unpatentable over Ping-Wei Wang et al. (CN 113205844 A relying upon US 2023/0164971 A1 for English translation; herein “Wang”) in view of Heesung Yang et al. (US 2023/0131912 A1; hereinafter “Yang”). Regarding Claim 13 , Wang teaches a manufacturing method of a semiconductor device, comprising: forming an etching stop layer material (704, Fig. 7A, para [0054] describes wherein semiconductor layer 704 may provide an etch stop during a thinning process), a plurality of sheet layers (706 and 802, Fig. 7A and Fig. 8, para [0049] describes a semiconductor layer 706 that may include a plurality of stack layers such as suitable for forming nanowire channel regions in a gate all around device such as found in the plurality of channel layers 802 of Fig. 8) and a plurality of spacer layers (706 and 804, Fig. 7A and Fig. 8, para [0059] describes spacer layers in an embodiment of Fig. 7A as shown in Fig. 8) on a substrate (702, Fig. 7A, para [0049] describes a substrate 702), wherein the sheet layers and the spacer layers are stacked to each other (802 and 804, Fig. 8, para [0059] describes a gate all around transistor including the plurality of sheet layers 802 and spacer layers 804 stacked to each other); forming a trench passing through the etching stop layer material, the sheet layers and the spacer layers (710 and 710a, Fig. 7B and Fig. 7C, para [0051] describes forming recesses 710 and 710a passing through sheet and spacer layers 706 and etching stop layer material 704) to form a plurality of etching stop layers (704, Fig. 7C depicts a plurality of etching stop layers 704 on each side of recess 710a), a first active structure (FAS, annotated Fig. 8 depicts a first active structure FAS of an embodiment of Fig. 7A-7G comprising stacked sheet layers 802 and spacer layers 804) and a second active structure (SAS, annotated Fig. 8 depicts a second active structure SAS of an embodiment of Fig. 7A-7G comprising stacked sheet layers 802 and spacer layers 804), wherein the first active structure comprises a plurality of first sheets and a plurality of first spacers, the first sheets and the first spacers are stacked to each other (FAS, 802 and 804, annotated Fig. 8 depicts the first active structure FAS of an embodiment of Fig. 7A-7G comprising sheet layers 802 and spacer layers 804 stacked to each other), the second active structure comprises a plurality of second sheets and a plurality of second spacers, the second sheets and the second spacers are stacked to each other (SAS, 802 and 804, annotated Fig. 8 depicts the second active structure SAS of an embodiment of Fig. 7A-7G comprising sheet layers 802 and spacer layers 804 stacked to each other); forming an epitaxy within the trench (714, Fig. 7E and Fig. 8, para [0053] describes forming source/drain epitaxial features in the trenches 710 and 710a); and planarizing the first active structure and the second active structure by a second CMP , wherein the semiconductor device forms a planarized surface comprising the first active structure and the second active structure (Fig. 7E and Fig. 8, para [0054] describes a chemical mechanical polishing process with a high polishing rate result ing compared to a first process involving a lower polishing rate in a process of planarizing the first active structure FAS and second active structure SAS as shown in annotated Fig. 8 ). Wang fails to explicitly disclose planarizing the first active structure and the second active structure by a first CMP; and planarizing the first active structure and the second active structure by a second CMP, wherein the semiconductor device forms a planarized surface comprising the first active structure and the second active structure, and the planarized surface has a flatness less than 10 nm. However, Wang teaches planarizing the first active structure and the second active structure by a first CMP (Fig. 7E and Fig. 8, para [0054] describes a grinding process of a polishing process wherein the polishing process is a CMP process further wherein the grinding process is a polishing process, such as a CMP process, with a lower polishing rate than a second CMP process in order to thin down the substrate comprising first active structure FAS and second active structures SAS) ; and planarizing the first active structure and the second active structure by a second CMP, wherein the semiconductor device forms a planarized surface comprising the first active structure and the second active structure (Fig. 7E and Fig. 8, para [0054] describes a chemical mechanical polishing process with a high polishing rate than a first polishing process result ing in a process of planarizing the first active structure FAS and second active structure SAS as shown in annotated Fig. 8 ) Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to disclose a manufacturing method comprising a first CMP process that describes a grinding process with a lower polishing rate in order to remove a larger portion of a substrate comprising first and second active structures at a faster rate and then following the bulk grinding process up with a second CMP process at a higher polishing rate resulting in a surface with enhanced flatness to provide the well-known advantage of shortening the duration of a manufacturing process by applying two separate CMP processes with different polishing rates to achieve a desired thickness and flatness. Wang may appear to fail to disclose the manufacturing method of claim 3, wherein the planarized surface has a flatness less than 10 nm . However, Yang teaches a manufacturing method, wherein the planarized surface has a flatness less than 10 nm (para [0169] describes a chemical mechanical polishing process performed on an inorganic layer in order to planarize an upper surface wherein para [0172] describes a surface roughness of the planarized surface resulting from the CMP process may be in a range of about 0 nm to 2 nm falling within an overall flatness range of less than 10 nm across a length of the planarized surface). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Wang with Yang to further disclose a manufacturing method wherein a CMP process produces a planarized surface with a flatness less than 10 nm in order to provide the advantage of removing defects such as particles existing on a layer surface reducing moisture permeability which could cause device defects (Yang, para [0171]) and to provide the well-known advantage of providing a substantially flat surface enabling increased adherence in further bonding and deposition steps. Regarding Claim 15 , the combination of Wang and Yang teaches the manufacturing method as claimed in claim 13, further comprising: forming a conductive via to connect with the epitaxy, wherein the conductive via has a height equal to or less than 35 nm ( Wang, 716, Fig. 7F and Fig. 8, para [0055] describes forming a contact or via to connect with the epitaxy 714 wherein the formed backside contact feature has a thickness in a range between 10 nm and 30 nm). Regarding Claim 16 , the combination of Wang and Yang teaches the teaches the manufacturing method as claimed in claim 15 , wherein in forming the etching stop layer material, the sheet layers and the spacer layers on the substrate, the substrate has a front side ( Wang, F, annotated Fig. 7A depicts a front side F of the substrate 702) and back side opposite to the front side ( Wang, B, annotated Fig. 7A depicts a back side B of the substrate 702 opposite of the front side F), and the front side faces up ( Wang, F, annotated Fig. 7A depicts wherein the front side F faces up); before forming the conductive via, the manufacturing method further comprises: inverting the substrate, wherein the back side faces up ( Wang, Fig. 7E, para [0053] describes flipping the substrate for backside processing before forming the back side conductive via 716 wherein flipping the substrate results in the back side B facing up). Regarding Claim 17 , the combination of Wang and Yang teaches the manufacturing method as claimed in claim 1 3, wherein in forming the etching stop layer material, the sheet layers and the spacer layers on the substrate, the etching stop layer material is formed of silicon germanium ( Wang, 704, Fig. 7A-7G and Fig. 8, para [0055] describes wherein the etching stop layer 704 is comprised of silicon germanium ( Si