Attorney Docket Number: TLCH/0082US
Filing Date: 10/04/2023
Inventor: Wang
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments filed 3/13/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA . In the event the determination of the status of the
application as to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis
(i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of
rejection if the prior art relied upon, and the rationale supporting the rejection, would be the
same under either status.
Claim Interpretation
Claim 14 recites the line “…a top surface of each of the plurality of insulation areas and a top surface of each of the plurality active areas are coplanar” which will be interpreted as “…a top surface of each insulation area of the plurality of insulation areas are coplanar and a top surface of each active area of the plurality active areas are coplanar”.
Acknowledgement
The Amendment filed on 3/13/2026, responding to the Office action mailed 12/18/2025, has been entered. Applicant amended claims 1, 8-10, 14, and 18, and cancelled claim 7. The present Office action is made with all the suggested amendments being fully considered.
Response to Amendments
Applicant’s amendments to the claims have overcome the respective claim rejections under 35 U.S.C. 112 and 35 U.S.C. 103, as previously formulated in the Non-Final Office action mailed on 12/18/2025. Accordingly, all previous claim rejections are hereby withdrawn. Accordingly, pending in this application are claims 1-6 and 8-20. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 10, 14-15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20210126087 A1) in view of Chen (US 20230144120 A1) further in view of Tung (US 12075609 B2).
Regarding claim 1, Huang (see, e.g., figs. 8 and 7C) shows most aspects of the invention, including a semiconductor structure comprising:
A substrate (e.g., semiconductor substrate 100), comprising an active area (e.g., active areas 150a, comprised of 152b + 156b + 154b) and a plurality of insulation areas (isolation structures 140 + paragraph 39 “the isolation structure 140 may be formed by depositing a silicon oxide layer”) surrounding the active area (e.g., active area 150b, comprised of 152b + 156b + 154b);
A plurality of word line structures (see, e.g., paragraph 48 “the first gate structure 180 and the second gate structure 182 serves as word lines (WL), while the third gate structure 184 and the fourth gate structure 186 serves as passing word lines (PWL)”), extending through the plurality of insulation areas (e.g., isolation structures 140 + paragraph 39 of Huang: “the isolation structure 140 may be formed by depositing a silicon oxide layer”) and the active area (e.g., active area 150b, comprised of 152b + 156b + 154b);
Wherein a first end (see, e.g., fig. 7C) of the active area (e.g., active area 150b, comprised of 152b + 156b + 154b) has a first head portion (e.g., first portion 152), a second end (see, e.g., fig. 7C) of the active area (e.g., active area 150b, comprised of 152b + 156b + 154b) has a second head portion (e.g., second portion 154), and a middle portion (see, e.g., fig. 7C) has a waist portion (e.g., third portion 156);
Wherein in a top view, the first head portion (e.g., first portion 152) and the second head portion (e.g., second portion 154) of the active area (e.g., active area 150b, comprised of 152b + 156b + 154b) have a first width (see, e.g., 152 and 154 width in fig. 7C, or fig. 2C), respectively, and the waist portion (e.g., third portion 156) of the active area (e.g., active area 150b, comprised of 152b + 156b + 154b) has a second width (see, e.g., 156 width in fig. 7C, or fig. 2C), and wherein the first width (see, e.g., 152 and 154 width in fig. 7C, or fig. 2C) is greater than the second width (see, e.g., 156 width in fig. 7C, or fig. 2C).
Huang (see, e.g., figs. 8 and 7C), however, fails to show a plurality of these active areas with a plurality of these word line structures, while it also fails to show wherein a depth of each of the plurality of word line structures in the plurality of active areas is identical to a depth of each of the plurality of word line structures in the plurality of insulation areas, and the plurality of insulation areas is between this plurality of active areas.
Chen (see, e.g., fig. 6), in a similar device to Huang, teaches a plurality of active areas (e.g., plurality of active areas 103) and a plurality of insulating areas (e.g., isolation regions 101) between the plurality of active areas (e.g., plurality of active areas 103).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the active area plurality and insulating area plurality stack-configuration of Chen within the device of Huang, expanding out the active area and insulating area configuration of Huang to this plurality setup, in order to achieve the expected result of increasing the transistor count, increasing the performance and capabilities within the device. Note that this extended semiconductor configuration would include the insulating area between the plurality of active areas, since the two areas alternate, as well as resulting in a greater number of substantially identical active areas, including additional pluralities of word line structures extending through each active area, substantially similar to the current embodiment of Huang.
In addition, it also would have been obvious to one of ordinary skill in the art to duplicate the semiconductor structure comprising the active area setup of Huang, around the current cross-section’s configuration, in order to increase the transistor count and thus improve the performance and capabilities within the semiconductor structure, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04. Note that these duplicated active and insulating areas would possess identical arrangements, hence the isolation material 140 would be configured between the original active area and the now duplicated active areas, and a greater plurality of word line structures would extend through the plurality of active areas, as the duplicated active areas are substantially similar in configuration and the current active area already comprises a plurality of extending word line structures.
Huang in view of Chen, however, fails to teach wherein a depth of each of the plurality of word line structures in the plurality of active areas is identical to a depth of each of the plurality of word line structures in the plurality of insulation areas.
Tung (see, e.g., fig. 4), in a similar device to Huang in view of Chen, teaches wherein a depth of each of a plurality of word line structures (e.g., plurality of word lines WL, see fig. 4) in a plurality of active areas (e.g., plurality of active areas AA1) is identical to a depth of each of the plurality of word line structures (e.g., plurality of word lines WL, see fig. 4) in a plurality of insulation areas (e.g., shallow trench isolations 301).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the identical word line depths of Tung within the word lines of the plurality of active areas and plurality of insulation areas of Huang in view of Chen, in order to provide a uniform electrical profile across the structure and maintain a consistent word-to-word dimensional layout, reducing potential word line resistance and capacitance throughout within the device.
Regarding claim 6, Huang (see, e.g., fig. 8) in view of Chen further in view of Tung teaches a plurality of source/drain regions (see, e.g., paragraph 60 of Huang: “The second segment 156b of the third portion 156 serves as a common source region of the transistors…The second segment 152b of the first portion 152 and the second segment 154b of the second portion 154 serve as drain regions of the transistors”) disposed in each of the plurality of active areas (e.g., added/duplicated active areas 150a) and between (e.g., note that the source/drains are located in the active areas, and the active area is between the plurality of insulation areas) the plurality of insulation areas (e.g., isolation structures 140 + paragraph 39 of Huang: “the isolation structure 140 may be formed by depositing a silicon oxide layer”).
Regarding claim 10, Huang (see, e.g., figs. 8 and 7C) shows most aspects of the invention, including a semiconductor structure comprising:
Providing a substrate (e.g., semiconductor substrate 100);
Forming (see, e.g., paragraph 37 “An isolation structure 140 is formed…”) a plurality of insulation areas (e.g., isolation structures 140 + paragraph 39 of Huang: “the isolation structure 140 may be formed by depositing a silicon oxide layer”) in the substrate (e.g., semiconductor substrate 100) to define an active area (e.g., active area 150a, comprised of 152a + 156a + 154a) on a top surface of the substrate (e.g., semiconductor substrate 100) has a first width (see, e.g., 152 and 154 width in fig. 7C, or fig. 2C), respectively, a middle portion (e.g., third portion 156) of the active area (e.g., active area 150a, comprised of 152a + 156a + 154a) on the top surface of the substrate (e.g., semiconductor substrate 100) has a second width (see, e.g., 156 width in fig. 7C, or fig. 2C), and wherein the first width (see, e.g., 152 and 154 width in fig. 7C, or fig. 2C) is greater than the second width (see, e.g., 156 width in fig. 7C, or fig. 2C).
Forming a plurality of word line structures (see, e.g., paragraph 48 “the first gate structure 180 and the second gate structure 182 serves as word lines (WL), while the third gate structure 184 and the fourth gate structure 186 serves as passing word lines (PWL)”) on the top surface of the substrate (e.g., semiconductor substrate 100), wherein the plurality of word line structures (e.g., active area 150a, comprised of 152a + 156a + 154a) extend through the plurality of insulation areas (e.g., isolation structures 140 + paragraph 39 of Huang: “the isolation structure 140 may be formed by depositing a silicon oxide layer”) and the active area (e.g., active area 150a, comprised of 152a + 156a + 154a).
Huang (see, e.g., figs. 8 and 7C), however, fails to show a plurality of these active areas, while it also fails to show the plurality of insulation areas is between this plurality of active areas, and wherein a depth of each of the plurality of word line structures in the plurality of active areas is identical to a depth of each of the plurality of word line structures in the plurality of insulation areas.
Chen (see, e.g., fig. 6), in a similar device to Huang, teaches a plurality of active areas (e.g., plurality of active areas 103) and a plurality of insulating areas (e.g., isolation regions 101) between the plurality of active areas (e.g., plurality of active areas 103).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the active area plurality and insulating area plurality stack-configuration of Chen within the device of Huang, expanding out the active area and insulating area configuration of Huang to this plurality setup, in order to achieve the expected result of increasing the transistor count, increasing the performance and capabilities within the device. Note that this extended semiconductor configuration would include the insulating area between the plurality of active areas, since the two areas alternate, as well as resulting in a greater number of substantially identical active areas, including additional pluralities of word line structures extending through each active area, substantially similar to the current embodiment of Huang.
In addition, it also would have been obvious to one of ordinary skill in the art to duplicate the semiconductor structure comprising the active area setup of Huang, around the current cross-section’s configuration, in order to increase the transistor count and thus improve the performance and capabilities within the semiconductor structure, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04. Note that these duplicated active and insulating areas would possess identical arrangements, hence the isolation material 140 would be configured between the original active area and the now duplicated active areas, and a greater plurality of word line structures would extend through the plurality of active areas, as the duplicated active areas are substantially similar in configuration and the current active area already comprises a plurality of extending word line structures.
Huang in view of Chen, however, fails to teach wherein a depth of each of the plurality of word line structures in the plurality of active areas is identical to a depth of each of the plurality of word line structures in the plurality of insulation areas.
Tung (see, e.g., fig. 4), in a similar device to Huang in view of Chen, teaches wherein a depth of each of a plurality of word line structures (e.g., plurality of word lines WL, see fig. 4) in a plurality of active areas (e.g., plurality of active areas AA1) is identical to a depth of each of the plurality of word line structures (e.g., plurality of word lines WL, see fig. 4) in a plurality of insulation areas (e.g., shallow trench isolations 301).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the identical word line depths of Tung within the word lines of the plurality of active areas and plurality of insulation areas of Huang in view of Chen, in order to provide a uniform electrical profile across the structure and maintain a consistent word-to-word dimensional layout, reducing potential word line resistance and capacitance throughout within the device.
Regarding claim 14, Huang (see, e.g., fig. 8) in view of Chen further in view of Tung teaches wherein after forming the plurality of insulation areas (e.g., isolation structures 140 + paragraph 39 of Huang: “the isolation structure 140 may be formed by depositing a silicon oxide layer”) and the plurality of active areas (e.g., extended active area 150a, comprised of 152a + 156a + 154a), a top surface of each insulation area of the plurality of insulation areas (e.g., isolation structures 140 + paragraph 39 of Huang: “the isolation structure 140 may be formed by depositing a silicon oxide layer”) are coplanar (e.g., note that isolation structures 140 have top surfaces on the same plane), and a top surface of each of the active areas (e.g., active area 150a, comprised of 152a + 156a + 154a) of the plurality of active areas (e.g., extended active area 150a, comprised of 152a + 156a + 154a) are coplanar.
Regarding claim 15, Huang (see, e.g., fig. 8) in view of Chen further in view of Tung teaches forming a plurality of source/drain regions (see, e.g., paragraph 60 of Huang: “The second segment 156b of the third portion 156 serves as a common source region of the transistors…The second segment 152b of the first portion 152 and the second segment 154b of the second portion 154 serve as drain regions of the transistors”) and between (e.g., note that the source/drains are located in the active areas, and the active area is between the plurality of insulation areas) the plurality of insulation areas (e.g., isolation structures 140 + paragraph 39 of Huang: “the isolation structure 140 may be formed by depositing a silicon oxide layer”).
Regarding claim 18, Huang (see, e.g., fig. 8) shows forming a plurality of word line structures (see, e.g., paragraph 48 “the first gate structure 180 and the second gate structure 182 serves as word lines (WL), while the third gate structure 184 and the fourth gate structure 186 serves as passing word lines (PWL)”) comprises forming a plurality of first trenches (see, e.g., trenches of fig. 8 or the trenches formed in fig. 5B(manufacturing step of fig. 8)) with a depth in the active area (e.g., active area 150a, comprised of 152a + 156a + 154a) and a depth of the insulation areas (e.g., isolation structures 140 + paragraph 39 of Huang: “the isolation structure 140 may be formed by depositing a silicon oxide layer”).
Huang (see, e.g., fig. 8), however, fails to show depositing a conductive layer in each of the plurality of the first trenches, while it also fails to show depositing a cap layer in each of the plurality of first trenches and on the conductive layer, while it also fails to show the depth in the active area is the depth of the insulation area.
Chen (see, e.g., fig. 6) teaches depositing a conductive layer (e.g., metal layer 165) in each of the plurality of first trenches (e.g., trenches of bit lines 160) and depositing a cap layer (e.g., capping layer 167) in each of the plurality of first trenches (e.g., trenches of bit lines 160) and on the conductive layer (e.g., metal layer 165).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the conductive layer and cap layer of Chen within the trench of Huang in view of Tung, as depositing the layers in this configuration was a well-known technique during fabrication of word/bit lines, as taught by Chen (see paragraph 30).
Tung (see, e.g., fig. 4), teaches forming a depth in the active area (e.g., active area AA1) and a plurality of trenches of the depth (see, e.g., paragraph 49) of the insulation areas (e.g., shallow trench isolations 301).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the shared trench depth configuration of Tung within the setup of Huang in view of Chen further in view of Tung, in order to achieve the expected result of providing a surface/geometry for equivalent-depth word line structures, in order to accommodate the equivalent-depth word line structures during fabrication of the device of Huang in view of Chen further in view of Tung.
Regarding claim 19, Huang (see, e.g., fig. 8) shows wherein forming the plurality of word line structures (see, e.g., paragraph 48 “the first gate structure 180 and the second gate structure 182 serves as word lines (WL), while the third gate structure 184 and the fourth gate structure 186 serves as passing word lines (PWL)”) comprises a dielectric liner (e.g., gate dielectric layer 160) in each of the plurality of first trenches (see, e.g., trenches of fig. 8 or the trenches formed in fig. 5B(manufacturing step of fig. 8)) prior to depositing the conductive layer (e.g., note that the gate dielectric layer 160 is formed immediately after forming the trench, see fig. 5A).
Regarding claim 20, Huang in view of Chen teaches further in view of Tung wherein the dielectric liner (e.g., gate dielectric layer 160) surrounds (e.g., note that the gate dielectric layer 160 is deposited directly into the formed trench and the conductive/cap layer of Chen were deposited into said trench, see rejection of claim 18) the conductive layer (e.g., metal layer 165) and the cap layer (e.g., capping layer 167).
Claims 2-5 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Chen further in view of Tung and Wang (US 20240334674 A1).
Regarding claim 2, Huang in view of Chen further in view of Tung fails to explicitly teach wherein a difference percentage between the first width and the second width is 20% to 30%.
Wang (see, e.g., fig. 8), in a similar device to Huang in view of Chen further in view of Tung, teaches a difference percentage between a first width (e.g., large width L21) and a second width (e.g., relatively small width L22) is 25% (see, e.g., paragraph 34 “… the top of the cross section of the active segment 210 in the second direction D2 has a relatively large width L21, for example, about 20 to 30 nanometers, while the bottom of the cross section of the active segment 210 in the second direction D2 has a relatively small width L22, for example, about 10 to 20 nanometers, ...0.75 times the width L21, but it is not limited thereto”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the widths of Wang within the two different widths of Huang in view of Chen further in view of Tung, as the magnitudes of 20 nm and 15 nm (note that .75 times 20 is 15, and 20:15 comprises a difference percentage of 25%) were well-known in the art at the time of filing the invention in order to maintain high transistor density and a small semiconductor structure size, as taught by Wang.
Regarding claim 3, Wang (see, e.g., fig. 8) teaches a ratio of the first width (e.g., large width L21) to the second width (e.g., relatively small width L22) substantially close to 10:8 (see, e.g., paragraph 34 “…which is about .5 to 0.75 times the width L21…” + note this upper bound is equivalent to a ratio of 10:7.5).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to modify Wang’s 15 nm width (.75 times the 20 nm length) to have a width of 16 nm (note that 20:16 comprises a ratio of 10:8) within Huang in view of Chen further in view of Tung since the dimension of the smaller width can be adjusted to accommodate carrier capacity/response speed in the middle portion of the structure. Further, a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties (Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed.Cir.1985)). In the instant case, process optimization will allow one of ordinary skill in the art to reach the ratio of 10:8 from the disclosed range of 10:7.5.
Regarding claim 4, Wang (see, e.g., fig. 8) teaches a ratio of the first width (e.g., large width L21) to the second width (e.g., relatively small width L22) is 10:7 (see, e.g., paragraph 34 “…which is about .5 to 0.75 times the width L21…” + note this range includes .7, which is equivalent to a ratio of 10:7).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the widths of Wang within the two different widths of Huang in view of Chen further in view of Tung, as the magnitudes of 20 nm and 14 nm (which is a ratio of 10:7) were well-known in the art at the time of filing the invention in order to maintain high transistor density and a small semiconductor structure size, as taught by Wang.
Regarding claim 5, Wang (see, e.g., fig. 8) teaches a first width (e.g., large width L21) is 20 nm (see, e.g., paragraph 34 “… the top of the cross section of the active segment 210 in the second direction D2 has a relatively large width L21, for example, about 20 to 30 nanometers,) and the second width (e.g., relatively small width L22) is 14 to 16 nm (see, e.g., paragraph 34 “…a relatively small width L22, for example, about 10 to 20 nanometers, ...0.75 times the width L21, but it is not limited thereto”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the widths of Wang within the two different widths of Huang in view of Chen further in view of Tung, as the magnitudes of 20 nm and 15 nm (note that .75 times 20 is 15) were well-known in the art at the time of filing the invention in order to maintain high transistor density and a small semiconductor structure size, as taught by Wang.
Regarding claim 12, Huang in view of Chen further in view of Tung fails to explicitly teach wherein a difference percentage between the first width and the second width is 20% to 30%.
Wang (see, e.g., fig. 8), in a similar device to Huang in view of Chen further in view of Tung, teaches a difference percentage between a first width (e.g., large width L21) and a second width (e.g., relatively small width L22) is 25% (see, e.g., paragraph 34 “… the top of the cross section of the active segment 210 in the second direction D2 has a relatively large width L21, for example, about 20 to 30 nanometers, while the bottom of the cross section of the active segment 210 in the second direction D2 has a relatively small width L22, for example, about 10 to 20 nanometers, ...0.75 times the width L21, but it is not limited thereto”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the widths of Wang within the two different widths of Huang in view of Chen further in view of Tung, as the magnitudes of 20 nm and 15 nm (note that .75 times 20 is 15, and 20:15 comprises a difference percentage of 25%) were well-known in the art at the time of filing the invention in order to maintain high transistor density and a small semiconductor structure size, as taught by Wang.
Regarding claim 13, Wang (see, e.g., fig. 8) teaches a first width (e.g., large width L21) is 20 nm (see, e.g., paragraph 34 “… the top of the cross section of the active segment 210 in the second direction D2 has a relatively large width L21, for example, about 20 to 30 nanometers…”) and the second width (e.g., relatively small width L22) is 14 to 16 nm (see, e.g., paragraph 34 “…a relatively small width L22, for example, about 10 to 20 nanometers, ...0.75 times the width L21, but it is not limited thereto”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the widths of Wang within the two different widths of Huang in view of Chen further in view of Tung, as the magnitudes of 20 nm and 15 nm (note that .75 times 20 is 15) were well-known in the art at the time of filing the invention in order to maintain high transistor density and a small semiconductor structure size, as taught by Wang.
Claims 8-9 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Chen further in view of Tung and Lu (US 20230115307 A1).
Regarding claim 8, Huang in view of Chen further in view of Tung fails to teach wherein each of the active areas is equipped with 3 to 4 word line structures on average.
Lu (see, e.g., fig. 4), in a similar device to Huang in view of Chen further in view of Tung, teaches an active area (e.g., active area 11) is equipped with 3 to 4 word line structures (see, e.g., paragraph 32 “The number of word line trenches 14 in each active area 11 may be one, two, three, or four, which will not be specifically limited here”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the 3-4 word line structure configuration of Lu within each active area of Huang in view of Chen further in view of Tung, in order to achieve the expected result of memory cells and read/write operations possible within each active area configuration.
Regarding claim 9, Huang (see, e.g., fig. 8) shows wherein one of the source/drain regions (see, e.g., paragraph 60 of Huang: “The second segment 156b of the third portion 156 serves as a common source region of the transistors…The second segment 152b of the first portion 152 and the second segment 154b of the second portion 154 serve as drain regions of the transistors”) collectively shares (e.g., note the shared adjacency of WL structure 180/182 and source/drain within active area 150a) the adjacent word line structures (see, e.g., paragraph 48 “the first gate structure 180 and the second gate structure 182 serves as word lines (WL), while the third gate structure 184 and the fourth gate structure 186 serves as passing word lines (PWL)”) and is controlled by the adjacent word line structures (see, e.g., paragraph 48 “the first gate structure 180 and the second gate structure 182 serves as word lines (WL), while the third gate structure 184 and the fourth gate structure 186 serves as passing word lines (PWL)”).
Regarding claim 16, Huang in view of Chen fails to teach wherein each of the active areas is equipped with 3 to 4 word line structures on average.
Lu (see, e.g., fig. 4), in a similar device to Huang in view of Chen further in view of Tung, teaches an active area (e.g., active area 11) is equipped with 3 to 4 word line structures (see, e.g., paragraph 32 “The number of word line trenches 14 in each active area 11 may be one, two, three, or four, which will not be specifically limited here”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the 3-4 word line structure configuration of Lu within each active area of Huang in view of Chen further in view of Tung, in order to achieve the expected result of memory cells and read/write operations possible within each active area configuration.
Regarding claim 17, Huang (see, e.g., fig. 8) shows wherein one of the source/drain regions (see, e.g., paragraph 60 of Huang: “The second segment 156b of the third portion 156 serves as a common source region of the transistors…The second segment 152b of the first portion 152 and the second segment 154b of the second portion 154 serve as drain regions of the transistors”) collectively shares (e.g., note the shared adjacency of WL structure 180/182 and source/drain within active area 150a) the adjacent word line structures (see, e.g., paragraph 48 “the first gate structure 180 and the second gate structure 182 serves as word lines (WL), while the third gate structure 184 and the fourth gate structure 186 serves as passing word lines (PWL)”) and is controlled by the adjacent word line structures (see, e.g., paragraph 48 “the first gate structure 180 and the second gate structure 182 serves as word lines (WL), while the third gate structure 184 and the fourth gate structure 186 serves as passing word lines (PWL)”).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (hereinafter Huang1) in view of Chen further in view of Tung and Huang (US 20210143261 A1) (hereinafter Huang2).
Regarding claim 11, Huang1 in view of Chen fails further in view of Tung to teach forming a mask on the top surface, exposing portions not covered by the mask, etching the exposed portions to form openings, and depositing a first dielectric layer in the openings and over the substrate.
Huang2 (see, e.g., figs. 20-21), in a similar device to Huang1 in view of Chen further in view of Tung, teaches forming a mask (e.g., fourth mask segment 607) on the top surface of a substrate (e.g., first insulating layer 111), exposing portions (see, e.g., mask openings in in fig. 2) not covered by the mask (e.g., fourth mask segment 607), etching (see, e.g., paragraph 82 “…an etch process, such as an anisotropic dry etch process, may be performed to form the plurality of word line trenches 311 so as to penetrate through the first insulating layer 111 and into the substrate 101…”) the exposed portions (see, e.g., mask openings in in fig. 2) to form openings (see, e.g., trench openings in fig. 21), and depositing a first dielectric layer (e.g., insulating films 305 + paragraph 60 “…305 may be formed of, for example, an insulating material having a dielectric constant of about 4.0 or greater…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the fabrication steps of Huang2 within the method process of Huang1 in view of Chen further in view of Tung, as the steps of Huang2 were well-known at the time of filing the invention to be a method of manufacturing trenches in substrates for material deposition, as taught by Huang2 (see paragraph 82 of Huang2).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM (Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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