Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to an Office action mailed on 03/19/2026 ("03-19-26 OA"), the Applicant (i) substantively amended claims 1, 3, 19 and 20, (ii), amended the independent claim 13 to include the limitations of the previously-indicated allowable claim 14 and then canceled claim 14, (iii) rewrote claim 17 in independent form to include the limitations of the previously-presented base claim 13 and the intervening claim 16 and (iv) added new claim 21 on 06-10-26 ("06-10-26 Response").
Applicant amended the title in the 06-10-26 Response.
Currently, claims 1-13 and 15-21 are pending.
Information Disclosure Statement
The Applicant submitted an information disclosure statement (IDS) on 05/05/2026 ("05-05-26 IDS") after the 03-19-26 OA. Since the Applicant has met the provisions of 37 CFR 1.97, the 05-05-26 IDS is in compliance and is being considered by the examiner.
Response to Arguments
Applicant's amendments to the title have overcome the objection to the Specification set forth on page 2 under line item number 1 of the 03-19-26 OA.
Applicant’s amendments to claims 1 and 19 have overcome the 35 U.S.C. 112(b) rejection of claims 1-12 and 19 set forth starting on page 3 under line item number 2 of the 03-19-26 OA.
Applicant's amendments to claim 1 have overcome the 35 U.S.C. 102(a)(2) rejection of claims 1, 2, 9, 11 and 12 as being anticipated by Kudymov set forth starting on page 4 under line item number 3 of the 03-19-26 OA.
Applicant's amendments to claims 1 and 20 have overcome the 35 U.S.C. 102(a)(2) rejection of claims 1, 2, 7-12 and 20 as being anticipated by Meng set forth starting on page 7 under line item number 4 of the 03-19-26 OA.
Applicant's amendments to claims 1 and 13 have overcome the 35 U.S.C. 102(a)(2) rejection of claims 1, 3-5, 13, 15, 16, 18 and 19 as being anticipated by Sang Lee set forth starting on page 11 under line item number 5 of the 03-19-26 OA.
Substantive-amendments to the independent claims 1 and 20 required further consideration and updated search. New grounds of rejection are provided below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 21 is indefinite, because it is unclear what is meant by “the at least one insulator film and the semiconductor substrate by the metal layer.”
A. Prior-art rejections based on Yang
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 10, 12 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US Pub. No. US 2022/0238694 A1 to Yang et al. (“Yang”) (cited in the 05-05-26 IDS).
Fig. 4 of Yang has been provided to support the rejection below:
PNG
media_image1.png
315
437
media_image1.png
Greyscale
Regarding independent claim 1, Yang teaches a structure (see Fig. 14; see also Fig. 4) comprising:
a semiconductor substrate 100 or 106, 104, 102, 100 (para [0031] - “substrate 100”; para [0047]);
at least one insulator film 108 (para [0042] - “passivation layer 108”) over the semiconductor substrate 100 or 106, 104, 102, 100, the at least one insulator film 108 including a recess 130 (para [0043] - “Please refer to FIG. 4. Subsequently, a conductive plate structure 140 is formed on the second passivation layer 132, which include a base portion 142 over the trenches 130 and a plurality of protruding portions 144 that extend downward (toward the channel layer 104) from a lower surface 142a of the base portion 142 and into the trenches 130 to fill the trenches 130.“; para [0049] - “When the conductive plate structure 140 is coupled to a voltage, it may also be used as a field plate in the high electron mobility transistor.”); and
a field plate 140, 132 comprising at least a metal layer 140 (para [0043] - “The material of the conductive plate structure 140 may include metal, for example, gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), palladium (Pd), platinum (Pt), a compound of the above materials, a composite layer of the above materials, or an alloy of the above materials, but is not limited thereto.”) and an insulator material 132 (para [0042] - “a second passivation layer 132”) both of which are extending into the recess 130 and over the at least one insulator film 108.
Regarding claim 2, Yang teaches the field plate 140, 132 that is a gate structure (para [0065] - “…the conductive plate structure 140 and the gate structure GE may be electrically connected to a same gate voltage.”) for a D-mode device (A limitation of “for a D-mode device” is a statement of intended use so it may not structurally distinguish the claimed structure over the structure taught by Yang.).
Regarding claim 3, Yang teaches the field plate 140, 132 that includes the insulator material 132 within the recess 130 and in contact with the semiconductor substrate 106, 104, 102, 100, and the metal layer 140 over the insulator material 132 within the recess 130.
Regarding claim 4, Yang teaches the insulator material 132 that forms a sidewall on vertical portions 144 (para [0043] - “protruding portion 144”) of the metal layer 140 of the field plate 140, 132.
Regarding claim 5, Yang teaches the insulator material 132 and the at least one insulator film 108 that comprises a same material (para [0042] - “According to an embodiment of the present invention, the first passivation layer 108 and the second passivation layer 132 may include a same dielectric material…”).
Regarding claim 6, Yang teaches the insulator material 132 and the at least one insulator film 108 that comprise AlyOx (para [0042] - “The material of the second passivation layer 132 may include…aluminum oxide (Al2O3)…”; para [0038] - “…the material of the first passivation layer 108 may include a dielectric material, such as aluminum nitride (AlN), aluminum oxide (Al2O3)…”).
Regarding claim 10, Yang teaches a gate structure GE (para [0046]; para [0048] - “The material of the metal gate layer 112 may include metal, for example, gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), palladium (Pd), platinum (Pt), a compound of the above materials, a composite layer of the above materials, or an alloy of the above materials, but is not limited thereto. According to an embodiment of the present invention, the metal gate layer 112, the source structure SE, and the drain structure DE may include a same metal.”) on the semiconductor substrate for a E-mode device (A limitation of “for a E-mode device” is a statement of intended use so it may not structurally distinguish the claimed structure over the structure taught by Yang.).
Regarding claim 12, Yang teaches the semiconductor substrate 106, 104, 102, 100 that comprises AlGaN/GaN material (para [0034] - “According to an embodiment of the present invention, the material of the buffer layer 102 may include aluminum nitride (AlN), the material of the channel layer 104 may include gallium nitride (GaN), and the material of the barrier layer 106 may include aluminum gallium nitride (AlGaN).”).
Regarding independent claim 20, Yang teaches a method comprising:
forming at least one insulator film 108 (para [0042] - “passivation layer 108”) over semiconductor substrate 106, 104, 102, 100 (para [0047]), the at least one insulator film 108 including a recess 130 exposing the semiconductor substrate 106, 104, 102, 100 (para [0043] - “Please refer to FIG. 4. Subsequently, a conductive plate structure 140 is formed on the second passivation layer 132, which include a base portion 142 over the trenches 130 and a plurality of protruding portions 144 that extend downward (toward the channel layer 104) from a lower surface 142a of the base portion 142 and into the trenches 130 to fill the trenches 130.“; para [0049] - “When the conductive plate structure 140 is coupled to a voltage, it may also be used as a field plate in the high electron mobility transistor.”); and
forming a field plate 140, 132 comprising at least a metal layer 140 (para [0043] - “The material of the conductive plate structure 140 may include metal, for example, gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), palladium (Pd), platinum (Pt), a compound of the above materials, a composite layer of the above materials, or an alloy of the above materials, but is not limited thereto.”) and an insulator material 132 (para [0042] - “a second passivation layer 132”) both extending into the recess 130 and over the at least one insulator film 108.
B. Prior-art rejections based on Hafez
Claim Rejections - 35 USC § 102
Claims 1-5, 7-10, 12 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US Pub. No. US 2020/0105884 A1 to Hafez et al. (“Hafez”).
Fig. 1 of Hafez has been annotated to support the rejection below:
[AltContent: textbox (RC)][AltContent: arrow][AltContent: arrow]
PNG
media_image2.png
688
491
media_image2.png
Greyscale
Regarding independent claim 1, Hafez teaches a structure (see Fig. 1) comprising:
a semiconductor substrate 104, 102, 101 (para [0039]);
at least one insulator film 116, 118, 120, 122, 124 (para [0057]) over the semiconductor substrate 104, 102, 101, the at least one insulator film 116, 118, 120, 122, 124 including a recess RC; and
a field plate 110, 108, 106, 107 or 108, 107 (para [0039] - “the gate 106 and a plate 110 on the plate 108”; para [0050] - “gate dielectric layer 107”) comprising at least a metal layer 110, 108, 106 (para [0052]) and an insulator material 107 both of which are extending into the recess RC and over the at least one insulator film 116, 118, 120, 122, 124.
Regarding claim 2, Hafez teaches the field plate 110, 108, 106, 107 that is a gate structure for a D-model device (A limitation of “for a D-mode device” is a statement of intended use so it may not structurally distinguish the claimed structure over the structure taught by Yang.).
Regarding claim 3, Hafez teaches the field plate 110, 108, 106, 107 that includes the insulator material 107 within the recess RC and in contact with the semiconductor substrate 104, 102, 101, and the metal layer 110, 108, 106 over the insulator material 107 within the recess RC.
Regarding claim 4, Hafez teaches the insulator material 107 that forms a sidewall on vertical portions of the metal layer 110, 108, 106 of the field plate 110, 108, 106, 107.
Regarding claim 5, Hafez teaches the insulator material 107 and the at least one insulator film 124 that comprise a same material (para [0053] - “In another embodiment, the gate dielectric layer 106A includes silicon and at least one of oxygen (e.g., silicon dioxide) or nitride (e.g., silicon nitride).”; para [0056] - “Dielectric material 124 includes any material that has sufficient dielectric strength to provide electrical isolation such as, but not limited to, silicon dioxide, silicon nitride...”).
Regarding claim 7, Hafez teaches the field plate 108, 107 that comprises an insulator film 124, 116 or 124, 122, 120, 118, 116 under and over a metal layer 108.
Regarding claim 8, Hafez teaches the at least one insulating film 124, 122, 120, 118, 116 that comprises two insulator films 116, 118, the recess RC extends into the two insulator films 116, 118 to expose the semiconductor substrate 104, 102, 101.
Regarding claim 9, Hafez teaches the at least one insulating film 124, 122, 120, 118, 116 that comprises two insulator films 116, 118, the recess RC extends into the two insulator films 116, 118 to expose a bottom of the two insulator films 116, 118.
Regarding claim 10, Hafez teaches a gate structure 106, 107 on the semiconductor substrate 104, 102, 101 for a E-mode device (A limitation of “for a E-mode device” is a statement of intended use so it may not structurally distinguish the claimed structure over the structure taught by Yang.).
Regarding claim 12, Hafez teaches the semiconductor substrate 104, 102, 101 that comprises AlGaN/GaN material (para [0058] - “One combination includes a polarization layer 104 of AlGaN and a channel layer 102 of GaN.”).
Regarding independent claim 20, Hafez teaches a method comprising:
forming at least one insulator film 116, 118, 120, 122, 124 (para [0057]) over semiconductor substrate 104, 102, 101, the at least one insulator film 116, 118, 120, 122, 124 including a recess RC exposing the semiconductor substrate 104, 102, 101; and
forming a field plate 110, 108, 106, 107 or 108, 107 (para [0039] - “the gate 106 and a plate 110 on the plate 108”; para [0050] - “gate dielectric layer 107”) comprising at least a metal layer 110, 108, 106 (para [0052]) and an insulator material 107 both of which are extending into the recess RC and over the at least one insulator film 116, 118, 120, 122, 124.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 11 is objected to, but would be allowable if (i) its base claim 1 is amended to include all of the limitations of claim 11 and the intervening claim 10 or (ii) claim 11 is rewritten in independent form to include all of the limitations of its base claim 1 and the intervening claim 10.
Independent claim 13 is allowed, because the independent claim 13 has been amended to include the limitations of the previously-indicated allowable claim 14 as stated on page 15 of the 03-19-26 OA.
Claims 15, 16, 18 and 19 are allowed, because they depend from the allowed independent claim 13.
Independent claim 17 is allowed, because the previously-indicated allowable claim 17 has been rewritten in independent form to include the limitations of the previously-presented base claim 13 and the intervening claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2008/0230786 A1 to Heikman et al.
Patent No. US 10,971,615 B2 to Tao et al.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8 A.M. to 7 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano, can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817
29 June 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Prosecution Insights