Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Currently, claims 1-20 are pending and examined below.
Information Disclosure Statement (IDS)
Seven IDSs submitted on 10/04/2023, 02/07/2024, 08/30/2024, 08/06/2025, 08/11/2025, 10/08/2025 and 12/10/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the seven IDSs are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: HIGH-ELECTRON MOBILITY TRANSISTOR HAVING FIELD PLATE EXTENDING INTO A RECESS OF INSULATOR FILM
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Section 2173.02.I. of the MPEP provides the following guidance on how pre-issuance claims under examination are construed differently than patented claims:
Patented claims are not given the broadest reasonable interpretation during court proceedings involving infringement and validity, and can be interpreted based on a fully developed prosecution record. While "absolute precision is unattainable" in patented claims, the definiteness requirement "mandates clarity." Nautilus, Inc. v. Biosig Instruments, Inc., 527 U.S. __, 134 S. Ct. 2120, 2129, 110 USPQ2d 1688, 1693 (2014). A court will not find a patented claim indefinite unless the claim interpreted in light of the specification and the prosecution history fails to "inform those skilled in the art about the scope of the invention with reasonable certainty." Id. at 1689.
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The Office does not interpret claims when examining patent applications in the same manner as the courts. In re Packard, 751 F.3d 1307, 1312, 110 USPQ2d 1785, 1788 (Fed. Cir. 2014); In re Morris, 127 F.3d 1048, 1054, 44 USPQ2d 1023, 1028 (Fed. Cir. 1997); In re Zletz, 893 F.2d 319, 321-22 (Fed. Cir. 1989). The Office construes claims by giving them their broadest reasonable interpretation during prosecution in an effort to establish a clear record of what the applicant intends to claim. Such claim construction during prosecution may effectively result in a lower threshold for ambiguity than a court's determination. Packard, 751 F.3d at 1323-24, 110 USPQ2d at 1796-97 (Plager, J., concurring). However, applicant has the ability to amend the claims during prosecution to ensure that the meaning of the language is clear and definite prior to issuance or provide a persuasive explanation (with evidence as necessary) that a person of ordinary skill in the art would not consider the claim language unclear. In re Buszard, 504 F.3d 1364, 1366 (Fed. Cir. 2007)( claims are given their broadest reasonable interpretation during prosecution "to facilitate sharpening and clarifying the claims at the application stage"); see also In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Cir. 1984); In re Zletz, 893 F.2d 319, 322, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989).
Here, the independent claim 1 is indefinite, because it is unclear what “the at least one recess” is referring to as there is no antecedent basis for it. For the purpose of advancing the examination of the instant application, "the at least one recess" has been assumed to refer to "a recess."
Claims 2-12 are indefinite, because they depend from the indefinite claim 1.
Claim 19 is indefinite, because it is unclear what is meant by “with a recess within into a top of the two insulator films.”
A. Prior-art rejections based on Kudymov
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 9, 11 and 12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pub. No. US 2025/0331297 A1 to Kudymov et al. ("Kudymov").
Fig. 1A of Kudymov has been provided to support the rejection below:
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Regarding independent claim 1, Kudymov teaches a structure (see Fig. 1A and Fig. 1B for example) comprising:
a semiconductor substrate 101, 102 and/or 103 (para [0038] - “The double-channel semiconductor device 100 includes a substrate 101, a GaN buffer layer 102, an AlGaN barrier layer 103, a two-dimensional electron gas (2DEG) 104, a HEMT source contact 105, a HEMT drain contact 106, implant isolation regions 107, a HEMT gate dielectric layer 108, a first passivation layer 109, a second passivation layer 110, a third passivation layer 111, a HEMT gate 112, a sacrificial dielectric region 113, a thin film transistor (TFT) gate 114, a TFT gate oxide 115, a TFT film 116, a TFT source contact 117, a TFT drain contact 118, a TFT source interconnect region 119, a first HEMT field plate 120, a second HEMT field plate 121, and a third HEMT field plate 122.”);
at least one insulator film 108, 109 and/or 110 (para [0044] - “a first passivation layer 109, a second passivation layer 110, a third passivation layer 111”; see Fig. 1A) over the semiconductor substrate 101, 102 and/or 103, the at least one insulator film 108, 109 and/or 110 including a recess (space occupied by the a HEMT gate 112 portion of the filed plates 122, 121, 120, 112. The HEMT gate 112 is monolithic or integral to the field plates 122, 121 and 120, so the HEMT gate 112 is a section or a part of the field plates 122, 121 and 120); and
a field plate 122, 121, 120, 112 (para [0042] - “a HEMT gate 112, a first HEMT field plate 120, a second HEMT field plate 121, and a third HEMT field plate 122.”) extending into the at least one recess and over the at least one insulating film 108, 109 and/or 110.
Regarding claim 2, Kudymov teaches the field plate 122, 121, 120, 112 that is a gate structure for a D-mode device (para [0039] - “HEMT 150 can be a depletion mode HEMT 150.”).
Regarding claim 9, Kudymov teaches the at least one insulator film 109, 110 or 108, 109, 110 that comprises two insulator films 109, 110, and the recess extends into a top 110 of the two insulator films 109, 110 to expose a bottom 109 of the two insulator films 109, 110.
Regarding claim 11, Kudymov teaches a gate structure 114 (para [0038] - “a thin film transistor (TFT) gate 114”) on the semiconductor substrate 101, 102 and/or 103 for an E-mode device (para [0041] - “TFT 140 can be an enhancement mode TFT 140.”).
Regarding claim 12, Kudymov teaches the semiconductor substrate 101, 102, 103 or 102, 103 that comprises AlGaN/GaN material (para [0038] - “a GaN buffer layer 102, an AlGaN barrier layer 103”).
B. Prior-art rejections based on Meng
Claim Rejections - 35 USC § 102
Claims 1, 2, 7-12 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pub. No. US 2025/0048668 A1 to Meng et al. ("Meng").
Fig. 1A of Meng has been provided to support the rejection below:
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Regarding independent claim 1, Meng teaches a structure (see Fig. 1A for example) comprising:
a semiconductor substrate 106, 104, 103 and/or 102 (para [0018] - “FIG. 1A is a vertical cross-sectional view of a semiconductor device 100A according to some embodiments of the present disclosure. FIG. 1B is an enlarged vertical cross-sectional view of a region A in FIG. 1A according to some embodiments of the present disclosure. The semiconductor device 100A includes a substrate 102, a buffer layer 103, nitride-based semiconductor layers 104 and 106, source/drain (S/D) electrodes 110 and 112, a doped III-V semiconductor layer 120, a gate electrode 130, a gate protection layer 140, passivation layers 150, 160, 170, 172 and 174, a field plate 162, a patterned conductive layer 180, and a plurality of contact vias 190 and 192.”);
at least one insulator film 150 and/or 160 (para [0042] - “Referring to FIG. 1A, the passivation layer 160 is disposed conformally over the passivation layer 150 and abuts against the sidewalls of the S/D electrodes 110 and 112.”) over the semiconductor substrate 106, 104, 103 and/or 102, the at least one insulator film 150 and/or 160 including a recess (space occupied by S/D electrode 110 portion of a field plate 162); and
a field plate 162, 110 (para [0043] - “The field plate 162 is connected to the S/D electrode 110. The field plate 162 can extend from the S/D electrode 110 or 112 to a position immediately on the gate protection layer 140.”) extending into the at least one recess and over the at least one insulator film 150 and/or 160.
Regarding claim 2, Meng teaches the field plate 162, 110 that is a gate structure for a D-mode device (para [0026] - “In some embodiments, the doped III-V semiconductor layer 120 can be omitted, such that the semiconductor device 100A is a depletion-mode device, which means the semiconductor device 100A in a normally-on state at zero gate-source voltage.”).
Regarding claim 7, Meng teaches the field plate 162, 110 that comprises an insulator film 170, 150 (para [0018] - “passivation layers 150, 160, 170, 172 and 174”) under and over a metal layer 162.
Regarding claim 8, Meng teaches the at least one insulator film 150, 160 that comprises two insulator films 150, 160, and the recess extends into the two insulator films to expose the semiconductor substrate 106 or 106, 104 or 160, 104, 103 or 160, 104, 103, 102.
Regarding claim 9, Meng teaches the at least one insulator film 150, 160 that comprises two insulator films 150, 160, the recess extends into a top of the two insulator films 150, 160 to expos a bottom of the two insulator films 150, 160.
Regarding claim 10, Meng teaches a gate structure 130 or 130, 120 (para [0025] - “In the exemplary illustration of FIG. 1B, the semiconductor device 100A is an enhancement mode device, which is in a normally-off state when the gate electrode 130 is at approximately zero bias. Specifically, the doped III-V semiconductor layer 120 may create at least one p-n junction with the nitride-based semiconductor layer 106 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding the gate electrode 130 has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked. “; para [0027] - “The exemplary materials of the doped III-V semiconductor layer 120 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN”) on the semiconductor substrate 102, 103, 104 and/or 106 for an E-mode device (para [0025] - “In the exemplary illustration of FIG. 1B, the semiconductor device 100A is an enhancement mode device, which is in a normally-off state when the gate electrode 130 is at approximately zero bias.”).
Regarding claim 11, Meng teaches the gate structure 130, 120 that comprises pGaN material 120.
Regarding claim 12, Meng teaches the semiconductor substrate 103, 104, 106 that comprises AlGaN/GaN material (para [0020] - “Accordingly, the exemplary materials of the buffer layer 103 can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.”; para [0021] - “The exemplary materials of the nitride-based semiconductor layer 104 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In.sub.xAl.sub.yGa.sub.(1-x-y)N where x+y≤1, Al.sub.yGa.sub.(1-y)N where y≤1. The exemplary materials of the nitride-based semiconductor layer 106 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In.sub.xAl.sub.yGa.sub.(1-x-y)N where x+y≤1, Al.sub.yGa.sub.(1-y)N where y≤1.”).
Regarding independent claim 20, Meng teaches a method comprising:
forming at least one insulator film 150 and/or 160 (para [0042] - “Referring to FIG. 1A, the passivation layer 160 is disposed conformally over the passivation layer 150 and abuts against the sidewalls of the S/D electrodes 110 and 112.”) over semiconductor substrate 106, 104, 103 and/or 102 (para [0018] - “FIG. 1A is a vertical cross-sectional view of a semiconductor device 100A according to some embodiments of the present disclosure. FIG. 1B is an enlarged vertical cross-sectional view of a region A in FIG. 1A according to some embodiments of the present disclosure. The semiconductor device 100A includes a substrate 102, a buffer layer 103, nitride-based semiconductor layers 104 and 106, source/drain (S/D) electrodes 110 and 112, a doped III-V semiconductor layer 120, a gate electrode 130, a gate protection layer 140, passivation layers 150, 160, 170, 172 and 174, a field plate 162, a patterned conductive layer 180, and a plurality of contact vias 190 and 192.”), the at least one insulator film 150 and/or 160 including a recess (space occupied by S/D electrode 110 portion of a field plate 162), the at least one insulator film 150 and/or 160 including a recess exposing the semiconductor substrate 106, 104, 103 and/or 102; and
forming a field plate 162, 110 (para [0043] - “The field plate 162 is connected to the S/D electrode 110. The field plate 162 can extend from the S/D electrode 110 or 112 to a position immediately on the gate protection layer 140.”) extending into the at least one recess and over the at least one insulator film 150 and/or 160.
C. Prior-art rejections based on Sang Lee
Claim Rejections - 35 USC § 102
Claims 1, 3-5, 13, 15, 16, 18 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pub. No. US 2024/0304678 A1 to Sang Lee ("Sang Lee").
Fig. 2H of Sang Lee has been annotated to support the rejection below:
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Regarding independent claim 1, Sang Lee teaches a structure (see Figure 2H) comprising:
a semiconductor substrate 15 (para [0064] - “epiwafer 15”);
at least one insulator film 26 (para [0067] - “surface dielectric layer 26) over the semiconductor substrate 15, the at least one insulator film 26 or 26, 42 including a recess R; and
a field plate 28, 22, 36 or 28, 22, 36, 42 (para [0070] - “A third dielectric layer 36 is formed over the second dielectric layer 28 and the field plate 22.”; para [0068] - “an insulation layer 42”).
Regarding claim 3, Sang Lee teaches the field plate 28, 22, 36 or 28, 22, 36, 42 that includes an insulator material 42 or 28 within the recess R and in (at least thermal or indirect) contact with the semiconductor substrate 15, and a metal layer 22 over the insulator material 42 or 28.
Regarding claim 4, Sang Lee teaches the insulator material 28 that forms a sidewall on vertical portions of the metal layer 22 of the field plate 28, 22, 36 or 28, 22, 36, 42.
Regarding claim 5, Sang Lee teaches the insulator material 28 (para [0069] - “The second dielectric layer 28 may comprise SiN.”) and the at least one insulator film 26 (para [0063] - “The surface dielectric layer 26 may comprise SiN”) that comprises a same material SiN.
Regarding independent claim 13, Sang Lee teaches a structure (see Figure 2H; para [0045] - “An integrated electronic device according to some embodiments includes a semiconductor die including a substrate and an epitaxial structure on the substrate, a depletion mode high electron mobility transistor (HEMT) device in a first region of the semiconductor die, and an enhancement mode HEMT device in a second region of the of the semiconductor die. The depletion mode HEMT includes first source and drain contacts, a first gate contact between the first source and drain contacts, and an insulation layer above the first gate contact, wherein the first gate contact directly contacts the epiwafer. The enhancement mode HEMT includes second source and drain contacts and a second gate contact between the second source and drain contacts, wherein the insulation layer is between the second gate contact and the epiwafer.”) comprising a high electron mobility transistor comprising a semiconductor substrate 15 (para [0064] - “epiwafer 15”), at least one insulator film 26 (para [0067] - “surface dielectric layer 26) over the semiconductor substrate 15 and a field plate 28, 22, 36 or 28, 22, 36, 42 (para [0070] - “A third dielectric layer 36 is formed over the second dielectric layer 28 and the field plate 22.”; para [0068] - “an insulation layer 42”) comprising an insulator material 42 and/or 28 extending into the at least one insulator film 26 and a metal plate 22 over the at least one insulator film 26 and the insulator material 42 and/or 28.
Regarding claim 15, Sang Lee teaches the field plate 28, 22, 36 or 28, 22, 36, 42 that is a gate structure for a D-mode device (para [0045]).
Regarding claim 16, Sang Lee teaches the insulator material 42 and/or 28 that extends within a recess R of the at least one insulator film 26 and which (at least thermally or indirectly) contacts the semiconductor substrate.
Regarding claim 18, Sang Lee teaches a structure (see Figure 2H) comprising a high electron mobility transistor comprising a semiconductor substrate 15 (para [0064] - “epiwafer 15”), at least one insulator film 26, 42 (para [0067] - “surface dielectric layer 26”; para [0068] - “an insulation layer 42”) over the semiconductor substrate 15 and a field plate 28, 22, 36 (para [0070] - “A third dielectric layer 36 is formed over the second dielectric layer 28 and the field plate 22.”) comprising an insulator material 28 extending into the at least one insulator film 26, 42 and a metal plate 22 over the at least one insulator film 26, 42 and the insulator material 28,
wherein the at least one insulator film 26, 42 comprises two insulator films 26, 42, and the recess R extends into the two insulator films 26, 42.
Regarding claim 19, Sang Lee teaches the at least one insulator film 26, 42 comprises two insulator films 26, 42, within a recess within into a top of the two insulator films 26, 42 and the insulator material 28 of the filed plate 28, 22, 36 extends to within the recess R and (at least thermally or indirectly) contacts a bottom insulator film 42 of the two insulator films 26, 42.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 is rejected, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 and the intervening claims 3 and 5 or the base claim 1 is amended to include all of the limitations of claim 6 and the intervening claims 3 and 5; and the pending 35 U.S.C. 112(b) rejection of the base claim 1 is successfully traverse.
Claim 14 is objected to, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 13 or the base claim 13 is amended to include all of the limitations of claim 14.
Claim 17 is objected to, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 13 and the intervening claims 16 or the base claim 13 is amended to include all of the limitations of claim 17 and the intervening claims 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2024/0429120 A1 to Schutte et al.
Pub. No. US 2024/0105450 A1 to Saripalli et al.
Pub. No. US 2024/0304702 A1 to Bothe et al.
Pub. No. US 2022/0293779 A1 to Du et al.
Pub. No. US 2022/0254912 A1 to Ramdani
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 07 March 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status