Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, claims 1-9, in the reply filed on 02/04/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chew (US-20220102254-A1) in view of Takada et al. (US-6590165-B1 referred as Takada).
Regarding claim 1. Chew discloses a method for manufacturing a component package substrate structure, the method comprising:
providing a first temporary bearing plate ([0127], figure 9, a first temporary bearing plate #117);
fitting a component on the first temporary bearing plate ([0136], figure 10, fitting a component #113 on the first temporary bearing plate #117);
applying a first dielectric layer on the first temporary bearing plate such that the component is embedded in the first dielectric layer ([0144, 0167], figure 20, applying a first dielectric layer #123/170 on the first temporary bearing plate #117 such that the component #113 is embedded in the first dielectric layer #123/170. Please note the material used for the first dielectric layer #123/170 is the Ajinomoto buildup film (ABF));
applying a second temporary bearing plate on the first dielectric layer ([0173], figure 23a, applying a second temporary bearing plate #118 is illustrated while inverting the device #150);
removing the first temporary bearing plate to expose a terminal face of the component and a first surface of the first dielectric layer ([0170, 0173], figure 23a, during the inverting of the device #150, the removal of the first temporary bearing plate #117 is also illustrated which results in exposing the terminal face of the component #113 through the hole #109 and also exposing the first surface of the first dielectric layer #123);
forming a connection pad connected to a terminal of the component on the first surface ([0177], figure 23b, a connection pad #125/127 is connected to a terminal of the component #113 on the first surface);
laminating a second dielectric layer on the first surface, and laminating a circuit board on the second dielectric layer, wherein the surface of the circuit board fitted to the second dielectric layer comprises a circuit layer ([0186], figure 23b, laminating a second dielectric layer #146 is seen on the first surface. Figure 26 illustrates laminating a circuit board #410 on the second dielectric layer #146. Since the circuit board #410 is a PCB, it is a fact to have a circuit layer within);
removing the second temporary bearing plate to expose a second surface of the first dielectric layer ([0187], figure 24, before applying the circuit board #410 in figure 26, the second temporary bearing plate #118 is removed to expose the second surface of the first dielectric layer #123/170);
Chew lacks the connection pad comprising an annular ring structure; and
opening a stepped hole on the second surface, wherein the stepped hole comprises a first via hole penetrating the first dielectric layer, an opening of an annular ring structure of the connection pad and a second via hole penetrating the second dielectric layer, wherein the first via hole, the opening and the second via hole together expose the circuit layer; and
electroplating the stepped hole to form a conductive column, wherein the conductive column renders the connection pad conductive with the circuit layer.
Takada discloses the connection pad comprising an annular ring structure ([col 31, lines 33-36], figure 28-29, the connection pad #404 comprises of an annular ring structure as described); and
opening a stepped hole on the second surface ([col 32 lines 30-38], figure 29, the stepped hole #453/454 is formed on the second surface), wherein the stepped hole comprises a first via hole penetrating the first dielectric layer, an opening of an annular ring structure of the connection pad and a second via hole penetrating the second dielectric layer, wherein the first via hole, the opening and the second via hole together expose the circuit layer ([col 32 lines 52-55], figure 29, the stepped hole #453/454 includes a first via hole #453 penetrating the first dielectric layer 416, an opening #440 of the annular ring structure being the connection pad #404, and a second via hole #454 penetrating the second dielectric layer #418. The first via hole #453 and the second via hole #454 together expose the circuit layer #461); and
electroplating the stepped hole to form a conductive column, wherein the conductive column renders the connection pad conductive with the circuit layer ([col 15 lines 18-28], figure 27, electroplating the stepped hole #453/454, as described, to form a conductive column #405 wherein the conductive column #405 renders the connection pad #404 with the circuit layer #461).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Chew to further include a stepped hole exposing the annular ring structure and the circuit layer thought the dielectric layers as taught by Takada in order to provide additional device versatility, ensuring strong connection within the circuitry, and to reduce signal loss.
Regarding claim 2. Chew as modified lacks forming a pad connected to the conductive column on the first dielectric layer.
Takada discloses forming a pad connected to the conductive column on the first dielectric layer ([col 31 lines 24-33], figure 27, forming a pad #462 is also seen connected to the conductive column #405 on the first dielectric layer #416).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Chew as modified to further include a pad connected to the conductive column as taught by Takada in order to ensure a strong connection within the circuitry, improve the devices integrity, and to reduce device failure.
Regarding claim 5. Chew as modified discloses wherein the circuit board is a multi-layer substrate having at least one circuit layer ([0195], figure 26, the circuit board #410 as a PCB is known to contain multiple layers with at least one circuit layer).
Regarding claim 6. Chew as modified discloses wherein the fitting of the component on the first temporary bearing plate comprises: forming an adhesive film on the first temporary bearing plate ([0129], figure 9-10, forming an adhesive film #121 on the first temporary bearing plate #117); and fitting the component at a predetermined position on the adhesive film such that a terminal face of the component is fitted to the adhesive film ([0129], figure 9-10, the component #113 is fitted to the adhesive film #121 as illustrated).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chew (US-20220102254-A1) and Takada et al. (US-6590165-B1 referred as Takada) in further view of Bhosale et al. (US-20190393085-A1).
Regarding claim 3. Chew as modified lacks removing a portion of the conductive column within the first via hole.
Bhosale et al. discloses removing a portion of the conductive column within the first via hole ([0035], figure 2a-2b, removing a portion of the conductive column #60 within the first via hole #54).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Chew as modified to further include removing a portion of the conductive column within the first via hole as taught by Bhosale et al. in order to the reduce total weight in the device, allow for additional room for other elements, and to reduce materials in manufacturing.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chew (US-20220102254-A1) and Takada et al. (US-6590165-B1 referred as Takada) in further view of Zou et al. (US-20200365320-A1).
Regarding claim 4. Chew as modified lacks wherein the forming of the connection pad connected to the terminal comprises: forming a metal seed layer on the first surface; forming a window pattern for manufacturing a connection pad on the metal seed layer; and electroplating to form the connection pad within the window pattern.
Zou et al. discloses wherein the forming of the connection pad connected to the terminal comprises: forming a metal seed layer on the first surface ([0040], figure 2, forming a metal seed layer #3 on the first surface); forming a window pattern for manufacturing a connection pad on the metal seed layer ([0042], figure 3, forming a window pattern #4 for manufacturing a connection pad on the metal seed layer #3); and electroplating to form the connection pad within the window pattern ([0046], figure 4, electroplating (as described) to form the connection pad #5 within the window pattern #3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Chew as modified to further include the process of forming the connection pad of using metal seeds, patterning window, and electroplating as taught by Zou et al. in order to ensure a reduce total materials used in manufacturing, reduce total weight in the device, and to have an enhanced placement accuracy.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chew (US-20220102254-A1) and Takada et al. (US-6590165-B1 referred as Takada) in further view of Yoshida et al. (US-20220328437-A1).
Regarding claim 7. Chew as modified lacks wherein the second temporary bearing plate comprises a support plate, a second metal layer on the support plate, and a first metal layer physically laminated on the second metal layer, wherein the first metal layer is laminated on the first dielectric layer.
Yoshida et al. discloses wherein the second temporary bearing plate comprises a support plate, a second metal layer on the support plate, and a first metal layer physically laminated on the second metal layer, wherein the first metal layer is laminated on the first dielectric layer ([0098-0099], figure 8, the second temporary bearing plate comprises of a support plate #43, a second metal layer #42 on a surface of the support plate #43, and a first metal layer #41 physically laminated on the second metal layers #42 surface. The first metal layer #41 is laminated on the first dielectric layer #32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Chew as modified to further include the second temporary bearing plate with a support layer, first metal layer and a second metal layer as taught by Yoshida et al. in order to enhance the devices integrity, increase the devices lifetime, and to distribute weight across the device.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chew (US-20220102254-A1), Takada et al. (US-6590165-B1 referred as Takada), and Yoshida et al. (US-20220328437-A1) as applied to claim 7, in further view of Biegelsen et al. (US-20220281009-A1)
Regarding claim 8 and 9. Chew as modified lacks
[claim 8] wherein the first metal layer and the second metal layer comprise a copper layer.
[claim 9] wherein the support plate is selected from the group consisting of a resin, aluminum, stainless steel, and copper.
Biegelsen et al. discloses
[claim 8] wherein the first metal layer and the second metal layer comprise a copper layer ([claim 7], the first metal layer and the second metal layer comprises of copper as described).
[claim 9] wherein the support plate is selected from the group consisting of a resin, aluminum, stainless steel, and copper ([0088], the support plate #502a contains copper as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Chew as modified to further include the copper materials for the first metal layer, second metal layer, and the support layer as taught by Biegelsen et al. in order to reduce manufacturing costs, maximize the connection integrity, and to enhance the electrical consistency.
Response to Amendment
Applicant's arguments filed 05/26/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art to Chew et al. in combination with Takada et al.. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
Regarding page 6 of the arguments, the applicant states that the preformed metal pillars #201 and the conductive structure #140/142/144 illustrated in the primary reference would not allow for a simple process flow that’s described in the present application of claim 1. The examiner responds that the surrounding unmapped elements would not affect the flow of the method claim since the components that construct claim 1 are still present in the primary reference. Applicant is invited to claim a specific sequence or detail in the method steps missing from the primary reference. The limitations of claim 1 are still met for the present application and described in the rejection above.
Regarding page 7 of the arguments, the applicant states that the primary reference does not contain the annular ring structure. It is disclosed in the rejection above that the primary reference does not contain the annular ring structure and it would require the combination of the secondary reference (Takada et al.) in order to meet the limitations of claim 1.
Furthermore, the applicant states that the primary reference contains a fan-out signal path of: the chip terminal, to the redistribution trace #125, to the solder pad #127, to the metal pillar #201, to the second conductive structure #140. Although additional elements are present in the primary reference, the elements #201 and #140 are not mapped in the rejection above, but the present application of claim 1 is still described within this primary reference of Chew et al... similarly to how a narrower invention could be present within a broader invention. It is suggested to further amend the limitations of claim 1 which are not in the scope of the primary reference.
Regarding page 8 of the arguments, the applicant states that stepped holes in the secondary reference would not combine with the preformed metal pillars in the primary reference since it would require fundamental reconstruction of the primary reference. The applicant argues that because the primary reference contains pre-formed metal frames which would disrupt the combination with the stepped holes seen in the secondary reference, a person of ordinary skill in the art would not be motivated to do a fundamental reconstruction of the primary reference. The examiner responds that it would be obvious in certain instances to include a stepped hole without the total reconstruction or removal of unmapped elements because they could be present in there together in order to provide additional device versatility, ensuring strong connection within the circuitry and to reduce signal loss.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272 - 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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