Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 03/10/2026 is acknowledged.
Claims 10-14 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/10/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "the embedded support frame" in lines 4 and 5. There is insufficient antecedent basis for this limitation in the claim. In the interest of compact prosecution, examiner will interpret "the embedded support frame" as “the embedded packaging frame.”
Allowable Subject Matter
Claims 1-8 allowed.
Claim 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1 and its dependent claims. The closest prior art (US20160341616A1, US20180278236A1, US20230302495A1) teaches a method for manufacturing a packaged cavity structure, the method comprising:
(a) preparing an embedded packaging frame; the embedded packaging frame comprising a first cavity and a first conductive post respectively penetrating an insulation layer along a height direction (Classen fig. 1h CMOS wafer 1 has recess 3B and via 15 penetrating insulating wafer 1 in a height direction);
(b) embedding a chipset at the bottom of the first cavity; the chipset comprising a first chip and a second chip provided in a stack, and the back faces of the first chip and the second chip being adhered to each other so that the terminal faces thereof being opposite to each other (Yin fig. 2 first chip 160 and second chip 300 formed in a stack with their back surfaces to one another);
(c) forming a packaging layer in a gap between the chipset and the first cavity; the packaging layer having a blind hole exposing a terminal of the second chip (Yin fig. 2 see ILD between second chip 300 and cavity 120);
(d) forming a first circuit layer and a second conductive post on an upper surface of the embedded packaging frame, wherein the first circuit layer is in conductive connection with a terminal of the second chip (Yin par. 36 teaches that “As shown in the figure [2], from bottom to top, it shows CMOS circuits of the first chip 160 (first layer) and two layers of semiconductor devices of the second chip 300” with plurality of vias 400);
(e) laminating a first dielectric layer on an upper surface of the first circuit layer; wherein an upper surface of the first dielectric layer is flush with an upper surface of the second conductive post Yin fig. 2 topmost ILD of second chip 300 is flush with upper surface with plurality of vias 400);
(f) forming a second circuit layer on an upper surface of the first dielectric layer, forming a third circuit layer on a lower surface of the embedded packaging frame, and forming a support post enclosure surrounding the first cavity on the third circuit layer(Yin par. 36 teaches that “As shown in the figure [2], from bottom to top, it shows CMOS circuits of the first chip 160 (first layer) and two layers of semiconductor devices of the second chip 300”);
(g) forming a through-hole penetrating the first dielectric layer and the insulation layer successively in a height direction, wherein the through-hole is surrounded by the above-mentioned support post enclosure (Classen fig. 3b pressure access through hole 3a).
However, the closest prior art does not teach in combination with the other claimed elements
forming a packaging layer along an outer side of the support post enclosure under the embedded packaging frame, and forming a second cavity between the packaging layer and the embedded packaging frame.
Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims.
Examiner notes that while there are embodiments within the prior art, see Classen fig. 3b, that teach a plurality of cavities formed between a frame and a packaging layer, examiner's search of the prior art did not find an embodiment nor any motivation to combine embodiments such that a packaging layer is formed along an outer side of the support post enclosure under the embedded packaging frame, and forming a second cavity between the packaging layer and the embedded packaging frame in addition with the other limitations of the independent claim.
Examiner additionally notes par. 26-28 of the specification which describes the difference in performance associated with the allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights