Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3- 5 and 7 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by WO 2007/126090 A1.
‘090 teaches:
for example, paragraphs [0123] - [0134] and [0182] - [0195] and (Fig. 7, 18-19), especially focusing on "Embodiment 13" of Fig. 18, includes a circuit board
including a first insulating layer (lower "insulating resin layer 10") and a first
circuit layer (conductor wiring 4a) (a portion other than "101" shown in Fig. 19
(a)), a core layer (insulating resin layer 8) covering the first circuit layer and
including a predetermined opening ("a space having a shape larger" "than the outer shape of the functional element 1" in paragraph 0130 and Fig. 7 (d)), a component
(functional element 1) embedded in the predetermined opening (see Figs. 7 (d) and
(e), etc.), a packaging layer (insulating resin layer 11) covering the core layer
(see Fig. 7 (d), etc.) and filling a gap between the core layer and the component
"a space having a shape larger" "than the outer shape of the
functional element 1" "is provided in advance" "in the insulating resin layer 8" in
paragraph 0130), and an outer circuit layer (conductor wiring 3a) located in the
packaging layer, wherein the outer circuit layer includes a first via pillar
(conductor via) penetrating the packaging layer.
An embedded component packaging substrate (circuit board 303) connected to the terminal (electrode terminal 5) of the component by 6) and connected to the first
circuit layer by a second via pillar (conductor via 7b) penetrating the core layer
and the packaging layer (see Fig. 17 (d), related Figs. 7 (f) - (h),)
In regards to claim 3-5,
‘090 teaches:
According to paragraph 0086 of Cited Document 1, the core layer (insulating resin layer 8) includes a glass fiber resin material ("glass cloth, glass filler," "organic resin epoxy containing, etc."). (2) In addition, according to paragraph 0085 of Cited Document 1, the packaging layer (insulating resin layer 11) contains an epoxy resin or a polyimide resin. Then, since paragraph 0086 does not mention the packaging layer (insulating resin layer 11), it is recognized that it does not contain glass fibers unlike the core layer (insulating resin layer 8) mentioned.
In regards to claim 7, ‘090 teaches:
The circuit board described in Cited Document 1 (for example, paragraph 0189 and Fig. 19 (a)) further includes a second circuit layer (conductor wiring 4b) located on the lower surface of the first insulating layer (lower "insulating resin layer 10"), and a third via pillar (conductor via 16) for conducting and connecting the first circuit layer (4a) and the second circuit layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-9, and 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over WO 2007/126090 A1
In regards to claim 8; ‘090
(for example, paragraphs [0123] - [0134], [0182] - [0195], and Figs. 7, 18, and 19) describes a method for manufacturing an embedded component packaging substrate (circuit board 303), in particular, focusing on "Embodiment 13" in Figs. 18 and 19. (a) Preparing a circuit board, wherein the circuit board includes a first insulating layer (lower "insulating resin layer 10") and a first circuit layer (conductor wiring 4a) located on the upper surface of the first insulating layer (paragraph 0189 and Fig. 19 (a)); (b') forming a medium layer (upper "insulating resin layer 10") on the first circuit layer, followed by forming an "adhesive layer 2" on the medium layer (paragraph 0191 and Fig. 19 (c), and "providing an adhesive layer 2 on the insulating resin layer 10" in the related paragraph 0126 and Fig. 7 (c)); (c') bonding the back surface of the component to the "adhesive layer 2" (paragraph 0192 and Fig. 19 (d), and "adhering the back surface of the functional element 1 to the insulating resin layer 10" "by the adhesive layer 2" in the related paragraph 0126 and Fig. 7 (c)); and (d') laminating a core layer (insulating resin layer 8) on the medium layer, wherein the core layer has an opening provided in advance to accommodate the component (paragraph 0130 and "the same shape as the outer shape of the functional element 1" in Fig. 7 (d)). Or "a space having a large shape") (see paragraph 0192 and Fig. 19 (d), and related paragraphs 0127, 0130 and Fig. 7 (d), etc.) (e) Laminating a packaging layer (insulating resin layer 11) on the core layer in order to package the component (see paragraph 0192 and Fig. 19 (d), and related paragraph 0127 and Fig. 7 (d), etc.); (f) Forming a first via pillar (conductor via 6) connected to a terminal of the component and a second via pillar (conductor via 7b) connected to the first circuit layer (paragraph 0192 and Fig. 19 (d), and related paragraphs 0131 to 0134 and Fig. 7) (f) - (h), (g)
A manufacturing method including forming an outer circuit layer (conductor wiring 3a) on the packaging layer, in which the outer circuit layer and the terminal of the component are conducted and connected by the first via pillar, and the outer circuit layer and the first circuit layer are conducted and connected by the second via pillar (paragraph 0192 and Fig. 19 (d), and related paragraph 0134 and Fig. 7 (h)) is described.
Paragraphs [0146] - [0148] and Fig. 11 of ‘090 teach in which a component (functional element 1) is temporarily fixed (bonded) by its own viscosity instead of the "adhesive layer 2", and the back surface of the component is bonded to the core adhesive medium layer (insulating resin layer 10) on the first circuit layer (conductor wiring 4).
Accordingly, it would have been obvious to one of an ordinary skill in the art before the effective filing date of the claimed invention would have easily applied the aforementioned technical matters to the "adhesive layer 2" and the medium layer (upper "insulating resin layer 10") described in paragraph 0191 and Fig. 19 (c) of ‘090, because it provides for a temporary bond prior to curing.
In regards to claim 9,
According to paragraph 0085 of ‘090 , the packaging layer (insulating resin layer 11) contains an epoxy resin or a polyimide resin.
(2) Regarding the "core layer" A. According to paragraph 0086 of ‘090, the core layer (insulating resin layer 8) includes a glass fiber resin material ("glass cloth, glass filler," "organic resin epoxy containing, etc.").
In regards to claim 11:
Paragraphs [0146] - [0148] and Fig. 11 of ‘090 teach in which a component (functional element 1) is temporarily fixed (bonded) by its own viscosity instead of the "adhesive layer 2", and the back surface of the component is bonded to the core adhesive medium layer (insulating resin layer 10) on the first circuit layer (conductor wiring 4).
Accordingly, it would have been obvious to one of an ordinary skill in the art before the effective filing date of the claimed invention would have easily applied the aforementioned technical matters to the "adhesive layer 2" and the medium layer (upper "insulating resin layer 10") described in paragraph 0191 and Fig. 19 (c) of ‘090, because it provides for a temporary bond prior to curing.
(2) Then, in relation to Claim 11, It is recognized that the "insulating resin layer 10" described in paragraphs [0107] - [0108] includes a "resin" that can be "cured" by heat at a "peak temperature of 160 degrees Celsius to 200 degrees Celsius". B. In addition, according to paragraph 0157, the "insulating resin layer 10" may include a photosensitive medium (photosensitive resin).
In regards 12, according to paragraph 0125, the "insulating resin layer 10" can be formed by crimping (vacuum laminator, vacuum press machine) or a coating or printing technique (roll coater, spin coat or curtain coat).
In regards to claim 13;
The circuit board described in ‘090 (for example, paragraph 0189 and Fig. 19 (a)) further includes a second circuit layer (conductor wiring 4b) located on the lower surface of the first insulating layer (lower "insulating resin layer 10"), and a third via pillar (conductor via 16) for conducting and connecting the first circuit layer (4a) and the second circuit layer.
Claim(s) 6 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over ‘090 as applied to claims 1 and 8 above, and further in view of WO2010/02423 and in further view of JP 2015-103753A.
In regards to claims 6 and 10,
WO2010/024233 (for example, paragraphs [0141] - [0145] and Figs. 11 and 18) and (for JP 2015-103753A example, paragraphs 0020,0050,0059 and Fig. 1)
WO2010/024233 describes a core layer (intermediate layer 404 / core substrate 2) includes a first opening ("opening" / opening 2a of "a portion where functional element 1 exists" described in paragraphs [0141] and [143] and Fig. 18 (d) used for embedding a component (functional element 1 / IC chip 3), and a second opening ("opening" of "a size larger than the outer shape of via hole 67" described in paragraphs [0141] and [143] and Fig. 18 (d)
Combined with the "through-shaped opening" provided at "a portion where a via hole for interlayer connection is formed" described in paragraphs [0050] and [0059] of JP 2015-103753A provided with a second via pillar (filled via 7 / "via hole conductor 8b" described in paragraphs [0050] and [059] of JP 2015-103753A.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because the second opening and column are conventionally done in the art to redistribute the current to the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/ Primary Examiner, Art Unit 2893