DETAILED ACTION
This correspondence is in response to the communications received 01/13/2026. Claims 21-34 have been added. Claims 1-7 and 14-20 have been canceled. Claims 8-13 and 21-34 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 8-13 and 21-34 in the reply filed on 01/13/2026 is acknowledged.
Claims 1-7 and 14-20 would be withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim, however claims 1-7 and 14-20 have been canceled. Election was made without traverse in the reply filed on 01/13/2026.
Specification
The disclosure is objected to because of the following informalities: Line 2 of ¶[0001] of the specification recites "a meal layer", it appears this should be written as "a metal layer". Appropriate correction is required.
Claim Objections
Claim 11 is objected to because of the following informalities: Claim 11 recites "the first metal layer and the second metal layer is pre-cleaned". For the purpose of examination this limitation will be interpretated as "the first metal layer and the second metal layer [[is]] . Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "the second metal" in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the second metal” will be interpretated as “the second metal layer”.
Claim 12 recites the limitation “the blocking layer is cured at 10 °C to 450 °C”. This limitation is unclear as to whether the curing process is performed at a single temperature between 10 °C and 450 °C, or if the process involves ramping the temperature from 10 °C to 450 °C. For the purposes of examination, the limitation will be interpretated as “the blocking layer is cured at a temperature between 10 °C [[to]] and 450 °C”.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
PNG
media_image1.png
365
529
media_image1.png
Greyscale
Regarding claim 8, a manufacturing method of a semiconductor structure (100), comprising:
forming a first dielectric layer (ILD1), a first metal layer (M1) and a second metal layer (M2), wherein the first metal layer and the second metal layer are embedded in the first dielectric layer and are separated from each other (see Fig. 3);
forming a blocking layer (BL) on the first metal layer and the second metal layer (see Fig. 4);
selectively depositing a first etching stop layer (ESL1) on the first dielectric layer by using the blocking layer as a mask (see Fig. 5);
removing the blocking layer and depositing a second etching stop layer (ESL2) on the first metal layer, the second metal layer and the first etching stop layer (see Fig. 6);
forming a second dielectric layer (ILD2) on the second etching stop layer (see Fig. 7);
etching the second dielectric layer to form a first concave (CV1) and a second concave (CV2, see Fig. 7); and
forming a first via (VA1) and a second via (VA2) in the first concave and the second concave respectively (see Fig. 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 10, 21-24, and 28-31 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 11,037,872 B2) in view of Yim et al. (US 9,245,809 B2) in view of McDaniel (US 6,258,709 B1).
PNG
media_image2.png
380
563
media_image2.png
Greyscale
PNG
media_image3.png
376
559
media_image3.png
Greyscale
PNG
media_image4.png
338
561
media_image4.png
Greyscale
PNG
media_image5.png
339
561
media_image5.png
Greyscale
PNG
media_image6.png
458
556
media_image6.png
Greyscale
PNG
media_image7.png
595
545
media_image7.png
Greyscale
Regarding claim 8, Figs. 1-9 of Han teach a manufacturing method of a semiconductor structure (“FIGS. 1 to 10 illustrate cross-sectional views of stages in a method of manufacturing a semiconductor device”, col. 2, lines 65-66), comprising:
forming a first dielectric layer (“a first insulating interlayer 110 may be formed on a substrate 100”, col. 3, lines 1-2, where “the first insulating interlayer 110 may include a low dielectric material (e.g., having a dielectric constant of 4.2 or lower). The low dielectric material may include, e.g., a silicon oxide doped with fluorine such as SiOF, a silicon oxide doped with carbon such as SiOCH”, col. 3, lines 18-27), a first metal layer and a second metal layer (“first wiring 155 may be formed in the first trench 115”, col. 3, lines 51-52, where “the first wiring 155 may include a first metal pattern 145”, col. 3, line 58, as depicted in Fig. 2, the left and right instances of 145 are a first and second metal layer respectively), wherein the first metal layer and the second metal layer are embedded in the first dielectric layer and are separated from each other (as seen in Fig. 2, the left and right instances of 145 are embedded in 110 and separated from each other);
forming a blocking layer (“a direct self assembly process may be performed to form a direct self assembly (DSA) layer 190 on the first wiring 155 and the first insulating interlayer 110. In an implementation, the DSA layer 190 may be formed by applying a composition including block copolymer (BCP)”, col. 4, lines 43-47, where “the first polymer unit may include, e.g., polymethylmethacrylate (PMMA), polydimethylsiloxane (PDMS), polyvinylpyrrolidone (PVP), polyethyleneoxide (PEO), polylactide (PLA) or polyimide (PI). In an implementation, the second polymer unit may include, e.g., polystyrene (PS). In an implementation…the BCP may include a first pattern 170 including PMMA and a second pattern 180 including PS”, col. 4, lines 57-57 and col. 5, lines 1-3) on the first metal layer and the second metal layer (as seen in Fig. 8, 170 is on the left and right instances of 145);
selectively depositing a first etching stop layer on the first dielectric layer by using the blocking layer as a mask (“Referring to FIG. 6, a first insulation pattern 210 may be formed on the exposed upper surface of the first insulating interlayer 110 to fill the first opening 200”, col. 5, lines 23-25, where as seen in Fig. 6, 210 is formed by 170 acting as a mask, Han does not disclose that 210 is an etch stop layer, however, Han does disclose “first insulation pattern 210 may include, e.g., a silicon oxide doped with fluorine (such as SiOF), a silicon oxide doped with carbon (such as SiOCH)”, col. 5, lines 36-38, therefore a secondary reference will be used below to teach that at least one of the materials taught by Han is an etch stop layer);
removing the blocking layer (“the first pattern 170 of the DSA layer 190 may be removed”, col. 5, lines 48-49) and depositing a second etching stop layer (“etch stop structure 230 may include a sequentially stacked first etch stop layer 232 and second etch stop layer 234”, col. 5, lines 60-62, here, 232 is interpretated to be the second etch stop layer, where “after forming an etch stop structure 230 on the exposed upper surface of the first wiring 155, a sidewall of the second opening 220, and an upper surface of the first insulation pattern 210, a second insulating interlayer 240 (filling a remaining portion of the second opening 220) may be formed on the etch stop structure 230”, col. 5, lines 53-58) on the first metal layer, the second metal layer and the first etching stop layer (as seen in Fig. 8, 232 is on the left and right instances of 145 and 210);
forming a second dielectric layer (240 is a second dielectric layer as “second insulating interlayer 240 may include a low dielectric material “, col. 6, lines 3-4) on the second etching stop layer (as seen in Fig. 8, 240 is on 232);
etching the second dielectric layer (“the via 280 and the second wiring 320 may be formed by forming a via hole extending through the lower portion of the second insulating interlayer 240”, Han does not specifically disclose etching, however, a secondary reference will be used to teach this limitation below) to form a first concave and a second concave (as seen in Fig. 9, the via holes filled by the left and right instances of 280 are a first and second concave respectively); and
forming a first via and a second via (the left and right instances of 280 are a first and second via respectively) in the first concave and the second concave respectively (as seen in Fig. 9, the left and right instances of 280 are in via holes filled by the left and right instances of 280).
Han fails to disclose “a first etching stop layer; and etching the second dielectric layer”.
However, in a similar field of endeavor, Fig. 2 of Yim teaches a first etching stop layer (“the etch stop is a low hydrogen containing oxide, such as SiOx or SiOF”, col. 4, 53-54).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first etching stop layer” as taught by Yim in the system of Han for the purpose of preventing over etching of the underlying material layers.
Han in combination with Yim fails to disclose “etching the second dielectric layer”.
However, in a similar field of endeavor, McDaniel teaches etching the second dielectric layer (“the dual damascene process uses two sequential photoresist and etch steps to form a first opening or via through an oxide layer to an underlying metal line”, col. 2, lines 41-43, thus the dual damascene process taught by Han includes an etch process to form the via holes).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “etching the second dielectric layer” as taught by McDaniel in the system of Han in combination with Yim for the purpose of forming openings in a dielectric layer to access the underlying conductive structures.
Regarding claim 10, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 8, Figs. 1-9 of Han further disclose wherein in the step of forming the blocking layer, the blocking layer is formed by vapor atomic layer deposition (ALD), monolayer doping (MLD), chemical vapor deposition (CVD), spin coating, dipping, or spray (“the DSA layer 190 may be formed by applying a composition including block copolymer (BCP) on the first wiring 155 and the first insulating interlayer 110 by a spin coating process”, col. 4, lines 46-49).
Regarding claim 21, Figs. 1-9 of Han teach a manufacturing method of a semiconductor structure (“FIGS. 1 to 10 illustrate cross-sectional views of stages in a method of manufacturing a semiconductor device”, col. 2, lines 65-66), comprising:
forming a first dielectric layer (“a first insulating interlayer 110 may be formed on a substrate 100”, col. 3, lines 1-2, where “the first insulating interlayer 110 may include a low dielectric material (e.g., having a dielectric constant of 4.2 or lower). The low dielectric material may include, e.g., a silicon oxide doped with fluorine such as SiOF, a silicon oxide doped with carbon such as SiOCH”, col. 3, lines 18-27), a first metal layer and a second metal layer (“first wiring 155 may be formed in the first trench 115”, col. 3, lines 51-52, where “the first wiring 155 may include a first metal pattern 145”, col. 3, line 58, as depicted in Fig. 2, the left and right instances of 145 are a first and second metal layer respectively), wherein the first metal layer and the second metal layer are embedded in the first dielectric layer and are separated from each other (as seen in Fig. 2, the left and right instances of 145 are embedded in 110 and separated from each other);
selectively depositing a first etching stop layer on the first dielectric layer (“Referring to FIG. 6, a first insulation pattern 210 may be formed on the exposed upper surface of the first insulating interlayer 110 to fill the first opening 200”, col. 5, lines 23-25, whereby 210 is selectively deposited on 110, but not 145 due to the presence of “a first pattern 170”, col. 5, lines 1-2, Han does not disclose that 210 is an etch stop layer, however, Han does disclose “first insulation pattern 210 may include, e.g., a silicon oxide doped with fluorine (such as SiOF), a silicon oxide doped with carbon (such as SiOCH)”, col. 5, lines 36-38, therefore a secondary reference will be used below to teach that at least one of the materials taught by Han is an etch stop layer) wherein the first etching stop layer exposes the first metal layer and the second metal layer (as seen in Fig. 7, 210 exposes the left and right instances of 145);
depositing a second etching stop layer (“etch stop structure 230 may include a sequentially stacked first etch stop layer 232 and second etch stop layer 234”, col. 5, lines 60-62, here, 232 is interpretated to be the second etch stop layer, where “after forming an etch stop structure 230 on the exposed upper surface of the first wiring 155, a sidewall of the second opening 220, and an upper surface of the first insulation pattern 210, a second insulating interlayer 240 (filling a remaining portion of the second opening 220) may be formed on the etch stop structure 230”, col. 5, lines 53-58) on the first metal layer, the second metal layer and the first etching stop layer (as seen in Fig. 8, 232 is on the left and right instances of 145 and 210);
forming a second dielectric layer (240 is a second dielectric layer as “second insulating interlayer 240 may include a low dielectric material “, col. 6, lines 3-4) on the second etching stop layer (as seen in Fig. 8, 240 is on 232);
etching the second dielectric layer (“the via 280 and the second wiring 320 may be formed by forming a via hole extending through the lower portion of the second insulating interlayer 240”, Han does not specifically disclose etching, however, a secondary reference will be used to teach this limitation below) to form a first concave and a second concave (as seen in Fig. 9, the via holes filled by the left and right instances of 280 are a first and second concave respectively); and
forming a first via and a second via (the left and right instances of 280 are a first and second via respectively) in the first concave and the second concave respectively (as seen in Fig. 9, the left and right instances of 280 are in via holes filled by the left and right instances of 280).
Han fails to disclose “a first etching stop layer; and etching the second dielectric layer”.
However, in a similar field of endeavor, Fig. 2 of Yim teaches a first etching stop layer (“the etch stop is a low hydrogen containing oxide, such as SiOx or SiOF”, col. 4, 53-54).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first etching stop layer” as taught by Yim in the system of Han for the purpose of preventing over etching of the underlying material layers.
Han in combination with Yim fails to disclose “etching the second dielectric layer”.
However, in a similar field of endeavor, McDaniel teaches etching the second dielectric layer (“the dual damascene process uses two sequential photoresist and etch steps to form a first opening or via through an oxide layer to an underlying metal line”, col. 2, lines 41-43, thus the dual damascene process taught by Han includes an etch process to form the via holes).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “etching the second dielectric layer” as taught by McDaniel in the system of Han in combination with Yim for the purpose of forming openings in a dielectric layer to access the underlying conductive structures.
Regarding claim 22, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 21, Figs. 1-9 of Han further disclose wherein after forming the first concave and the second concave, a width of the second etching stop layer disposed between the first concave and the second concave (“W2” denoted in Fig. 9 is a width of 232 between the via holes filled by the left and right instances of 280) is less than a width of the first etch stop layer disposed between the first concave and the second concave (“W1” denoted in Fig. 9 is a width of 210 between the via holes filled by the left and right instances of 280, and as seen in Fig. 9, W2 is less than W1).
Regarding claim 23, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 21, Figs. 1-9 of Han further disclose wherein in the step of selectively depositing the first etching stop layer and in the step of depositing the second etching stop layer, a material of the second etching stop layer is different from a material of the second etching stop layer (as discussed previously, 210 may be formed of SiOx or SiOF, and as “first etch stop layer 232 may include, e.g., aluminum oxide, aluminum nitride, or the like”, col, 5, lines 62-63, 210 and 232 are therefore of different materials).
Regarding claim 24, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 21, Figs. 1-9 of Han further disclose wherein in the step of selectively depositing the first etching stop layer, the first dielectric layer is fully covered by the first etching stop layer
(“the first insulation pattern 210 may be formed by forming a first insulation layer on the exposed upper surface of the first insulating interlayer 110 and an upper surface of the first pattern 170 of the DSA layer 190 to fill the first opening 200, and planarizing the first insulation layer until the upper surface of the first pattern 170 is exposed”, col. 5, lines 26-31, thus as 210 is formed on the upper surface of both 110 and 170, where 170 is on 110 as seen in Fig. 6, then 110 is fully covered by 210).
Regarding claim 28, Figs. 1-9 of Han teach a manufacturing method of a semiconductor structure (“FIGS. 1 to 10 illustrate cross-sectional views of stages in a method of manufacturing a semiconductor device”, col. 2, lines 65-66), comprising:
forming a first dielectric layer (“a first insulating interlayer 110 may be formed on a substrate 100”, col. 3, lines 1-2, where “the first insulating interlayer 110 may include a low dielectric material (e.g., having a dielectric constant of 4.2 or lower). The low dielectric material may include, e.g., a silicon oxide doped with fluorine such as SiOF, a silicon oxide doped with carbon such as SiOCH”, col. 3, lines 18-27), a first metal layer and a second metal layer (“first wiring 155 may be formed in the first trench 115”, col. 3, lines 51-52, where “the first wiring 155 may include a first metal pattern 145”, col. 3, line 58, as depicted in Fig. 2, the left and right instances of 145 are a first and second metal layer respectively), wherein the first metal layer and the second metal layer are embedded in the first dielectric layer and are separated from each other (as seen in Fig. 2, the left and right instances of 145 are embedded in 110 and separated from each other);
selectively depositing a first etching stop layer on the first dielectric layer (“Referring to FIG. 6, a first insulation pattern 210 may be formed on the exposed upper surface of the first insulating interlayer 110 to fill the first opening 200”, col. 5, lines 23-25, whereby 210 is selectively deposited on 110, but not 145 due to the presence of “a first pattern 170”, col. 5, lines 1-2, Han does not disclose that 210 is an etch stop layer, however, Han does disclose “first insulation pattern 210 may include, e.g., a silicon oxide doped with fluorine (such as SiOF), a silicon oxide doped with carbon (such as SiOCH)”, col. 5, lines 36-38, therefore a secondary reference will be used below to teach that at least one of the materials taught by Han is an etch stop layer) wherein the first etching stop layer exposes the first metal layer and the second metal layer (as seen in Fig. 7, 210 exposes the left and right instances of 145);
selectively depositing a second etching stop layer (“etch stop structure 230 may include a sequentially stacked first etch stop layer 232 and second etch stop layer 234”, col. 5, lines 60-62, here, 232 is interpretated to be the second etch stop layer, where “after forming an etch stop structure 230 on the exposed upper surface of the first wiring 155, a sidewall of the second opening 220, and an upper surface of the first insulation pattern 210, a second insulating interlayer 240 (filling a remaining portion of the second opening 220) may be formed on the etch stop structure 230”, col. 5, lines 53-58, and as seen in Fig. 9, a portion of 232 is later etched, thus making 232 selectively deposited as understood by the manner in the Applicant has presented the claim limitation) on the first etching stop layer (as seen in Fig. 8, 232 is on 210);
forming a second dielectric layer (240 is a second dielectric layer as “second insulating interlayer 240 may include a low dielectric material “, col. 6, lines 3-4) on the second etching stop layer (as seen in Fig. 8, 240 is on 232);
etching the second dielectric layer (“the via 280 and the second wiring 320 may be formed by forming a via hole extending through the lower portion of the second insulating interlayer 240”, Han does not specifically disclose etching, however, a secondary reference will be used to teach this limitation below) to form a first concave and a second concave (as seen in Fig. 9, the via holes filled by the left and right instances of 280 are a first and second concave respectively); and
forming a first via and a second via (the left and right instances of 280 are a first and second via respectively) in the first concave and the second concave respectively (as seen in Fig. 9, the left and right instances of 280 are in via holes filled by the left and right instances of 280).
Han fails to disclose “a first etching stop layer; and etching the second dielectric layer”.
However, in a similar field of endeavor, Fig. 2 of Yim teaches a first etching stop layer (“the etch stop is a low hydrogen containing oxide, such as SiOx or SiOF”, col. 4, 53-54).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first etching stop layer” as taught by Yim in the system of Han for the purpose of preventing over etching of the underlying material layers.
Han in combination with Yim fails to disclose “etching the second dielectric layer”.
However, in a similar field of endeavor, McDaniel teaches etching the second dielectric layer (“the dual damascene process uses two sequential photoresist and etch steps to form a first opening or via through an oxide layer to an underlying metal line”, col. 2, lines 41-43, thus the dual damascene process taught by Han includes an etch process to form the via holes).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “etching the second dielectric layer” as taught by McDaniel in the system of Han in combination with Yim for the purpose of forming openings in a dielectric layer to access the underlying conductive structures.
Regarding claim 29, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 28, Figs. 1-9 of Han further disclose wherein after forming the first concave and the second concave, a width of the second etching stop layer disposed between the first concave and the second concave (“W2” denoted in Fig. 9 is a width of 232 between the via holes filled by the left and right instances of 280) is less than a width of the first etch stop layer disposed between the first concave and the second concave (“W1” denoted in Fig. 9 is a width of 210 between the via holes filled by the left and right instances of 280, and as seen in Fig. 9, W2 is less than W1).
Regarding claim 30, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 28, Figs. 1-9 of Han further disclose wherein in the step of selectively depositing the first etching stop layer and in the step of selectively depositing the second etching stop layer, a material of the second etching stop layer is different from a material of the second etching stop layer (as discussed previously, 210 may be formed of SiOx or SiOF, and as “first etch stop layer 232 may include, e.g., aluminum oxide, aluminum nitride, or the like”, col, 5, lines 62-63, 210 and 232 are therefore of different materials).
Regarding claim 31, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 28, Figs. 1-9 of Han further disclose wherein in the step of selectively depositing the first etching stop layer, the first dielectric layer is fully covered by the first etching stop layer
(“the first insulation pattern 210 may be formed by forming a first insulation layer on the exposed upper surface of the first insulating interlayer 110 and an upper surface of the first pattern 170 of the DSA layer 190 to fill the first opening 200, and planarizing the first insulation layer until the upper surface of the first pattern 170 is exposed”, col. 5, lines 26-31, thus as 210 is formed on the upper surface of both 110 and 170, where 170 is on 110 as seen in Fig. 6, then 110 is fully covered by 210).
Claims 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 11,037,872 B2) in view of Yim et al. (US 9,245,809 B2) in view of McDaniel (US 6,258,709 B1) in view of Bristol et al. (US 10,109,583 B2) .
Regarding claim 9, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 8, Figs. 1-9 of Han further disclose wherein a material of the blocking layer is a polymer inhibitor composed of C, O, N, Cl, or F, a self-assembly monolayer composed of phosphonic acid material, thiol material or silane- based material, benzotriazole (BTA), thiol (-SH) material, or phosphonic acid (-POOH) material (as discussed previously, 190 is a direct self assembly layer, Han discloses a number of possible polymer units such as PMMA and PS, however Han does not disclose 190 being composed of “phosphonic acid material, thiol material or silane- based material”, instead a secondary reference will be used to teach this limitation below).
Han in combination with Yim and McDaniel fails to disclose “wherein a material of the blocking layer is a polymer inhibitor composed of C, O, N, Cl, or F, a self-assembly monolayer composed of phosphonic acid material, thiol material or silane- based material, benzotriazole (BTA), thiol (-SH) material, or phosphonic acid (-POOH) material.”
However, in a similar field of endeavor, Figs. 2A-2P of Bristol teach wherein a material of the blocking layer is a polymer inhibitor composed of C, O, N, Cl, or F, a self-assembly monolayer composed of phosphonic acid material, thiol material or silane- based material, benzotriazole (BTA), thiol (-SH) material, or phosphonic acid (-POOH) material (“Embodiments that include a PS brush formed over the surface of the selective cap 239 may further improve the segregation of the PS portion 248 and the PMMA portion 249. For example, thiol chemistry on the tail end of the PS brush may attract the PS portion 248 to the selective cap 239. While thiol chemistry is used as an exemplary embodiment, other tail end chemistries may also selectively attract the first polymer region 248 (e.g., phosphonic acid selectively attracts the PS portions 248)”, col. 10, lines 42-50, thus the PS polymer units of 190 of Han may additionally compose a thiol or a phosphonic acid tail chemistry).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein a material of the blocking layer is a polymer inhibitor composed of C, O, N, Cl, or F, a self-assembly monolayer composed of phosphonic acid material, thiol material or silane- based material, benzotriazole (BTA), thiol (-SH) material, or phosphonic acid (-POOH) material” as taught by Bristol in the system of Han in combination with Yim and McDaniel for the purpose of improving the reaction process during the formation of the self-assembly monolayer.
Regarding claim 13, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 8.
Han in combination with Yim and McDaniel fails to disclose “wherein in the step of removing the blocking layer, the blocking layer is removed by thermal annealing, plasma treatment or wet approach.”
However, in a similar field of endeavor, Figs. 2A-2P of Bristol teach wherein in the step of removing the blocking layer, the blocking layer is removed by thermal annealing, plasma treatment or wet approach (“the second polymer region 249 may be removed with a wet or dry etch chemistry”, col. 10, lines 49-51, where 249 is “PMMA portion 249”, col. 10, line 63, equivalent to 170 of Han).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein in the step of removing the blocking layer, the blocking layer is removed by thermal annealing, plasma treatment or wet approach” as taught by Bristol in the system of Han in combination with Yim and McDaniel for the purpose of removing the blocking layer to enable deposition of above layers.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 11,037,872 B2) in view of Yim et al. (US 9,245,809 B2) in view of McDaniel (US 6,258,709 B1) in view of Ke et al. (US 10,770,292 B2).
Regarding claim 11, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 8.
Han in combination with Yim and McDaniel fails to disclose “wherein in the step forming the blocking layer, the first metal layer and the second metal is pre-cleaned”.
However, in a similar field of endeavor, Figs. 4A-4C of Ke teach wherein in the step forming the blocking layer, the first metal layer and the second metal is pre-cleaned (“Flaw or defects in the SAMs can cause failed circuits and device yield loss. In some embodiments, the wafer (or substrate) is pretreated to clean contaminants and heat the wafer to a temperature higher than a subsequent SAM step. The pre-clean process of some embodiments finishes with a surface treatment to replenish the hydroxyl terminations on the surface.”, col. 5, lines 54-60).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein in the step forming the blocking layer, the first metal layer and the second metal is pre-cleaned” as taught by Ke in the system of Han in combination with Yim and McDaniel to improve self-assembly monolayer film quality and thereby device yield.
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 11,037,872 B2) in view of Yim et al. (US 9,245,809 B2) in view of McDaniel (US 6,258,709 B1) in view of Colburn et al. (US 8,358,011 B1).
Regarding claim 12, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 8.
Han in combination with Yim and McDaniel fail to disclose “wherein in the step forming the blocking layer, the blocking layer is cured at 10 °C to 450 °C.”
However, in a similar field of endeavor, Figs. 2a-2h of Colburn teach wherein in the step forming the blocking layer, the blocking layer is cured at 10 °C to 450 °C (“a two layer structure that consists of a random brush polymer 2100 and diblock copolymer film 2110 is coated and subjected to a thermal cure”, col. 5, lines 5-7, where “Typical thermal cure cycle entails baking at between about 100°C and about 300 °C, preferably about 200 °C for 30 to 60 minute. In the exemplary case of a polymethylmethacrylate-polystyrene (PMMA-PS) system, the resulting structure consists circular regions of PMMA roughly 12 to 25 nm in diameter located at 30-40 nm centers distributed uniformly in a matrix of PS”, col. 5, lines 14-20, thus 190 of Han which can comprise PMMA and PS can be thermally cured “at between about 100°C and about 300 °C”).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein in the step forming the blocking layer, the blocking layer is cured at 10 °C to 450 °C” as taught by Colburn in the system of Han in combination with Yim and McDaniel for the purpose of avoiding the use of UV based curing techniques.
Claims 25-27 and 32-34 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 11,037,872 B2) in view of Yim et al. (US 9,245,809 B2) in view of McDaniel (US 6,258,709 B1) in view of Yang et al. (US 11244898 B2) .
Regarding claim 25, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 21.
Han in combination with Yim and McDaniel fails to disclose “wherein in the step of selectively depositing the first etching stop layer, a thickness of the first etching stop layer is 1 nm to 100 nm.”
PNG
media_image8.png
361
535
media_image8.png
Greyscale
However, in a similar field of endeavor, Figs. 1B and 3-12 of Yang teach wherein in the step of selectively depositing the first etching stop layer, a thickness of the first etching stop layer is 1 nm to 100 nm (“dielectric etch stop material 602 includes silicon oxide, silicon nitride, and/or a dielectric oxide of aluminum (AlXOY) and has a thickness between about 10 Å and about 50 Å”, col. 11, lines 25-28, thus 210 of Han which can be formed of silicon oxide as previously discussed, can have a thickness between 1 nm and 5 nm).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein in the step of selectively depositing the first etching stop layer, a thickness of the first etching stop layer is 1 nm to 100 nm” as taught by Yang in the system of Han in combination with Yim and McDaniel for the purpose of minimizing layer thickness to shrink device size.
Regarding claim 26, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 21.
Han in combination with Yim and McDaniel fails to disclose “wherein in the step of depositing the second etching stop layer, a thickness of the second etching stop layer is 1 nm to 100 nm.”
However, in a similar field of endeavor, Figs. 1B and 3-12 of Yang teach wherein in the step of depositing the second etching stop layer, a thickness of the second etching stop layer is 1 nm to 100 nm (“dielectric etch stop material 602 includes silicon oxide, silicon nitride, and/or a dielectric oxide of aluminum (AlXOY) and has a thickness between about 10 Å and about 50 Å”, col. 11, lines 25-28, thus as “first etch stop layer 232 may include, e.g., aluminum oxide, aluminum nitride, or the like”, col, 5, lines 62-63, 232 can therefore have a thickness between 1 nm and 5 nm).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein in the step of depositing the second etching stop layer, a thickness of the second etching stop layer is 1 nm to 100 nm” as taught by Yang in the system of Han in combination with Yim and McDaniel for the purpose of minimizing layer thickness to shrink device size.
Regarding claim 27, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 21.
Han in combination with Yim and McDaniel fails to disclose “wherein after depositing the second etching stop layer, a thickness of a combination of the first etching stop layer and the second etching stop layer is 1 nm to 200 nm.”
However, in a similar field of endeavor, Figs. 1B and 3-12 of Yang teach wherein after depositing the second etching stop layer, a thickness of a combination of the first etching stop layer and the second etching stop layer is 1 nm to 200 nm (“dielectric etch stop material 602 includes silicon oxide, silicon nitride, and/or a dielectric oxide of aluminum (AlXOY) and has a thickness between about 10 Å and about 50 Å”, col. 11, lines 25-28, thus as previously discussed, 210 of Han can be formed of silicon oxide and “first etch stop layer 232 may include, e.g., aluminum oxide, aluminum nitride, or the like”, col, 5, lines 62-63, 210 and 232 can therefore have a combined thickness between 2 nm and 10 nm).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein after depositing the second etching stop layer, a thickness of a combination of the first etching stop layer and the second etching stop layer is 1 nm to 200 nm” as taught by Yang in the system of Han in combination with Yim and McDaniel for the purpose of minimizing layer thickness to shrink device size.
Regarding claim 32, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 28.
Han in combination with Yim and McDaniel fails to disclose “wherein in the step of selectively depositing the first etching stop layer, a thickness of the first etching stop layer is 1 nm to 100 nm.”
However, in a similar field of endeavor, Figs. 1B and 3-12 of Yang teach wherein in the step of selectively depositing the first etching stop layer, a thickness of the first etching stop layer is 1 nm to 100 nm (“dielectric etch stop material 602 includes silicon oxide, silicon nitride, and/or a dielectric oxide of aluminum (AlXOY) and has a thickness between about 10 Å and about 50 Å”, col. 11, lines 25-28, thus 210 of Han which can be formed of silicon oxide as previously discussed, can have a thickness between 1 nm and 5 nm).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein in the step of selectively depositing the first etching stop layer, a thickness of the first etching stop layer is 1 nm to 100 nm” as taught by Yang in the system of Han in combination with Yim and McDaniel for the purpose of minimizing layer thickness to shrink device size.
Regarding claim 33, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 28.
Han in combination with Yim and McDaniel fails to disclose “wherein in the step of selectively depositing the second etching stop layer, a thickness of the second etching stop layer is 1 nm to 100 nm.”
However, in a similar field of endeavor, Figs. 1B and 3-12 of Yang teach wherein in the step of selectively depositing the second etching stop layer, a thickness of the second etching stop layer is 1 nm to 100 nm (“dielectric etch stop material 602 includes silicon oxide, silicon nitride, and/or a dielectric oxide of aluminum (AlXOY) and has a thickness between about 10 Å and about 50 Å”, col. 11, lines 25-28, thus as “first etch stop layer 232 may include, e.g., aluminum oxide, aluminum nitride, or the like”, col, 5, lines 62-63, 232 can therefore have a thickness between 1 nm and 5 nm).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein in the step of selectively depositing the second etching stop layer, a thickness of the second etching stop layer is 1 nm to 100 nm” as taught by Yang in the system of Han in combination with Yim and McDaniel for the purpose of minimizing layer thickness to shrink device size.
Regarding claim 34, Figs. 1-9 of Han in combination with Fig. 2 of Yim and McDaniel disclose the manufacturing method of the semiconductor structure according to claim 28.
Han in combination with Yim and McDaniel fails to disclose “wherein after depositing the second etching stop layer, a thickness of a combination of the first etching stop layer and the second etching stop layer is 1 nm to 200 nm.”
However, in a similar field of endeavor, Figs. 1B and 3-12 of Yang teach wherein after depositing the second etching stop layer, a thickness of a combination of the first etching stop layer and the second etching stop layer is 1 nm to 200 nm (“dielectric etch stop material 602 includes silicon oxide, silicon nitride, and/or a dielectric oxide of aluminum (AlXOY) and has a thickness between about 10 Å and about 50 Å”, col. 11, lines 25-28, thus as previously discussed, 210 of Han can be formed of silicon oxide and “first etch stop layer 232 may include, e.g., aluminum oxide, aluminum nitride, or the like”, col, 5, lines 62-63, 210 and 232 can therefore have a combined thickness between 2 nm and 10 nm).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein after depositing the second etching stop layer, a thickness of a combination of the first etching stop layer and the second etching stop layer is 1 nm to 200 nm” as taught by Yang in the system of Han in combination with Yim and McDaniel for the purpose of minimizing layer thickness to shrink device size.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893