DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 in the reply filed on 02/12/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites “wherein a top surface of the second bottom conductive material and a bottom surface of the second top conductive material have substantially a same width.”
The term "substantially" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Substantially” is defined as "being largely but not wholly that which is specified” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how many .
The term “substantially” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target (in this case, the target is width, and possible values length), and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear.
Therefore, claim 8 is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention, and claims 9-10 are rejected for at least their dependencies.
For the purposes of Examination, any length will be considered “substantially” the same.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 5-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20220216213 A1, hereinafter Huang).
With regards to claim 1, Huang discloses a memory device, (FIG. 2) comprising:
a substrate; (substrate 112)
a first word line structure (at least word line WL1) in the substrate, comprising:
a first bottom conductive material; (lower portion 144) and
a first top conductive material (upper portion 146) over the first bottom conductive material, wherein a top surface of the first bottom conductive material is wider than a bottom surface of the first top conductive material; (See FIG. 2, showing the top of 144 being wider than the bottom of 144)
a first dielectric layer (dielectric (unlabeled) directly between layers 210 and 220) over the first word line structure; (see Fig. 2)
a dielectric liner (dielectric layer 140/150) lining the first word line structure; and
a bit line structure (bit line comprising bit line contact 210) over the substrate. (See FIG. 2)
With regards to claim 5, Huang discloses the memory device of claim 1, further comprising a capacitor (capacitor 220) electrically coupled with a doped region (doped region 114) of the substrate. (see FIG. 2)
With regards to claim 6, Huang discloses the memory device of claim 1, wherein a portion of the top surface of the first bottom conductive material is free of coverage by the first top conductive material. (See FIG. 2, where the layer 144 is free of coverage on a top of the layer)
With regards to claim 7, Huang discloses the memory device of claim 1, wherein the first dielectric layer is in contact with a top surface of the first top conductive material and a sidewall of the first top conductive material. (see FIG. 2, where the layer 150 is in contact with a top of the layer 146, where the top is also a sidewall)
With regards to claim 8, Huang discloses the memory device of claim 1, further comprising:
an isolation structure (ILD 120) in the substrate; and
a second word line structure (at least WL 3) in the isolation structure, comprising:
a second bottom conductive material; (layer 132) and
a second top conductive material (layer 134/136) over the second bottom conductive material, wherein a top surface of the second bottom conductive material and a bottom surface of the second top conductive material have substantially a same width. (See FIG. 2, wherein at least one width is substantially the same between layers 132 and 144)
With regards to claim 9, Huang discloses the memory device of claim 8, wherein the second top conductive material is wider than the first top conductive material. (see FIG. 2, where the layer 136/134 is wider than the layer 146)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 4 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20220216213 A1, hereinafter Huang) in view of KIM (US 20200395455 A1)
With regards to claim 2, Huang discloses the memory device of claim 1.
Huang does not explicitly teach wherein the first dielectric layer is in contact with the first bottom conductive material.
Kim teaches wherein the first dielectric layer (TiN barrier layer 110) is in contact with the first bottom conductive material. (gate electrode 109, See FIG.9 )
It would have been obvious to one of ordinary skill in the art to modify the device of Huang to have the dielectric of Kim, as both references are in the same field of endeavor.
One of ordinary skill would appreciate that the second barrier layer may serve to prevent inter-diffusion or interaction between the first gate electrode and a subsequent second gate electrode. (See Kim Paragraph [0084])
With regards to claim 4, Huang discloses the memory device of claim 1.
Huang does not explicitly teach wherein a bottom surface of the first dielectric layer is lower than a top surface of the first top conductive material.
Kim teaches wherein a bottom surface of the first dielectric layer (TiN barrier layer 110) is lower than a top surface of the first top conductive material. (dielectric 105, See FIG.9 )
It would have been obvious to one of ordinary skill in the art to modify the device of Huang to have the dielectric of Kim, as both references are in the same field of endeavor.
One of ordinary skill would appreciate that the second barrier layer may serve to prevent inter-diffusion or interaction between the first gate electrode and a subsequent second gate electrode. (See Kim Paragraph [0084])
With regards to claim 10, Huang discloses the memory device of claim 8, further comprising a second dielectric layer (dielectric directly over 150) over the second top conductive material, while the second dielectric layer is spaced apart from the second bottom conductive material. (See FIG 2)
Huang does not explicitly teach wherein the first dielectric layer is in contact with the first bottom conductive material.
Kim teaches wherein the first dielectric layer (TiN barrier layer 110) is in contact with the first bottom conductive material. (gate electrode 109, See FIG.9 )
It would have been obvious to one of ordinary skill in the art to modify the device of Huang to have the dielectric of Kim, as both references are in the same field of endeavor.
One of ordinary skill would appreciate that the second barrier layer may serve to prevent inter-diffusion or interaction between the first gate electrode and a subsequent second gate electrode. (See Kim Paragraph [0084])
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the cited references teach or suggest, either alone or in combination, at least “wherein the first top conductive material has a first sidewall and a second sidewall opposite to the first sidewall, the first sidewall is in contact with the first dielectric layer and the second sidewall is in contact with the dielectric liner.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
HSIEH et al. (US 20190198676 A1) – buried word line structure..
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812