DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 8-10 and 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group (II), Species (B) and Device Embodiment (C1, C3 and C4), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 26 December 2025.
Applicant’s election without traverse of Group I, Species A, Device Embodiment C2 in the reply filed on 26 December 2025 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10 October 2023 and 6 December 2024 have been considered by the examiner and made of record in the application file.
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract of the disclosure is objected to because of undue length. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 11, 14 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by June Hwan Kim et al. (US 2021/0104558 A1; hereinafter “Kim”).
Regarding Claim 1, Kim teaches a complementary semiconductor device comprising:
a substrate (110, Fig. 22, para [0101] describes a first substrate 110);
a first thin film transistor of a first conductivity type (DT_11, Fig. 22, para [0225] describes a driving transistor DT_11 wherein para [0083] describes wherein the driving transistors may be formed as N-type MOS transistors), the first thin film transistor being supported by the substrate (DT_11, Fig. 22 depicts the first thin film transistor DT_11 being supported by the substrate 110); and
a second thin film transistor of a second conductivity type that is different from the first conductivity type (ST2_11, Fig. 22, para [0225] describes a switching transistor ST2_11 wherein para [0083] describes wherein the switching transistors may be formed as P-type MOS transistors), the second thin film transistor being supported by the substrate (ST2_11, Fig. 22 depicts the second thin film transistor ST2_11 being supported by the substrate 110),
wherein the first thin film transistor (DT_11) includes
a first semiconductor layer made of an oxide semiconductor material of the first conductivity type (350, Fig. 22, para [0102] describes a first active layer 350 wherein para [0129] describes the first active layer 350 may be comprised of an oxide semiconductor), the first semiconductor layer including a first channel region (350C, Fig. 22, para [0130] describes a first channel region 350c) and a first source region (350a, Fig. 22, para [0130] describes a first conductive region 350a coupled to a source electrode 330) and a first drain region located on opposite sides of the first channel region (350b, Fig. 22, para [0130] describes a second conductive region 350b coupled to a drain electrode 340 located on an opposite side of the channel region 350c from the source region 350a),
a first gate insulating layer provided on the first semiconductor layer (135_11 and 133_11, Fig. 22, para [0226] describes gate insulating layers 135_11 and 133_11),
a first gate electrode located opposite to the first channel region with the first gate insulating layer interposed therebetween (310, Fig. 22, para [0102] describes a first gate electrode located opposite to the first channel region 350c with the first gate insulating layer 133_11 and 135_11 interposed therebetween), and
a first source electrode electrically coupled with the first source region (330, Fig. 22, para [0130] describes a source electrode 330 coupled to a conductive region 350a which may comprise a source region),
wherein the second thin film transistor (ST2_11) includes
a second semiconductor layer made of an oxide semiconductor material of the second conductivity type or a transparent semiconductor material of the second conductivity type (550, Fig. 22, para [0102] describes a third active layer 550 wherein para [0125] describes the active layers may be comprised of different materials and further wherein para [0129] describes wherein the third active layer 550 may be comprised of an oxide semiconductor layer), the second semiconductor layer including a second channel region (550C, Fig. 22, para [0131] describes a second channel region 550c) and a second source region (350a, Fig. 22, para [0131] describes a third conductive region 550a coupled to a source electrode 530) and a second drain region located on opposite sides of the second channel region (550b, Fig. 22, para [0130] describes a fourth conductive region 550b coupled to a drain electrode 540 located on an opposite side of the second channel region 550c from the second source region 550a),
a second gate insulating layer provided on the second semiconductor layer (133_11, Fig. 22, para [0226] describes a second gate insulating layer 133_11),
a second gate electrode located opposite to the second channel region with the second gate insulating layer interposed therebetween (510_11, Fig. 22, para [0225] describes a third gate electrode 510_11 located opposite to the second channel region 550c with the second gate insulating layer 133_11 interposed therebetween), and
a second source electrode electrically coupled with the second source region (530, Fig. 22, para [0130] describes a second source electrode 530 coupled to a conductive region 550a which may comprise a second source region),
wherein the first gate insulating layer (133_11 and 135_11) includes a first layer (135_11, para [0226] describes a third gate insulating layer 135_11) and a second layer provided on the first layer (133_11, Fig. 22, para [0226] describes a second gate insulating layer 133_11 provided on the first layer 135_11), and
wherein the second layer of the first gate insulating layer and the second gate insulating layer are provided in the same layer (133_11, Fig. 22, para [0226] describes a second gate insulating layer 133_1 comprising a second layer of the first gate insulating layer and the second gate insulating layer for the second gate electrode 510).
Regarding Claim 2, Kim teaches the semiconductor device of claim 1, wherein
the first gate electrode and the second gate electrode are provided in the same layer (310 and 510, Fig. 22 depicts the first gate electrode 310 and second gate electrode 510_11 being comprised in a same layer 133_11), and
the first source electrode and the second source electrode are provided in the same layer (180, Fig. 22, para [0101] describes a second protective layer 180 in which the first source electrode 330 and second source electrode 530 are provided in).
Regarding Claim 3, Kim teaches the semiconductor device of claim 1 further comprising
an insulating layer provided in the same layer as the first layer of the first gate insulating layer (170, Fig. 22, para [0101] describes an interlayer insulating layer 170 that is provided in the same layer as the first layer of the first gate insulating layer 135_11),
wherein the second semiconductor layer is provided on the insulating layer (170 and 550, Fig. 22, depicts wherein the second semiconductor layer 550 is provided on the insulating layer 170).
Regarding Claim 4, Kim teaches the semiconductor device of claim 1, wherein
the first thin film transistor (DT_11) includes a first drain electrode electrically coupled with the first drain region (340, Fig. 22, para [0102] describes a source/drain electrode 340 coupled with conductive region 350b which may comprise a drain region wherein a resulting source/drain electrode 340 is a drain electrode),
the second thin film transistor (ST2_11) includes a second drain electrode electrically coupled with the second drain region (540, Fig. 22, para [0102] describes a source/drain electrode 540 coupled with conductive region 550b which may comprise a drain region wherein a resulting source/drain electrode 540 is a drain electrode),
the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are provided in the same layer (330, 340, 530, 540 and 180, Fig. 22 depicts the first source electrode 330, first drain electrode 340, second source electrode 530 and second drain electrode 540 provided in the same layer 180).
Regarding Claim 5, Kim teaches the semiconductor device of claim 4 further comprising an interlayer insulating layer provided so as to cover the first gate electrode and the second gate electrode (140, Fig. 22, para [0117] describes a protective layer 140 comprising a silicon oxide or silicon nitride covering at least a first surface of the first gate electrode 310 and second gate electrode 510_11),
wherein the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are provided on the interlayer insulating layer (140, Fig. 22 depicts wherein the first source electrode 330, first drain electrode 340, second source electrode 530 and second drain electrode 540 are provided on the interlayer insulating layer 140 with second gate insulating layer 133_11 and insulating layer 170 therebetween).
Regarding Claim 6, Kim teaches the semiconductor device of claim 1, wherein the first conductivity type is n-type (DT_11, Fig. 22, para [0083] describes wherein the driving transistors may be formed as N-type MOS transistors wherein a resulting first conductivity type is n-type), and the second conductivity type is p-type (ST2_11, Fig. 22, para [0083] describes wherein the switching transistors may be formed as P-type MOS transistors wherein a resulting second conductivity type is p-type).
Regarding Claim 7, Kim teaches the semiconductor device of claim 6, wherein the first semiconductor layer includes an In-Ga-Zn-O based semiconductor (350, Fig. 22, para [0129] describes wherein the first semiconductor layer 350 may be made of an oxide semiconductor such as indium gallium zing oxide (IGZO)).
Regarding Claim 11, Kim teaches the semiconductor device of claim 1, wherein the semiconductor device is an active matrix substrate for a display device (Fig. 2, para [0062] and para [0063] describes wherein a display device 1 comprises a plurality of pixels PX arranged in matrix form wherein para [0070] describes the pixels PX may comprise transistors comprising active regions thereby forming an active matrix substrate) that includes a display region (DA, Fig. 2, para [0061] describes a display area DA) defined by a plurality of pixel regions (PX, Fig. 2, para [0063] describes a plurality of pixels PX defining a display area DA) and a peripheral region lying around the display region (NDA, Fig. 2, para [0062] describes a non-display area NDA defining a peripheral region around the display region DA).
Regarding Claim 14, Kim teaches a display device comprising the semiconductor device of claim 11 as the active matrix substrate (1, Fig. 2, para [0066] describes a display device 1 comprising the display panel 10 as the active matrix substrate wherein the display panel 10 comprises the semiconductor device of claim 11).
Regarding Claim 16, Kim teaches the display device of claim 14, wherein the display device is an organic EL display device (1, Fig. 2, para [0059] describes wherein the display device 1 may comprise an organic light-emitting display panel 10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over by June Hwan Kim et al. (US 2021/0104558 A1; hereinafter “Kim”) in view of Saeroonter Oh et al. (US 2016/0063924 A1; hereinafter “Oh”).
Regarding Claim 12, Kim discloses all the limitations of claim 11.
Kim fails to explicitly disclose the semiconductor device of claim 11 further comprising a gate driver circuit provided in the peripheral region, wherein the gate driver circuit includes the first thin film transistor and the second thin film transistor.
However, Oh teaches a similar semiconductor device further comprising a gate driver circuit provided in the peripheral region (300, Fig. 7, para [0120] describes a gate driver circuitry 300 which may be disposed within the non-display area of the thin film transistor substrate of a display device),
wherein the gate driver circuit includes the first thin film transistor and the second thin film transistor (Fig. 7, para [0120] and para [0036] describe first and second complementary thin film transistors of an N-MOS type and a P-MOS type such as found in Kim, wherein the first thin film transistor T1 and second thin film transistor T2 may be embedded into the gate driver circuitry 300).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kim with Oh to further disclose a semiconductor device comprising a gate driver circuit in a peripheral region of a display device powered by first and second complimentary thin film transistors in order to provide the advantage of providing at least one thin film transistor having an oxide semiconductor material so that an LDD area may not be required further reducing the number of mask processes resulting in a simplified manufacturing process (Oh, para [0038]).
Regarding Claim 15, Kim discloses all the limitations of claim 14.
Kim fails to explicitly disclose the display device of claim 14, wherein the display device is a liquid crystal display device.
However, Oh teaches a similar display device, wherein the display device is a liquid crystal display device (para [0121] describes wherein the thin film transistor substrate according to the present invention may be applied to any type of display requiring an active matrix thin film transistor substrate such as a liquid crystal display).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kim with Oh to further disclose a display device which may be used as a liquid crystal display in order to provide the well-known advantage of providing a thin film transistor substrate which may be used in multiple different types of display devices increasing the number of possible intended uses for an active matrix substrate and reducing manufacturing costs when manufacturing multiple displays of different types.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over by June Hwan Kim et al. (US 2021/0104558 A1; hereinafter “Kim”) in view of Akhiro Oda et al. (US 2020/0243568 A1; hereinafter “Oda”).
Regarding Claim 13, Kim discloses all the limitations of claim 11.
Kim fails to explicitly disclose the semiconductor device of claim 11 further comprising a demultiplexer circuit provided in the peripheral region, wherein the demultiplexer circuit includes the first thin film transistor and the second thin film transistor.
However, Oda teaches a similar semiconductor device further comprising a demultiplexer circuit provided in the peripheral region (DMX, Fig. 1, para [0070] and para [0131] describes forming a demultiplexer circuit DMX in a peripheral region of a display device),
wherein the demultiplexer circuit includes the first thin film transistor and the second thin film transistor (DMX, Fig. 1, para [0070] and para [0131] describes using oxide semiconductor thin film transistors 10, such as used those found in the first thin film transistor DT_11 and second thin film transistor ST2_11 of Kim, for a demultiplexer circuit in a peripheral region of Oda).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kim with Oda to further disclose a semiconductor device comprising a demultiplexer circuit in a peripheral region of a display device powered by first and second complimentary thin film transistors in order to provide the advantage of simplifying the manufacturing process and producing a display device with a narrower bezel increasing display size (Oda, para [0070]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Thursday 7:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898