DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claim 1 in the Applicant’s response dated 16 June 2026. The claim amendments have been addressed below.
The Examiner acknowledges the amendment to the abstract in the Applicant’s response dated 16 June 2026. The objection to the abstract presented in the previous office action is therefore withdrawn.
The Examiner acknowledges the cancellation of claims 3 and 17-20 in the Applicant’s response dated 16 June 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 4-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kyeong-Ju Moon et al. (US 2021/0202634 A1; hereinafter “Moon”).
Regarding Claim 1, Moon teaches a complementary semiconductor device comprising:
a substrate (110, Fig. 3, para [0036] describes a substrate 110);
a first thin film transistor of a first conductivity type (350, Fig. 3, para [0158] describes a first thin film transistor 350 which may be comprised of an n-type TFT), the first thin film transistor being supported by the substrate (110 and 350, Fig. 3, para [0042] describes wherein the substrate may support various elements of the display apparatus, such as the first thin film transistor 350); and
a second thin film transistor of a second conductivity type that is different from the first conductivity type (320, Fig. 3, para [0158] describes a second thin film transistor 320 which may be comprised of a p-type TFT different than the first n-type TFT), the second thin film transistor being supported by the substrate (110 and 320, Fig. 3, para [0042] describes wherein the substrate may support various elements of the display apparatus, such as the second thin film transistor 320), wherein
the first thin film transistor (350, Fig. 3) includes
a first semiconductor layer made of an oxide semiconductor material of the first conductivity type (351, Fig. 3, para [0117] describes a first semiconductor layer 351 made of an oxide semiconductor pattern of the first n-type), the first semiconductor layer including a first channel region (351C, Fig. 3, para [0118] describes a first channel region 351C) and a first source region (351S, Fig. 3, para [0118] describes a first source region 351S) and a first drain region located on opposite sides of the first channel region (351D, Fig. 3, para [0118] describes a first drain region 351D on an opposite side of the first channel 351C from the first source region 351S),
a first gate insulating layer provided on the first semiconductor layer (FGI, annotated Fig. 3, para [0159] wherein a first gate insulating layer FGI comprises portions of insulating layers 115 and 116 is provided on the first semiconductor layer 351),
a first gate electrode located opposite to the first channel region with the first gate insulating layer interposed therebetween (354, Fig. 3, para [0116] describes a first gate electrode 354 located opposite to the first channel region 351 with the first gate insulating layer FGI interposed therebetween), and
a first source electrode electrically coupled with the first source region (352, Fig. 3, para [0116] describes a first source electrode 352 electrically coupled to the first source region 351S),
the second thin film transistor (320, Fig. 3) includes
a second semiconductor layer made of an oxide semiconductor material of the second conductivity type or a transparent semiconductor material of the second conductivity type (321, Fig. 3, para [0122] describes a second semiconductor layer 321 made of an oxide semiconductor pattern of the second p-type), the second semiconductor layer including a second channel region (321C, Fig. 3, para [0123] describes a second channel region 321C) and a second source region (321S, Fig. 3, para [0123] describes a second source region 321S) and a second drain region located on opposite sides of the second channel region (321D, Fig. 3, para [0123] describes a second drain region 321D on an opposite side of the second channel 321C from the second source region 321S),
a second gate insulating layer provided on the second semiconductor layer (SGI, annotated Fig. 3, para [0159] wherein a second gate insulating layer SGI comprising insulating layer 116 is provided on the second semiconductor layer 321),
a second gate electrode located opposite to the second channel region with the second gate insulating layer interposed therebetween (324, Fig. 3, para [0122] describes a second gate electrode 324 located opposite to the second channel region 321 C with the second gate insulating layer SGI interposed therebetween), and
a second source electrode electrically coupled with the second source region (322, Fig. 3, para [0122] describes a second source electrode 322 coupled to the second source region 321S), and
an insulating layer provided between the second semiconductor layer and the substrate (115, Fig. 3, para [0066] describes an insulating layer 115 provided between the second semiconductor layer 321 and the substrate 110),
the first gate insulating layer includes a first layer and a second layer provided on the first layer (FGI, 115 and 116, annotated Fig. 3, para [0159] wherein the first gate insulating layer FGI includes a first insulating layer 115 and a second insulating layer 116 provided on the first layer 115), and
the second layer of the first gate insulating layer and the second gate insulating layer are provided in the same layer (116 and SGI, annotated Fig. 3 depicts wherein the second layer 116 of the first gate insulating layer FGI and the second gate insulting layer SGI are provided in the same layer),
the first layer of the first gate insulating layer and the insulating layer are provided in the same layer (115, annotated Fig. 3, para [0159] describes a continuous insulating layer 115 wherein the first layer 115 of the first gate insulating layer FGI and the insulating layer 115 provided between the second semiconductor layer 321 and the substrate 110 are provided in the same continuous insulating layer 115),
the first semiconductor layer is provided between the substrate and the first gate insulating layer (351, 110 and FGI, annotated Fig. 3 depicts wherein the first semiconductor layer 351 is provided between the substrate 110 and the first gate insulating layer FGI), and
the second semiconductor layer is provided between the substrate and the second gate insulating layer (321, 110 and SGI, annotated Fig. 3 depicts wherein the second semiconductor layer 321 is provided between the substrate 110 and the second gate insulating layer SGI).
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Regarding Claim 2, Moon teaches the semiconductor device of claim 1, wherein
the first gate electrode and the second gate electrode are provided in the same layer (354, 324 and 117, Fig. 3, para [0188] describes a second interlayer insulating layer 117 in which both the first gate electrode 354 and second gate electrode 324 are provided), and
the first source electrode and the second source electrode are provided in the same layer (352, 322 and 118, Fig. 3, para [0159] describes a passivation layer 118 in which both the first source electrode 352 and second source electrode 322 are provided).
Regarding Claim 4, Moon teaches the semiconductor device of claim 1, wherein
the first thin film transistor (350, Fig. 3) includes a first drain electrode electrically coupled with the first drain region (353, Fig. 3, para [0174] describes a first drain electrode 353 electrically coupled with the first drain region 351D),
the second thin film transistor (320, Fig. 3) includes a second drain electrode electrically coupled with the second drain region (323, Fig. 3, para [0178] describes a second drain electrode 323 electrically coupled with the second drain region 321D),
the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are provided in the same layer (352, 353, 322, 323 and 118, Fig. 3, para [0159] describes a passivation layer 118 in which the first source electrode 352, first drain electrode 353, second source electrode 322 and second drain electrode 323 are provided).
Regarding Claim 5, Moon teaches the semiconductor device of claim 4 further comprising an interlayer insulating layer provided so as to cover the first gate electrode and the second gate electrode (117, 354 and 325, Fig. 3, para [0188] describes a second interlayer insulating layer 117 provided so as to cover both the first gate electrode 354 and second gate electrode 324),
wherein the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are provided on the interlayer insulating layer (352, 353, 322, 323 and 117, Fig. 3 depicts wherein the first source electrode 352, the first drain electrode 353, the second source electrode 322 and the second drain electrode 323 are provided on the interlayer insulating layer 117).
Regarding Claim 6, Moon teaches the semiconductor device of claim 1, wherein the first conductivity type is n-type (350, Fig. 3, para [0158] describes wherein the first thin film transistor 350 comprises a first conductivity type wherein the first conductivity type may be n-type), and the second conductivity type is p-type (320, Fig. 3, para [0158] describes wherein the second thin film transistor 320 comprises a second conductivity type wherein the second conductivity type may be p-type).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kyeong-Ju Moon et al. (US 2021/0202634 A1; hereinafter “Moon”) in view of the following arguments:
Regarding Claim 7, Moon discloses all the limitations of claim 6.
Moon fails to explicitly disclose the semiconductor device of claim 6, wherein the first semiconductor layer includes an In-Ga-Zn-O based semiconductor.
However, Moon describes in para [0156] wherein the first thin film transistor (350) comprising the first semiconductor layer (351) may be a driving thin film transistor and the first semiconductor layer (351) may be an oxide semiconductor layer. Moon further describes in para [0069], a thin film transistor comprising an oxide semiconductor such as a third semiconductor pattern (331) may be used as a driving thin film transistor and para [0070] describes wherein an example of an oxide semiconductor used for the third semiconductor pattern (331) of a driving thin film transistor may be indium gallium zinc oxide (IGZO) or In-Ga-Zn-O.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different oxide semiconductor materials from a finite number of possible oxide semiconductor materials, such as the In-Ga-Zn-O based semiconductor used in similar oxide semiconductor patterns by Moon, resulting in a first semiconductor layer including an In-Ga-Zn-O based semiconductor in order to provide the advantage of providing a thin film transistor which can applied to a variety of different uses in a display device such as a driving thin film transistor or a switching thin film transistor (Moon, para [0069] and para [0070]) and to provide the well-known advantage of providing a same oxide semiconductor material for multiple different thin film transistors in a semiconductor device therefore simplifying the manufacturing process which may lower cost and increase throughput.
Claim 11-12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kyeong-Ju Moon et al. (US 2021/0202634 A1; hereinafter “Moon”) in view of Saeroonter Oh et al. (US 2016/0063924 A1; hereinafter “Oh”).
Regarding Claim 11, Moon teaches the semiconductor device of claim 1, wherein the semiconductor device is a substrate for a display device (Fig. 3, para [0155] describes wherein Fig. 3 is a sectional view of a display apparatus) that includes a display region defined by a plurality of pixel regions (DA, Fig. 3, para [0156] describes a display area DA constituted by a plurality of pixels) and a peripheral region lying around the display region (NDA, Fig. 3, para [0157] describes a non-display area NDA adjacent to the display region DA in the substrate 310).
Moon fails to explicitly disclose wherein the semiconductor device is an active matrix substrate for a display device.
However, Oh describes a similar semiconductor device wherein the semiconductor device is an active matrix substrate for a display device (Fig. 10, para [0121] describes wherein the thin film substrate according to the present invention may be applied to any type of display requiring an active matrix thin film transistor substrate).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Moon with Oh to further disclose a semiconductor device wherein the semiconductor device is an active matrix substrate for a display device in order to provide the advantage of enabling a display device substrate to be used in a wide variety of display use cases that require an active matrix thin film transistor substrate such as a liquid crystal display or an organic light emitting diode display therefore increasing the number of potential end users of the display device (Oh, para [0121]).
Regarding Claim 12, the combination of Moon and Oh discloses all the limitations of claim 11.
Moon fails to explicitly disclose the semiconductor device of claim 11 further comprising a gate driver circuit provided in the peripheral region, wherein the gate driver circuit includes the first thin film transistor and the second thin film transistor.
However, Oh teaches a similar semiconductor device further comprising a gate driver circuit provided in the peripheral region (300, Fig. 7, para [0120] describes a gate driver circuitry 300 which may be disposed within the non-display area of the thin film transistor substrate of a display device),
wherein the gate driver circuit includes the first thin film transistor and the second thin film transistor (Fig. 7, para [0120] and para [0036] describe first and second complementary thin film transistors of an n-type and a p-type such as found in Moon, wherein the first thin film transistor T1 and second thin film transistor T2 may be embedded into the gate driver circuitry 300).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Moon with Oh to further disclose a semiconductor device comprising a gate driver circuit in a peripheral region of a display device powered by first and second complimentary thin film transistors in order to provide the advantage of providing at least one thin film transistor having an oxide semiconductor material so that an LDD area may not be required further reducing the number of mask processes resulting in a simplified manufacturing process (Oh, para [0038]).
Regarding Claim 14, the combination of Moon and Oh teaches a display device comprising the semiconductor device of claim 11 as the active matrix substrate (Oh, Fig. 10, para [0121] describes using the active matrix thin film transistor substrate of claim 11 in a display device such as an OLED or LCD wherein Fig. 10 depicts one pixel of the active matrix substrate as describes in para [0131]).
Regarding Claim 15, the combination of Moon and Oh teaches the display device of claim 14, wherein the display device is a liquid crystal display device (Oh, Fig. 10, para [0121] describes wherein the display device using the active matrix thin film transistor substrate may be a liquid crystal display).
Regarding Claim 16, the combination of Moon and Oh teaches the display device of claim 14, wherein the display device is an organic EL display device (Oh, Fig. 10, para [0121] describes wherein the display device using the active matrix thin film transistor substrate may be an organic light emitting diode display).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kyeong-Ju Moon et al. (US 2021/0202634 A1; hereinafter “Moon”) in view of Saeroonter Oh et al. (US 2016/0063924 A1; hereinafter “Oh”) and in further view of Akhiro Oda et al. (US 2020/0243568 A1; hereinafter “Oda”).
Regarding Claim 13, the combination of Moon and Oh discloses all the limitations of claim 11.
Moon and Oh fails to explicitly disclose the semiconductor device of claim 11 further comprising a demultiplexer circuit provided in the peripheral region, wherein the demultiplexer circuit includes the first thin film transistor and the second thin film transistor.
However, Oda teaches a similar semiconductor device further comprising a demultiplexer circuit provided in the peripheral region (DMX, Fig. 1, para [0070] and para [0131] describes forming a demultiplexer circuit DMX in a peripheral region of a display device),
wherein the demultiplexer circuit includes the first thin film transistor and the second thin film transistor (DMX, Fig. 1, para [0070] and para [0131] describes using oxide semiconductor thin film transistors 10, such as used those found in the first thin film transistor 350 and second thin film transistor 320 of Moon, for a demultiplexer circuit in a peripheral region of Oda).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Moon and Oh with Oda to further disclose a semiconductor device comprising a demultiplexer circuit in a peripheral region of a display device powered by first and second complimentary thin film transistors in order to provide the advantage of simplifying the manufacturing process and producing a display device with a narrower bezel increasing display size (Oda, para [0070]).
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 4-7 and 11-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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