Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
The claims recite “first to sixth conductors”, “first/second channel formation region” and “first/second insulators”. The specification is objected to as failing to provide proper antecedent basis for said elements.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2-4 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification recites that the first gate electrode and the second gate electrode are elements 404 and 413, respectively. Said elements are described in the non-elected embodiment of figure 6B.
There is no support in the elected embodiment of figure 31 for said elements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoneda et al. (2013/0161607).
Regarding claims 1-4, Yoneda et al. teach in figure 1B and related text a semiconductor device comprising
a first transistor Tr111 including a first channel formation region, the first channel formation region which can comprise silicon;
a second transistor Tr112 comprising an oxide semiconductor 110b, the oxide semiconductor including a second channel formation region; and
a capacitor C112,
wherein a first conductor 121a overlaps with the first channel formation region,
wherein the first conductor 121a (at least part thereof) does not overlap with the oxide semiconductor,
wherein a second conductor 121b is in contact with the oxide semiconductor 110a,
wherein a third conductor 122b is in contact with the oxide semiconductor and is electrically connected to the first conductor,
wherein the third conductor is one electrode of the capacitor C112,
wherein a first insulator 102 is positioned over the first conductor 121a,
wherein the oxide semiconductor 110b is positioned over the first insulator 102,
wherein a second insulator 105 is positioned over the oxide semiconductor, the second conductor, and the third conductor,
wherein the second insulator include an opening,
wherein a fourth conductor 160b (the vertical part located on the right side) is positioned in the opening, and
wherein the fourth conductor is electrically connected to the second conductor.
Yoneda et al. do not explicitly state that the first channel formation region comprising silicon.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first channel formation region comprising silicon in Yoneda et al.’s device, in order to reduce the cost of making the device by using conventional channel region material.
Regarding claim 2, Yoneda et al. teach in figure 1B and related text that the oxide semiconductor 110b is interposed between a fifth conductor 123b and a sixth conductor (the horizontal part of element 160b), and wherein the fifth conductor, the sixth conductor, and the second channel formation region overlap with one another.
Regarding claim 3, Yoneda et al. teach in figure 1B and related text that a fifth conductor (133 or 123b) overlaps with the second channel formation region 110b, and wherein a part of a bottom surface of the fifth conductor is positioned under a bottom surface (located on the right side) of the second channel formation region.
Regarding claim 4, Yoneda et al. teach in figure 1B and related text that the oxide semiconductor 110b is interposed between a fifth conductor 160b/123b and a sixth conductor 123b, and the fifth conductor is positioned over the oxide semiconductor,
wherein the fifth conductor, the sixth conductor, and the second channel formation region overlap with one another, and wherein a part of a bottom surface of the fifth conductor 160b/123b is positioned under a bottom surface (located on the right side) of the second channel formation region.
Regarding claims 2-4, Yoneda et al. further teach in figure 10 and related text that the fifth conductor (in structure 250c) is configured to be a first gate electrode (chosen as such), wherein the sixth conductor (in structure 250e e.g.) is configured to be a second gate electrode (chosen as such).
Response to Arguments
1. Applicants argue that “it would be clear to one of ordinary skill in the art, given the context and other structural features recited in the claims, that the ordinal designations recited in claims 1-4 for the conductors, channel formation regions, and insulators are intrinsic from the descriptions in the specification and elements depicted in the drawings. In particular, the general descriptions of conductors, channel formation regions, and insulating films in the specification, with respect to at least FIGS. 6B and 31, would reasonably convey to one skilled in the relevant art that the structural aspects recited in claims 1-4 denote first, second, third, fourth, fifth, and sixth conductors, first and second channel formation regions, and first and second insulating films”.
Applicants further argue that “Furthermore, applicant submits that, as required under MPEP §2163, the specification describes the claimed invention in sufficient detail that one skilled in the art can reasonably conclude that the inventor had possession of the claimed invention. In the present case, applicant submits that the features recited in claims 1-4 are sufficiently described in the specification to reasonably convey to one skilled in the relevant art that the inventor, at the time the application was filed, had possession of the claimed invention, with respect to at least the structural features shown in at least FIGS. 6B and 31, as well as the structural features described in the specification, although an ordinal designation of conductors, channel formation regions, and insulators recited in the claims may not be explicitly described”.
1. Contrary to applicants’ assertion that an artisan would understand the correlation between the claimed elements and the disclosure, an artisan would not understand said correlation. The examiner suggests to either officially annotate the drawings as provided by the current response or amending the disclosure to include the elements “first to sixth conductors”, “first/second channel formation region” and “first/second insulators” therein.
Regarding applicants’ argument that figure 6B provides support for the claimed elements, it is noted that figure 31 was elected for examination, and not figure 6B.
2. Applicants argue that Yoneda does not teach that "the first conductor does not overlap with the oxide semiconductor," as recited in claim 1.
2. Yoneda teaches that at least part of the first conductor does not overlap with the oxide semiconductor.
The broad recitation of the claim does not require that the entire first conductor does not overlap with the oxide semiconductor.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
3/26/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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