Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments have been fully considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-10, 14-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. US 2022/0246549.
Re claim 1, Wu teaches a semiconductor package substrate core (114, fig2A, [30]) comprising:
a substrate core material comprising a brittle material (114 as Si, Fig2A, [30]; Silicon is a hard and brittle material [2] teaching reference Choong et al. US 2020/0039109);
at least one crack cessation structure (107 with 107a and 107b, fig2A, [32]) formed within said substrate core material,
said crack cessation structure being formed in said substrate core material to a first depth (fig2A); and
wherein said crack cessation structure comprises at least a selected one of one hole and one trench (201 and 203, fig2A, [32]);
said crack cessation structure being further characterized as being filled with a selected one of an insulative material and a metallic material (201 as dielectric material and 203 as metal material, fig2A, [32]); and
wherein said crack cessation structure (107 with 107a and 107b, fig2A, [32]) is positioned inward of an exterior edge (outer edge of 114 away from center 109, fig2A and 2B, [32]) of said semiconductor package substrate core and between said exterior edge (outer edge of 114 away from center 109, fig2A and 2B) and an interior region (109, fig2A and 2B, [32]) of said semiconductor package substrate core, and is arranged as a crack-stop structure to arrest propagation of a crack (131, fig2A and 2B, [25]) originating from said exterior edge toward said interior region by dissipating or diverting crack energy (fig2A and 2B).
Re claim 2, Wu teaches the semiconductor package substrate core of claim 1, wherein said crack cessation structure (107 with 107a and 107b, fig2A, [32]) formed in said substrate core material to a first depth is further characterized as being formed near the exterior edge (outer edge of 114 away from center 109, fig2A and 2B, [32]) of said semiconductor package substrate core (114, fig2A, [30]).
Re claim 3, Wu teaches the semiconductor package substrate core of claim 2, wherein said first depth is greater than one-half of the thickness of said semiconductor package substrate core (107 with 107a and 107b, fig2A, [32]).
Re claim 7, Wu teaches the semiconductor package substrate core of claim 1, wherein the at least one trench is further characterized as a partial trench (201, 203, fig2A, [32]).
Re claim 8, Wu teaches a method for manufacturing a semiconductor package substrate core (114, fig2A, [30]), comprising:
forming a substrate core material comprising a brittle material (114 as Si, Fig2A, [30]; Silicon is a hard and brittle material [2] teaching reference Choong et al. US 2020/0039109);
forming at least one crack cessation structure (107 with 107a and 107b, fig2A, [32]) in said substrate core material,
said crack cessation structure being formed in said substrate core material to a first depth (fig2A),
said crack cessation structure comprising at least a selected one of one hole and one trench (201 and 203, fig2A, [32]); and
filling the at least a selected one of one hole and one trench with a selected one of an insulative material and a metallic material (201 as dielectric material and 203 as metal material, fig2A, [32]),
wherein said crack cessation structure (107 with 107a and 107b, fig2A, [32]) is formed inward of an exterior edge (outer edge of 114 away from center 109, fig2A and 2B, [32]) of said semiconductor package substrate core and between said exterior edge (outer edge of 114 away from center 109, fig2A and 2B, [32]) and an interior region (109, fig2A and 2B, [32]) of said semiconductor package substrate core, and is arranged as a crack-stop structure to arrest propagation of a crack originating (131, fig2A and 2B, [25]) from said exterior edge toward said interior region by dissipating or diverting crack energy.
Re claim 9, Wu teaches the method of manufacturing a semiconductor package substrate core of claim 8, wherein said crack cessation structure (107 with 107a and 107b, fig2A, [32]) formed in said substrate core material (114 as Si, Fig2A, [30]) to a first depth is further characterized as being formed near the exterior edge (outer edge of 114 away from center 109, fig2A and 2B, [32]) of said semiconductor package substrate core (114, fig2A, [30]).
Re claim 10, Wu teaches the method of manufacturing a semiconductor package substrate core of claim 9, wherein said first depth is greater than one-half of the thickness of said semiconductor package substrate core (107 with 107a and 107b, fig2A, [32]).
Re claim 14, Wu teaches the method of manufacturing a semiconductor package substrate core of claim 8, wherein the at least one trench is further characterized as a partial trench (201, 203, fig2A, [32]).
Re claim 15, Wu teaches a semiconductor package substrate core (114, fig2A, [30]) comprising:
a substrate core material comprising a brittle material (114 as Si, Fig2A, [30]; Silicon is a hard and brittle material [2] teaching reference Choong et al. US 2020/0039109); and
at least one crack cessation structure (107 with 107a and 107b, fig2A, [32]) formed within said substrate core material,
said crack cessation structure further comprising:
a first hole formed in said substrate core material to a first depth (107a, fig2A, [32]),
said hole being formed in a first surface of said substrate core material (top surface of 114, fig2A), and said hole being filled with a selected one of an insulative material and a metallic material (201 as dielectric material and 203 as metal material, fig2A, [32]); and
a second hole formed in said substrate core material to a second depth (107b, fig2A, [32]), said hole being formed in a second surface (bottom surface of 114, fig2A) of said substrate core material opposite said first surface, and
said hole being filled with a selected one of an insulative material and a metallic material (201 as dielectric material and 203 as metal material, fig2A, [32]),
wherein said first hole and said second hole form an offset pair of blind holes (107a and 107b, fig2A, [32]) positioned inward of an exterior edge (outer edge of 114 away from center 109, fig2A and 2B, [32]) of said semiconductor package substrate core and between said exterior edge (outer edge of 114 away from center 109, fig2A and 2B, [32]) and an interior region (109, fig2A and 2B, [32]) of said semiconductor package substrate core to arrest propagation of a crack (131, fig2A and 2B, [25]) originating from said exterior edge toward said interior region.
Re claim 16, Wu teaches the semiconductor package substrate core of claim 15, wherein said crack cessation structure (107 with 107a and 107b, fig2A, [32]) formed in said substrate core material (114, fig2A, [30]) is further characterized as being formed near the exterior edge (outer edge of 114 away from center 109, fig2A and 2B, [32]) of said semiconductor package substrate core (114, fig2A, [30]).
Re claim 17, Wu teaches the semiconductor package substrate core of claim 16, wherein said first depth is greater than one-half of the thickness of said semiconductor package substrate core (107a through 114, fig2A, [32]), and said second depth is greater than one-half of the thickness of said semiconductor package substrate core (107b through 114, fig2A, [32]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2022/0246549 in view of Dyer et al. US 2015/0325531.
Re claim 4, Wu teaches the semiconductor package substrate core of claim 1, wherein the at least one hole is characterized as a blind structure (201 as dielectric material and 203 as metal material, fig2A, [32]).
Wu does not explicitly show the at least one hole is characterized as a blind via.
Dyer teaches crack structure with at least one hole characterized as a blind via (130, fig14, [58]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu and Dyer to adjust the shape of 107a and 107b as TSVs 130 in Dyer fig14. The motivation to do so is to prevent propagation of crack at the corner region (Dyer, [59]).
Re claim 5, Wu does not explicitly show the semiconductor package substrate core of claim 1, wherein the at least one hole is characterized as a through hole.
Dyer teaches crack structure with at least one hole characterized as a through hole (130, fig14, [58]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu and Dyer to adjust the shape of 107a and 107b as TSVs 130 in Dyer fig14. The motivation to do so is to prevent propagation of crack at the corner region (Dyer, [59]).
Re claim 6, Wu does not explicitly show the semiconductor package substrate core of claim 1, wherein the at least one hole is characterized as an offset pair of blind vias.
Dyer teaches crack structure with at least one hole characterized as an offset pair of blind vias (130, fig14, [58]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu and Dyer to adjust the shape of 107a and 107b as TSVs 130 in Dyer fig14. The motivation to do so is to prevent propagation of crack at the corner region (Dyer, [59]).
Re claim 11, Wu teaches the method of manufacturing a semiconductor package substrate core of claim 8, wherein the at least one hole is characterized as a blind structure (201 as dielectric material and 203 as metal material, fig2A, [32]).
Wu does not explicitly show the at least one hole is characterized as a blind via.
Dyer teaches crack structure with at least one hole characterized as a blind via (130, fig14, [58]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu and Dyer to adjust the shape of 107a and 107b as TSVs 130 in Dyer fig14. The motivation to do so is to prevent propagation of crack at the corner region (Dyer, [59]).
Re claim 12, Wu does not explicitly show the method of manufacturing a semiconductor package substrate core of claim 8, wherein the at least one hole is characterized as a through hole.
Dyer teaches crack structure with at least one hole characterized as a through hole (130, fig14, [58]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu and Dyer to adjust the shape of 107a and 107b as TSVs 130 in Dyer fig14. The motivation to do so is to prevent propagation of crack at the corner region (Dyer, [59]).
Re claim 13, Wu does not explicitly show the method of manufacturing a semiconductor package substrate core of claim 8, wherein the at least one hole is characterized as an offset pair of blind vias.
Dyer teaches crack structure with at least one hole characterized as an offset pair of blind vias (130, fig14, [58]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu and Dyer to adjust the shape of 107a and 107b as TSVs 130 in Dyer fig14. The motivation to do so is to prevent propagation of crack at the corner region (Dyer, [59]).
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2022/0246549 in view of Marimuthu et al. US 2019/0088603 and Dennison et al. US 2016/0195581.
Re claim 18, Wu teaches an apparatus (fig2A) comprising:
a semiconductor package substrate core (114, fig2A, [30]) comprising a brittle substrate core material (114 as Si, Fig2A, [30]; Silicon is a hard and brittle material [2] teaching reference Choong et al. US 2020/0039109);
a first defect sensor structure (107 with 107a and 107b, fig2A, [32]) formed in said brittle substrate core material (114 as Si, Fig2A, [30]) and arranged as a crack-stop structure positioned inward of an exterior edge (outer edge of 114 away from center 109, fig2A and 2B, [32]) of said semiconductor package substrate core and between said exterior edge (outer edge of 114 away from center 109, fig2A and 2B, [32]) and an interior region (109, fig2A and 2B, [32]) of said semiconductor ackage substrate core.
Wu does not explicitly show a first plated-through hole disposed in said brittle substrate core material having: a first top terminal disposed on a first surface of said semiconductor package substrate core; and a first bottom terminal disposed on a second surface of said semiconductor package substrate core; a second plated-through hole disposed in said brittle substrate core material having: a second top terminal disposed on said first surface of said semiconductor package substrate core; and a second bottom terminal disposed on said second surface of said semiconductor package substrate core; and a conductive connecting track coupled to said first bottom terminal and to said second bottom terminal; and said rst defect sensor structure configured to receive a detection signal therethrough between the first top terminal and the second top terminal to detect a break in the conductive track between said first and second top terminals and thereby detect a defect in the semiconductor substrate package core, and wherein said first defect sensor structure is further configured to arrest propagation of a crack originating from said exterior edge toward said interior region.
Marimuthu teaches vias (174, fig4, [45]) through core substrate (172, fig4, [45]) formed by plating ([45]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu and Marimuthu to form the through hole vias by a plating process to achieve desirable electrical property (Marimuthu, [45]).
Dennison teaches a first defect sensor structure (225/425, fig2 and 4, [18, 26]) comprising:
a first through hole (one via of chain 225, fig2) disposed in said substrate having:
a first top terminal disposed (226, fig2, [18]) on a first surface of said substrate (top surface of die, fig2); and
a first bottom terminal (231, fig2, [18]) disposed on a second surface of said substrate (bottom surface of die, fig2);
a second through hole (another via of chain 225/425, fig2 and 4, [18, 26]) disposed in said substrate having:
a second top terminal disposed (226, fig2, [18]) on said first surface of said substrate; and
a second bottom terminal (231, fig2, [18]) disposed on said second surface of said substrate; and
a conductive connecting track coupled to said first bottom terminal and to said second bottom terminal (fig2 and 4); and
said first defect sensor structure configured to receive a detection signal therethrough between the first top terminal and the second top terminal to detect a break in the conductive track between said first and second top terminals and thereby detect a defect in the semiconductor substrate package core (fig2, 4 and 5, [31]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu in view of Marimuthu and Dennison to replace 107a with the via chain as in Dennsion using 201 of Wu as 231 of Dennison and adjusting 203 as upper part of Dennsion 225. The motivation to do so is to detect cracks formed in the interposer layer and improve process yield (Dennison, [2]).
Wu modified above teaches wherein said first defect sensor structure (Wu 107 in fig 2A with 107a adjusted as in 225 Dennison fig2A) is further configured to arrest propagation of a crack (Wu, 131, fig2A and 2B, [25]) originating from said exterior edge toward said interior region.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOMING LIU whose telephone number is (571)270-0384. The examiner can normally be reached Monday-Friday, 9am-8pm, EST.
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/XIAOMING LIU/Examiner, Art Unit 2812
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