DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 15 objected to because of the following informalities: the claim appears to have a typographical error " a second hold formed in said substrate core material to a second depth ". For the purpose of examination, the examiner will interpret the above limitation as " a second hole formed in said substrate core material to a second depth".
Claim 18 objected to because of the following informalities: the claim appears to have a typographical error “a second plated-through hole disposed in said substrate having: a top terminal disposed on said first surface of said substrate”. For the purpose of examination, the examiner will interpret the above limitation as “a second plated-through hole disposed in said substrate having: a second top terminal disposed on said first surface of said substrate”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-8 and 11-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. US 2020/0105544.
Re claim 1, Tsai teaches a semiconductor package substrate core (100, fig7 or 12, [20]) comprising:
a substrate core material (110, Fig7, [24]);
at least one crack cessation structure (120, fig7, [29]) formed within said substrate core material,
said crack cessation structure being formed in said substrate core material to a first depth (fig7); and
wherein said crack cessation structure comprises at least a selected one of one hole and one trench (114, fig4, [26]);
said crack cessation structure being further characterized as being filled with a selected one of an insulative material and a metallic material (120 formed in same process as via 116, fig5, [29]).
Re claim 4, Tsai teaches the semiconductor package substrate core of claim 1, wherein the at least one hole is characterized as a blind via (120 uncoupled and electrically floats formed in same process as via 116, fig5, [29]).
Re claim 5, Tsai teaches the semiconductor package substrate core of claim 1, wherein the at least one hole is characterized as a through hole (fig7 or 12).
Re claim 6, Tsai teaches the semiconductor package substrate core of claim 1, wherein the at least one hole is characterized as an offset pair of blind vias (fig7 or 12).
Re claim 7, Tsai teaches the semiconductor package substrate core of claim 1, wherein the at least one trench is further characterized as a partial trench (114 over 106, fig4, [24]).
Re claim 8, Tsai teaches a method for manufacturing a semiconductor package substrate core (100, fig7 or 12, [20]), comprising:
forming a substrate core material (110, Fig3, [24]);
forming at least one crack cessation structure (120, fig5, [29]) in said substrate core material,
said crack cessation structure being formed in said substrate core material to a first depth (fig5),
said crack cessation structure comprising at least a selected one of one hole and one trench (114, fig4, [26]); and
filling the at least a selected one of one hole and one trench with a selected one of an insulative material and a metallic material (120 formed in same process as via 116, fig5, [29]).
Re claim 11, Tsai teaches the method of manufacturing a semiconductor package substrate core of claim 8, wherein the at least one hole is characterized as a blind via (120 uncoupled and electrically floats formed in same process as via 116, fig5, [29]).
Re claim 12, Tsai teaches the method of manufacturing a semiconductor package substrate core of claim 8, wherein the at least one hole is characterized as a through hole (fig7 or 12).
Re claim 13, Tsai teaches the method of manufacturing a semiconductor package substrate core of claim 8, wherein the at least one hole is characterized as an offset pair of blind vias (fig12).
Re claim 14, Tsai teaches the method of manufacturing a semiconductor package substrate core of claim 8, wherein the at least one trench is further characterized as a partial trench (114 over 106, fig4, [24]).
Re claim 15, Tsai teaches a semiconductor package substrate core (100, fig7 or 12, [20]) comprising:
a substrate core material (110, Fig3, [24]); and
at least one crack cessation structure (120, fig5, [29]) formed within said substrate core material,
said crack cessation structure further comprising:
a first hole formed in said substrate core material to a first depth (114 over 106, fig4, [24]),
said hole being formed in a first surface of said substrate core material (top surface of 110, fig7), and said hole being filled with a selected one of an insulative material and a metallic material (120 formed in same process as via 116, fig5, [29]); and
a second hole formed in said substrate core material to a second depth (120, fig5, [29]), said hole being formed in a second surface (bottom surface of 110, fig7) of said substrate core material opposite said first surface, and
said hole being filled with a selected one of an insulative material and a metallic material (120 formed in same process as via 116, fig5, [29]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 9-10 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. US 2020/0105544 in view of and Dennison et al. US 2016/0195581.
Re claim 2, Tsai teaches the semiconductor package substrate core of claim 1 wherein said crack cessation structure (120, fig7, [29]) formed in said substrate core material (110, Fig7, [24]) to a first depth.
Tsai does not explicitly show said crack cessation structure formed near the exterior edge of said package substrate.
Dennison teaches crack cessation structure (225/425, fig2 and 4, [18, 26]) formed near the exterior edge of said package substrate.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai and Dennison to add a set of crack cessation structure around outer edge as in Dennsion. The motivation to do so is to detect cracks formed in the interposer layer and improve process yield (Dennison, [2]).
Re claim 3, Tsai modified above teaches the semiconductor package substrate core of claim 2 wherein said first depth is greater than one-half of the thickness of said package substrate (fig12).
Re claim 9, Tsai teaches the method of manufacturing a semiconductor package substrate core of claim 8 wherein said crack cessation structure (120, fig12, [29]) formed in said substrate core material (110, Fig12, [24]) to a first depth.
Tsai does not explicitly show said crack cessation structure formed near the exterior edge of said package substrate.
Dennison teaches crack cessation structure (225/425, fig2 and 4, [18, 26]) formed near the exterior edge of said package substrate.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai and Dennison to add a set of crack cessation structure around outer edge as in Dennsion. The motivation to do so is to detect cracks formed in the interposer layer and improve process yield (Dennison, [2]).
Re claim 10, Tsai modified above teaches the method of manufacturing a semiconductor package substrate core of claim 9 wherein said first depth is greater than one-half of the thickness of said package substrate (fig7 or 12).
Re claim 16, Tsai does not explicitly show the semiconductor package substrate core of claim 15 wherein said crack cessation structure formed in said substrate core material is further characterized as being formed near the exterior edge of said package substrate.
Dennison teaches crack cessation structure (225/425, fig2 and 4, [18, 26]) formed near the exterior edge of said package substrate.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai and Dennison to add a set of crack cessation structure around outer edge as in Dennsion. The motivation to do so is to detect cracks formed in the interposer layer and improve process yield (Dennison, [2]).
Re claim 17, Tsai modified above teaches the semiconductor package substrate core of claim 16 wherein said first depth is greater than one-half of the thickness of said semiconductor package substrate core (120 over 106, fig30 or 78), and said second depth is greater than one-half of the thickness of said semiconductor package substrate core (120 through 110, fig30 or 78).
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. US 2020/0105544 in view of Marimuthu et al. US 2019/0088603 and Dennison et al. US 2016/0195581.
Re claim 18, Tsai teaches an apparatus (fig12 and 13) comprising:
a substrate (100, fig12, [19]);
a first through hole (120 around 140, fig12 and 13, [29]) disposed in said substrate;
a second through hole ( another 120 around 140, fig12 and 13, [29]) disposed in said substrate.
Tsai does not explicitly show the through hole are plated to for the via and a first defect sensor structure comprising: a first plated-through hole disposed in said substrate having: a first top terminal disposed on a first surface of said substrate; and a first bottom terminal disposed on a second surface of said substrate;
a second plated-through hole disposed in said substrate having: a top terminal disposed on said first surface of said substrate; and a second bottom terminal disposed on said second surface of said substrate; and a conductive connecting track coupled to said first bottom terminal and to said second bottom terminal; and
said first defect sensor structure configured to receive a detection signal therethrough between the first top terminal and the second top terminal to detect a break in the conductive track between said first and second top terminals and thereby detect a defect in the substrate.
Marimuthu teaches vias (174, fig4, [45]) through core substrate (172, fig4, [45]) formed by plating ([45]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai and Marimuthu to for the through hole vias by a plating process to achieve desirable electrical property (Marimuthu, [45]).
Dennison teaches a first defect sensor structure (225/425, fig2 and 4, [18, 26]) comprising:
a first through hole (one via of chain 225, fig2) disposed in said substrate having:
a first top terminal disposed (226, fig2, [18]) on a first surface of said substrate (top surface of die, fig2); and
a first bottom terminal (231, fig2, [18]) disposed on a second surface of said substrate (bottom surface of die, fig2);
a second plated-through hole (another via of chain 225/425, fig2 and 4, [18, 26]) disposed in said substrate having:
a second top terminal disposed (226, fig2, [18]) on said first surface of said substrate; and
a second bottom terminal (231, fig2, [18]) disposed on said second surface of said substrate; and
a conductive connecting track coupled to said first bottom terminal and to said second bottom terminal (fig2 and 4); and
said first defect sensor structure configured to receive a detection signal therethrough between the first top terminal and the second top terminal to detect a break in the conductive track between said first and second top terminals and thereby detect a defect in the substrate (fig2, 4 and 5, [31]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai in view of Marimuthu and Dennison to form at least two sets of via chains one set around center hole 140 and another set around outer edge as in Dennsion. The motivation to do so is to detect cracks formed in the interposer layer and improve process yield (Dennison, [2]).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812