Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 01/27/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 7-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tachi, US 2023/0253471.
Tachi shows the invention as claimed including a structure comprising:
A semiconductor substrate 12/14 (see fig. 1 and paragraph 0022);
A gate structure 22,24 on the semiconductor substrate (see paragraphs 0028-0030);
A gate metal 24 connected to the gate structure (see paragraph 0031); and
A field plate 28B connected to a source region of the gate structure (see paragraph 0033);
Wherein the gate metal and the field plate comprise a same material (see paragraphs 0031-0032).
Regarding claim 2, note that Tachi discloses the same material comprises TiN (see paragraphs 0031-0032).
With respect to dependent claim 7, note that the gate structure comprises p-doped GaN (see paragraph 0030).
Concerning dependent claim 8, note that the substrate of Tachi can comprise a GaN stack (see paragraph 0016).
Claim(s) 1-2, 4-6, 8-15, and 17-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Renesas Electronics Corp., JP 2015-050335 (translation provided by applicant).
Renesas Electronics Corp. shows the invention as claimed including a structure comprising:
A semiconductor substrate (see paragraph 0018-0019);
A gate structure GI/GE on the semiconductor substrate (see paragraphs 0021-0023);
A gate metal GE connected to the gate structure (see paragraph 0023); and
A field plate FP1 connected to a source region of the gate structure, wherein the gate metal and field plate comprise a same material (see paragraph 0024 of translation).
Concerning dependent claims 2 and 13, note that Renesas Electronics Corp. discloses where the same material is titanium nitride (see paragraph 0024 of translation).
With respect to dependent claim 4, note that Renesas discloses an airgap between the field plate and the gate metal (see paragraph 0048 of translation).
Concerning dependent claims 5 and 14, note that in Renesas the airgap is encapsulated by interlevel dielectric material.
As to dependent claims 6 and 15, note that at least a portion of the interlevel dielectric material is over at least a portion of the field gate and gate metal (see fig. 12, for example).
Regarding dependent claim 8, note that Renesas discloses where the semiconductor substrate comprises a GaN stack (see, for example, paragraph 0004 disclosing AlGaN/GaN HEMTs).
With respect to dependent claims 9-10 and 17, note that the field plate and gate metal are co-planar with the same thickness.
As to dependent claims 11 and 18 and the airgap being self-aligned to the field plate, note that it appears the air gap is aligned to the field plate. This notwithstanding, such limitation is a process limitation and is not given patentable weight in product claims.
As to independent claim 12, Renessas Electronics Corp. shows the invention as claimed including a structure comprising:
A semiconductor substrate (see paragraph 0018-0019 of translation);
A gate structure GI/GE on the semiconductor substrate (see paragraphs 0021-0023 of translation);
A gate metal GE connecting to the gate structure (see paragraph 0023 of translation); and a
A field plate FP1 adjacent to and coplanar with the gate metal (see paragraph 0024 of translation and figs. 1-12).
Additionally, regarding dependent claim 19, note that the field plate FP1 connects to a source region of the gate structure (also see independent claim 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tachi, US 2023/0253471 or Renesas Electronics Corp., JP 2015-050335 in view of Suzhou Yingjiatong Semiconductor Co. CN 111916449A (translation provided).
Tachi and Renesas Electronics Corp. are applied as above but do not expressly disclose the use of TiN/Al/TiN metal materials for the gate electrode, for example. Suzhou discloses the use of TiN/Al/TiN gate electrode materials (see paragraph 0039 of translation). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Tachi or Renesas so as to comprise TiN/Al/TiN gate electrode materials because Suzhou shows that this particular series of gate electrode materials are commonly used in GaN based devices.
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Renesas Electronics Corp., JP 2015-050335 in view of Tachi, US 2023/0253471.
Renesas Electronics Corp. is applied as above but does not expressly disclose wherein the gate structure comprises p-doped GaN. Tachi discloses where the gate structure of a HEMT comprises p-doped GaN (see, for example, paragraph 0030). In view of this disclosure, it would have been obvious ton one of ordinary skill in the art at the time the invention was filed to modify the device of Renesas Electronics Corp. so as to form the gate electrode of the claimed gallium nitride material because Tachi shows this is a material that is suitable for use in high electron mobility transistors.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chou et al., US 2020/0373420 discloses an HEMT including field plates (see paragraph 0003) and Tsai et al., US 2017/0133496 discloses a field plate formed adjacent a gate electrode (see abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
February 6, 2026