DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/10/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Invention I, and Claims 1-16 in the reply filed on 04/28/2026 is acknowledged. Claims 17 - 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/28/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantially” in claims 4 and 5 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The “thickness” and “material” of the insulation pattern and the insulating layer has been rendered indefinite by the use of the term appearing in “substantially”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 7, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (JP2012027469A; hereinafter Kwon) in view of Seo et al. (KR101996656B1; hereinafter Seo).
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Kwon: FIG. 7
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Seo: FIGS. 4 & 5
Regarding Claim 1, Kwon discloses a display panel manufacturing method (liquid crystal display panel repair device and method, [0001]) comprising:
detecting a machining target area (predetermined region K including defect occurrence region Q) of a bottom layer (gate electrode pattern 12), FIGS. 1, 7A reproduced above, [0034], [0045].
removing an area (source/drain electrode pattern), overlapping the machining target area (defect occurrence region Q of predetermined region K), of a top layer (source/drain electrode pattern 15) disposed on the bottom layer (gate electrode pattern 12), FIG. 7, [0045];
removing an area, overlapping the machining target area, of an insulation layer disposed on the bottom layer (removing insulating film pattern 13 disposed on gate electrode pattern 12 which overlaps the repair region K with defect Q), FIG. 7B, [0045];
forming an insulation pattern (repair pattern R2) in the removed area of the insulation layer (gate insulator pattern 13), FIG. 7D, [0048]; and
forming a compensation pattern (repair pattern R3) in the removed area of the top layer (source/drain electrode 15), FIG. 7E, [0049],
wherein the bottom layer comprises a semiconductor material or a conductive material (gate electrode 12 is a metal, [0035]), and the top layer comprises a conductive material (source/drain 15 is a conductive material, [0034]), FIG. 1.
Kwon discloses emitting a laser beam to the machining target area (repair region K with defect Q) of the bottom layer (gate electrode pattern 12) by using by offset printing method, FIG. 7A -7C, [0045], [0046], [0047], but does not disclose “a laser beam to form a bottom pattern.”
In a similar art, Seo discloses a display device and a repair method thereof [0001].
Seo [0043], [0045] discloses after the liquid crystal panel is formed, whether or not the wiring formed on the liquid crystal panel is disconnected is detected to detect a defect occurrence region DFA.
Seo discloses: detecting a machining target area (DFA) of a bottom layer (data lines 107a, 107b), FIG. 3, [0046].
emitting a laser beam (L1) to the machining target area (DFA) of the bottom layer (107a and 107b) to form a bottom pattern (metal thin film 107c formed using laser CVD to reconnect 107a and 107b) from the machining target area (DFA), FIGS. 4 & 5 reproduced above, [0048], [0049], [0050];
Seo discloses that a method as taught detects and repairs defects in the defect occurrence region using a known technique to improve similar methods in the same way [0009]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kwon’s method in order to detect and repair defects using a known technique to improve similar methods in the same way as disclosed by Seo [0009].
Regarding Claim 4, The combination of Kwon and Seo discloses the display panel manufacturing method according to claim 1.
Kwon discloses: wherein the insulation pattern (R2) has a substantially same thickness as that of the insulation layer (13), FIG. 1, [0045], [0048], [0050].
Kwon [0045] discloses insulating film 13 is removed and [0048] discloses the repair pattern R2 of the removed insulating film pattern is patterned and [0050] discloses the defective area of the first substrate 10 can be repaired to a normal area. It would be obvious for the insulation pattern R2 to have the substantially same thickness as that of the insulation layer 13.
Regarding Claim 5, The combination of Kwon and Seo discloses the display panel manufacturing method according to claim 4.
Kwon discloses: wherein the insulation pattern (R2) comprises a substantially same material as that of the insulation layer (13), .
Kwon [0045] discloses insulating film 13 is removed and [0048] discloses the repair pattern R2 of the removed insulating film pattern is patterned and [0050] discloses the defective are of the first substrate 10 can be repaired to a normal area. It would be obvious for the insulation pattern R2 to have the same material as that of the insulation layer 13.
Regarding Claim 7, The combination of Kwon and Seo discloses the display panel manufacturing method according to claim 1.
Kwon does not disclose “wherein the compensation pattern constitutes a portion of a scan line.”
Seo [0024] discloses the gate driver sequentially generates a gate signal and supplies the gate signal to the display panel, indicating the gate line functions as a scan line. Seo [0084] discloses the method of repairing a broken wire in a defect occurrence region can be used in various regions such as a gate line region. This indicates the conductive thin film 123c [0056] may constitute a portion of a scan line.
Seo discloses: wherein the compensation pattern (123c) constitutes a portion of a scan line (gate line), FIG. 8, [0024], [0056], [0084].
Seo discloses that a method as taught enables repair of defects in the scan lines of the display panel [0084]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kwon’s method in order to repair defects in the scan line as disclosed by Seo [0084].
Regarding Claim 8, The combination of Kwon and Seo discloses the display panel manufacturing method according to claim 7.
The combination of Kwon and Seo does not disclose “wherein a line-width of the scan line is about 3 μm or smaller.”
However, applicant is advised that, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only ordinary skill in the art. In re Aller, 105 USPQ 233. In the instant case the prior art method would not perform differently if modified to the claimed range. Therefore, the claimed limitation is considered met.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view Seo, further in view of Son et al. (US20210091163A1; hereinafter Son).
Regarding Claim 2, The combination of Kwon and Seo discloses the display panel manufacturing method according to claim 1.
The combination of Kwon and Seo does not disclose “wherein the bottom layer comprises the semiconductor material, the bottom pattern comprises a channel area of a transistor, and the compensation pattern comprises a control electrode of the transistor.”
In a similar art, Son discloses a method of manufacturing a display device with improved process efficiency [0007].
Son discloses: wherein the bottom layer comprises the semiconductor material (semiconductor layer 1200 may include the first and second semiconductor patterns 1210 and 1220) FIG. 7, [0155].
the bottom pattern comprises a channel area of a transistor (part of the extension of the first semiconductor pattern 1210 that may connect the first and second
conductive regions 1210a and 1210b may be the channel region of the driving transistor DTR), FIG. 7, [0160] and
the compensation pattern comprises a control electrode of the transistor (second conductive layer 1300 including gate electrode 1335 of driving transistor), FIG. 7, [0169].
Son discloses that a method including a transistor structure as taught improves process efficiency [0007], [0030]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kwon and Seo’s method in order to improve process efficiency as disclosed by Seo [0007], [0030].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view Seo, further in view of Adachi et al. (US20120298973A1; hereinafter Adachi).
Regarding Claim 6, The combination of Kwon and Seo discloses the display panel manufacturing method according to claim 1.
The combination of Kwon and Seo does not disclose “wherein the compensation pattern comprises a material having a higher electrical conductivity than the top layer.”
In a similar art, Adachi discloses a method of manufacturing a light-emitting device [0001].
Adachi discloses the connection electrode layer 111 is preferably formed using a material having higher conductivity than a conductive material for the upper electrode layer 107, FIG. 4, [0059].
Kwon [0049] discloses the source/drain electrode pattern 15 is removed within the predetermined region K and is subsequently repaired by forming the compensation pattern R3. Repair pattern R3 reconnects to the source/drain electrode pattern 15. Adachi [0059] discloses the connection electrode layer having a higher conductive material that the upper electrode layer, indicating in the repair pattern R3 may have a higher electrical conductivity that the source/drain pattern 15 in Kwon’s method.
The combination of Kwon, Seo, and Adachi discloses: wherein the compensation pattern (Kwon: R3) comprises a material having a higher electrical conductivity than the top layer (Kwon: source/drain electrode pattern 15), Adachi: [0059].
Adachi discloses that a method as taught improves electrical performance of the device [0059]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kwon and Seo’s method in order to improve electrical performance of the display device as disclosed by Adachi [0059].
Claims 3, 9 - 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Seo, further in view of Isa et al. (US20100099217A1; hereinafter Isa).
Regarding Claim 3, The combination of Kwon and Seo discloses the display panel manufacturing method according to claim 1.
The combination of Kwon and Seo does not disclose “wherein the bottom pattern has a curved shape in a plan view.”
In a similar art, Isa discloses a semiconductor device, an electronic device, and a method of manufacturing a semiconductor device by using a printing method [0002].
Isa [0169] discloses a pixel electrode layer 211 is formed by processing a conductive film using a droplet discharge method and has a shape having a curvature at the periphery, indicating the bottom pattern may have a curved shape in the plan view.
Isa discloses that a method as taught enables formation of a conductive pattern having a desired shape [0169]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kwon and Seo’s method in order to enable formation of a conductive pattern of a desired shape as disclosed by Isa [0169].
Regarding Claim 9, The combination of Kwon and Seo discloses the display panel manufacturing method according to claim 1.
Kwon does not explicitly disclose “wherein the forming of the insulation pattern comprises: providing an insulation ink to the removed area of the insulation layer; and curing the insulation ink.”
Seo discloses: wherein the forming of the insulation pattern (106c) comprises:
providing an insulation ink (insulation material) to the removed area of the insulation layer (106a and 106b), [0052].
Seo does not explicitly disclose “curing the insulation ink.”
Isa discloses: curing the insulation ink (the insulating layer is formed by solidifying a liquid composition containing an insulative material and by drying or baking after discharging), [0010].
Isa discloses that a method as taught enables formation of a stable insulation pattern [0008]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Kwon and Seo’s method in order to form a stable insulation pattern in the display panel as disclosed by Isa [0008].
Regarding Claim 10, The combination of Kwon, Seo, and Isa discloses the display panel manufacturing method according to claim 9.
Kwon does not disclose “wherein the insulation ink is provided from an electrohydrodynamic insulation ink nozzle.”
Seo discloses: wherein the insulation ink (insulation material) is provided from an electrohydrodynamic insulation ink nozzle, [0052], [0054], [0056].
Seo discloses forming the insulation material 106c may be formed by an inkjet process to recover the removed portions of insulating films 106a and 106b, [0052]. Seo [0054], [0056] discloses the nano ink is provided using EHD (Electrohydrodynamic) nano inkjet to form a conductive thin film. Therefore, it would be obvious to provide the insulation material also from an electrohydrodynamic insulation ink nozzle.
Seo discloses that a method as taught providing ink from an EHD nozzle enables fine patterning of the layers [0054]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable fine patterning of the layers as disclosed by Seo [0054].
Regarding Claim 11, The combination of Kwon, Seo, and Isa discloses the display panel manufacturing method according to claim 10.
The combination of Kwon and Seo does not disclose “wherein the electrohydrodynamic insulation ink nozzle is spaced apart from the insulation layer by about 5 μm or greater.”
Isa [0010] discloses the insulating layer is formed by solidifying a liquid composition containing an insulative material and by drying or baking after discharging.
Isa [0065] discloses the formation position may be determined based on a marker
1411 that is formed over a substrate 1400. Isa [0083] discloses it is preferable that the distance between an object to be processed and the discharge opening of the nozzle is as short as possible in order to drop a droplet on a desired position with a preferable distance set within the approximate range of 0.1 mm to 3 mm (100μm to 3000μm). Therefore, the nozzle is spaced apart from the insulation layer (which is formed on the substrate) by about 5μm or greater.
Isa discloses: wherein the electrohydrodynamic insulation ink nozzle is spaced apart from the insulation layer by about 5 μm or greater, (100μm to 3000μm, [0065], [0083]).
Isa discloses that a method as taught enables the insulation ink to be discharged at a desired position [0083]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable the insulation ink to be discharged at a desired position as disclosed by Isa [0083].
Regarding Claim 12, The combination of Kwon, Seo, and Isa disclose the display panel manufacturing method according to claim 9.
Kwon does not disclose “wherein the insulation ink comprises silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.”
Seo discloses forming the insulating material 106c to recover the insulating films 106a and 106b, [0052]. Seo [0036] discloses first insulating layer 106 may be silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof, but is not limited thereto. Therefore, the insulation ink may comprise silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
Seo discloses: wherein the insulation ink (insulating material 106c) comprises silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, [0036].
Seo discloses that a method as taught enables formation of insulation layers comprised of known insulating materials having desired insulating properties [0036]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to form insulation layers comprised of known insolating materials having desired insulating properties as disclosed by Seo [0036].
Regarding Claim 13, The combination of Kwon and Seo discloses the display panel manufacturing method according to claim 1.
Kwon discloses formation of compensation pattern (R3) in the removed area of the top layer (15), but does not explicitly disclose “providing a metal ink to the removed area of the top layer; and curing the metal ink.”
Seo discloses: wherein the forming of the compensation pattern (123c) comprises: providing a metal ink (nano ink) to the removed area of the top layer (109a and 109b), [0056]; and
Seo does not explicitly disclose “curing the metal ink.”
Isa discloses: curing the metal ink (drying and baking), [0067], [0089].
Seo discloses that a method as taught enables formation of the compensation pattern using a known technique to improve similar methods in the same way [0056]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable formation of the compensation pattern using a known technique to improve similar methods in the same way as disclosed by Seo [0056].
Regarding Claim 14, The combination of Kwon, Seo, and Isa discloses the display panel manufacturing method according to claim 13.
Kwon does not disclose “wherein the metal ink is provided from an electrohydrodynamic metal ink nozzle.”
Seo discloses: wherein the metal ink (nano ink) is provided from an electrohydrodynamic metal ink nozzle, [0054], [0056].
Seo [0054], [0056] discloses the nano ink is provided using EHD (Electrohydrodynamic) nano inkjet to form a conductive thin film 123c.
Seo discloses that a method as taught providing ink from an EHD nozzle enables fine patterning of the layers [0054]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable fine patterning of the layers as disclosed by Seo [0054].
Regarding Claim 15, The combination of Kwon, Seo, and Isa discloses the display panel manufacturing method according to claim 14.
The combination of Kwon and Seo does not disclose “wherein the electrohydrodynamic metal ink nozzle is spaced apart from the top layer by about 5 μm or greater.”
Isa [0065] discloses the formation position may be determined based on a marker 1411 that is formed over a substrate 1400. Isa [0083] discloses it is preferable that the distance between an object to be processed and the discharge opening of the nozzle is as short as possible in order to drop a droplet on a desired position with a preferable distance set within the approximate range of 0.1 mm to 3 mm (100μm to 3000μm). Therefore, the nozzle is spaced apart from the top layer (which is formed on the substrate) by about 5μm or greater.
Isa discloses: wherein the electrohydrodynamic metal ink nozzle is spaced apart from the top layer by about 5 μm or greater (100μm to 3000μm, [0065], [0083]).
Isa discloses that a method as taught enables the metal ink to be discharged at a desired position [0083]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to enable the metal ink to be discharged at a desired position as disclosed by Isa [0083].
Regarding Claim 16, The combination of Kwon, Seo, and Isa discloses the display panel manufacturing method according to claim 13.
The combination of Kwon and Seo does not disclose “wherein the metal ink comprises silver.”
Isa discloses: wherein the metal ink comprises silver, [0084].
Isa [0084] discloses it is preferable to use conductive material formed of silver or copper, indicating the metal ink may comprise silver.
Isa discloses that a method as taught with the metal ink comprising silver lowers resistance and improves conductivity of the conductive layers [0084]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to lower resistance and improve conductivity of the conductive layers as disclosed by Isa [0084].
Conclusion
Any inquiry concerning this communication or earlier communications from the
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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