DETAILED ACTION
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Election/Restrictions
Applicant’s election without traverse of Invention I (semiconductor device), reflected in claims 1-10 in the reply filed on 03/27/2026 is acknowledged. Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142 (b), as being drawn to the nonelected group.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore elements, ‘the pad oxide layer’ cited in claim 2, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
The claimed device is the finished product shown in applicant’s fig. 10 and it doesn’t include the pad oxide layer. During the manufacturing, part of the pad oxide layer (element 210 in fig. 4-5) is removed and the rest (110a in fig. 5) is converted to thermal oxide layer (142 in fig. 6). Thus, at the end of the manufacturing process in fig. 10, the pad oxide layer doesn’t exist.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20190157421 A1, hereinafter Wang‘421) in view of Su et al. (US 20200006152 A1, hereinafter Su‘152).
Regarding independent claim 1, Wang‘421 teaches, “A semiconductor device (fig. 1-10; ¶ [0012] - ¶ [0030]), comprising:
a substrate (110, fig. 10) having a first region (B) and a second region (A);
a first oxide layer (120b, 122b) disposed on the first region (B), wherein the first oxide layer comprises a first thermal oxide layer (120b, ‘a thermal oxide process’, ¶ [0015]) and a first deposited oxide layer (122b, ¶ [0016]), and a portion of the first thermal oxide layer is formed by a pad oxide layer; and
a second oxide layer (120a, 120b) disposed on the second region (A), wherein the second oxide layer comprises a second thermal oxide layer (120a, ‘a thermal oxide process’, ¶ [0015]) and a second deposited oxide layer (122a, ¶ [0016])”.
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The limitations, ‘thermal oxide’, ‘deposited oxide’, ‘oxide layer is formed by a pad oxide layer’ are directed towards the process of making an oxide by thermal process, an oxide by deposition process and a thermal oxide layer formed by a pad oxide layer respectively. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "thermal oxide", ‘deposited oxide’, ‘formed by a pad oxide layer’ only requires an oxide layer in the claimed semiconductor device, which does not distinguish the invention from Wang‘421, who teaches the structure as claimed.
In above rejection, the claimed elements ‘first deposited oxide layer’, and ‘second deposited oxide layer’ are mapped to elements 122b and 122a respectively which are defined by Wang‘421 as “dielectric layer having a high dielectric constant” (¶ [0016]). Wang‘421 may not be explicitly mentioning the high dielectric constant layer 122 (122b and 122a) is an oxide layer.
However, Su‘152 teaches examples of dielectric layer having a high dielectric constant are oxides e.g., Hafnium Oxide, Zirconium Oxide, Aluminum Oxide etc (¶ [0023]).
Wang‘421 and Su‘152 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang‘421 with the features of Su‘152 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Wang‘421 and Su‘152 to use oxides as high dielectric constant layer according to the teachings of Su‘152 as these are conventional choices in the related semiconductor field.
Regarding claim 2, Wang‘421 modified by Su‘152 further teaches, “The semiconductor device of claim 1, wherein the pad oxide layer, the first thermal oxide layer (120b, Wang‘421) and the second thermal oxide layer (120a) comprise a same material”.
Regarding claim 3, Wang‘421 modified by Su‘152 further teaches, “The semiconductor device of claim 1, further comprising: a first gate (M2, Wang‘421) disposed on the first oxide layer (120b, 122b); and a second gate (M1) disposed on the second oxide layer (120a, 122a)”.
Regarding claim 4, Wang‘421 modified by Su‘152 further teaches, “The semiconductor device of claim 3, further comprising: a first spacer (150b, fig. 9, Wang‘421) surrounding the first gate (M2) and disposed on the first oxide layer (120b, 122b); and a second spacer (150a) surrounding the second gate (M1) and disposed on the second oxide layer (120a, 122a)”.
Regarding claim 6, Wang‘421 modified by Su‘152 further teaches, “The semiconductor device of claim 1, wherein a thickness of the first deposited oxide layer (122b, fig. 10, Wang‘421) is equal to a thickness of the second deposited oxide layer (122a)”.
Regarding claim 7, Wang‘421 modified by Su‘152 further teaches, “The semiconductor device of claim 1, wherein a thickness of the first thermal oxide layer (120a, fig. 10, Wang‘421) is greater than a thickness of the second thermal oxide layer (120b)”.
Regarding claim 8, Wang‘421 modified by Su‘152 further teaches, “The semiconductor device of claim 1, wherein a thickness of the first oxide layer (120b, 122b, fig. 10, Wang‘421) is greater than a thickness of the second oxide layer (120a, 122a)”.
Regarding claim 9, Wang‘421 modified by Su‘152 further teaches, “The semiconductor device of claim 1, wherein in the first oxide layer (120b, 122b, fig. 10, Wang‘421), a thickness of the first thermal oxide layer (120b) is greater than a thickness of the first deposited oxide layer (122b)”.
Regarding claim 10, Wang‘421 modified by Su‘152 further teaches, “The semiconductor device of claim 1, wherein in the second oxide layer, a thickness of the second thermal oxide layer is greater than a thickness of the second deposited oxide layer (mapping region A and B in fig.10 as first region and second region in claim 1)”.
Claims 1 and 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Su‘152.
Regarding independent claim 1, Su‘152 teaches, “A semiconductor device (fig. 1-3; ¶ [0014] - ¶ [0043]), comprising:
a substrate (110, fig. 2A) having a first region (106) and a second region (108);
a first oxide layer disposed on the first region, wherein the first oxide layer
comprises a first thermal oxide layer (136b, silicon oxide, ¶ [0023]) and a first deposited oxide layer (138b, see annotation, silicon oxide, ¶ [0023]), and a portion of the first thermal oxide layer is formed by a pad oxide layer; and
a second oxide layer disposed on the second region (108), wherein the second oxide layer comprises a second thermal oxide layer (136c, silicon oxide, ¶ [0023]) and a second deposited oxide layer (138c, see annotation, silicon oxide)”.
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The limitations, ‘thermal oxide’, ‘deposited oxide’, ‘oxide layer is formed by a pad oxide layer’ are directed towards the process of making an oxide by thermal process, an oxide by deposition process and a thermal oxide layer formed by a pad oxide layer respectively. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "thermal oxide", ‘deposited oxide’, ‘formed by a pad oxide layer’ only requires an oxide layer in the claimed semiconductor device, which does not distinguish the invention from Su‘152, who teaches the structure as claimed.
Regarding claim 3, Su‘152 further teaches, “The semiconductor device of claim 1, further comprising: a first gate (140b, fig. 2A) disposed on the first oxide layer; and a second gate (140c) disposed on the second oxide layer”.
Regarding claim 4, Su‘152 further teaches, “The semiconductor device of claim 3, further comprising: a first spacer (see annotated fig. 2A) surrounding the first gate (140b) and disposed on the first oxide layer; and a second spacer (see annotated fig. 2A) surrounding the second gate (140c) and disposed on the second oxide layer”.
Regarding claim 5, Su‘152 further teaches, “The semiconductor device of claim 4, wherein an outer side surface of the first spacer (see annotated fig. 2A) is aligned with a side surface of the first oxide layer (136b, annotated first deposited oxide layer), and an outer side surface of the second spacer (see annotated fig. 2A) is aligned with a side surface of the second oxide layer (136b, annotated first deposited oxide layer),”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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