DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Election of claims 1-8 for continued examination was made without traverse in the reply filed on February 17, 2026. Claims 9-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented in bold if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 and/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 8 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, in claim 8, applicant recites: “a first contact hole connecting the third electrode to the first semiconductor portion is provided in the first insulating film and the third insulating film at a position overlapping the first semiconductor portion and the fourth electrode”. Examiner is interpreting said first contact hole to correspond to element 15CH1 in fig. 6 of the present disclosure, said third electrode to correspond to element 15B in the same fig. 6, said first semiconductor portion to correspond to element 15D in the same fig. 6, said first insulating film to correspond to element 30 in the same fig. 6, and said third insulating film to correspond to element 33 in the same fig. 6. All of these elements are included in the first thin film transistor 15 within the non-display region NAA (fig. 6). However, said fourth electrode is believed to correspond to element 27B in the second thin film transistor 27 within the display region AA (fig. 6). Therefore, how can the claimed first contact hole connect the recited elements at a position overlapping the first semiconductor portion and the fourth electrode given that the first semiconductor portion occurs in the non-display region NAA (fig. 6) and the fourth electrode occurs in the display region AA (fig. 6)? For the purpose of continued examination, the examiner will interpret the claim limitation such that the first contact hole overlaps the first semiconductor portion and the third electrode (similar to present claim 1): “a first contact hole connecting the third electrode to the first semiconductor portion is provided in the first insulating film and the third insulating film at a position overlapping the first semiconductor portion and the third electrode”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Suzumura et al. (US 20210109412 A1), hereinafter referred to as “Suzumura”, in view of Yamazaki (US 20170025548 A1), hereinafter referred to as “Yamazaki”.
Regarding claim 1, Suzumura discloses a display device (Suzumura fig. 4; see [0045]) comprising:
a first semiconductor portion (Suzumura fig. 4, SC2; see [0048]) comprising a first semiconductor film (see Suzumura [0048]: semiconductor layer SC2 is formed from a polysilicon (polycrystalline silicon) film);
a first insulating film (Suzumura fig. 4, 12; see [0050]) disposed on an upper-layer side of the first semiconductor film (see Suzumura fig. 4);
a first electrode (Suzumura fig. 4, GE2; see [0051]-[0052]) comprising a first part of a first conductive film (see Suzumura [0051]-[0052]; gate electrode GE2 is formed of a titanium/aluminum bi-layer conductive film) disposed on an upper-layer side of the first insulating film (see Suzumura fig. 4), and the first electrode being disposed to overlap a part of the first semiconductor portion (see Suzumura fig. 4);
a second electrode (Suzumura fig. 4, G; see [0051]-[0052]) comprising a second part of the first conductive film (see Suzumura [0051]-[0052]; gate line G, like gate electrode GE2, is formed of a titanium/aluminum bi-layer conductive film), the second part of the first conductive film being different from the first part of the first conductive film corresponding to the first electrode (see Suzumura fig. 4 and [0051]-[0052]; gate line G and gate electrode GE2 are composed of the same conductive film yet located in different regions (the gate line G in the display area DA and the gate electrode GE2 in the non-display area NDA));
an insulating film (Suzumura fig. 4, 13; see [0054]) disposed on an upper-layer side of the first conductive film (see Suzumura fig. 4);
a second semiconductor portion (Suzumura fig. 4, SC1; see [0055]) comprising a second semiconductor film (see Suzumuta [0055]: semiconductor layer SC1 is formed of an oxide semiconductor film) disposed on an upper-layer side of the insulating film (see Suzumura fig. 4), the second semiconductor portion including an overlapping part disposed to overlap the second electrode (see Suzumura fig. 4: semiconductor layer SC1 overlaps gate line G);
a third insulating film (Suzumura fig. 4, 15; see [0064]) disposed on an upper-layer side of the second semiconductor film (see Suzumura fig. 4);
a third electrode (Suzumura fig. 4, UC2; see [0065] and [0068]) comprising a first part of a second conductive film (see Suzumura [0068]; upper contact electrode UC2 is formed of a titanium/aluminum/titanium tri-layer conductive film) disposed on an upper-layer side of the third insulating film (see Suzumura fig. 4), the third electrode being disposed at a position overlapping the first semiconductor portion, and not overlapping the first electrode (See Suzumura fig. 4: upper contact electrode UC2 overlaps semiconductor layer SC2 but does not overlap gate electrode GE2);
and a fourth electrode (Suzumura fig. 4, S; see [0066] and [0068]) comprising a second part of the second conductive film (see Suzumura [0068]; source line S, like upper contact electrode UC2, is formed of a titanium/aluminum/titanium tri-layer conductive film), the second part of the second conductive film being different from the first part of the second conductive film corresponding to the third electrode (see Suzumura fig. 4 and [0068]; source line S and upper contact electrode UC2 are composed of the same conductive film yet located in different regions (the source line S in the display area DA and the upper contact electrode UC2 in the non-display area NDA)), the fourth electrode being disposed to overlap a part of the second semiconductor portion (see Suzumura fig. 4), wherein:
a first contact hole (Suzumura fig. 4: h3, BC2, and h6; see [0061] and [0067]) connecting the third electrode to the first semiconductor portion (see Suzumura fig. 4, [0061], and [0067]: the upper contact electrode UC2 is connected to the fourth region R4 of semiconductor layer SC2 via a contact hole comprising contact hole h3, lower contact electrode BC2, and contact hole h6) is provided in the first insulating film and the third insulating film at a position overlapping the first semiconductor portion and the third electrode (see Suzumura fig. 4),
and a second contact hole (Suzumura fig. 4, h4; see [0066]) connecting the fourth electrode to the second semiconductor portion (see [0066]: contact hole h4 connects the source line S with the semiconductor layer SC2) is provided in the third insulating film at a position overlapping the second semiconductor portion and the fourth electrode (see Suzumura fig. 4).
Suzumura fails to disclose wherein a second insulating film is further disposed to overlap at least the second semiconductor portion, and is not formed in a range overlapping the first semiconductor portion.
Yamazaki discloses a thin film transistor (TFT) device (Yamazaki fig. 1B; see [0092] and <Transistor Structure 1>) that can be used in a liquid crystal display device (see Yamazaki fig. 39B and c.f. fig. 1B: note that transistor 751 is similar to the transistor disclosed in fig. 1B; see [0414]), wherein the TFT has a double gate structure (see Yamazaki fig. 1B: conductor 404 functions as a first gate electrode ([0094]) and conductor 310 functions as a second gate electrode ([0106])) and a lower gate insulating layer (Yamazaki fig. 1B, 406a; see [0124]) disposed directly below and overlapping an active semiconductor layer (Yamazaki fig. 1B, 406b; see [0123]).
The lower gate insulating layer of Yamazaki is incorporated into the display device of Suzumura directly below the second semiconductor portion and overlapping the second electrode. The combination, thus, discloses wherein a second insulating film is further disposed to overlap at least the second semiconductor portion, and is not formed in a range overlapping the first semiconductor portion.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of Suzumura with the second insulating film of Yamazaki to better protect the second semiconductor portion against a potential gate insulator tunneling current between said second semiconductor portion and the second electrode (i.e. lower gate) during device operation.
Regarding claim 2, Suzumura and Yamazaki disclose the display device according to claim 1, further comprising:
a fourth insulating film (Suzumura fig. 4, 14; see [0058]) disposed on the upper-layer side of the second semiconductor film (Suzumura fig. 4, SC1; see [0055]), and on a lower-layer side of the third insulating film (Suzumura fig. 4, 15; see [0064]);
and a fifth electrode (Suzumura fig. 4, GE1; note that there are two instances of GE1 in the cross-sectional view shown in fig. 4: one instance is overlapping SC1 and the other instance is located to the right on the page; examiner takes the instance of GE1 that overlaps SC1 as the claimed fifth electrode; see fig. 5 (described in [0111]-[0113]) for a top view of the relevant structures that shows how the relevant elements of fig. 4 interrelate three-dimensionally: it should be noted that both instances of GE1 in fig. 4 are electrically connected and part of the same three-dimensional whole) comprising a third conductive film (see Suzumura [0062]: gate electrode GE1 is formed of a titanium/aluminum/titanium tri-layer conductive film) disposed on an upper-layer side of the fourth insulating film (see Suzumura fig. 4) and on a lower-layer side of the third insulating film (see Suzumura fig. 4), the fifth electrode being disposed to overlap a different part of the second semiconductor portion than the part overlapped by fourth electrode (Suzumura fig. 4, S; gate electrode GE1 overlaps a different portion of SC1 than the part overlapped by source line S),
wherein the fifth electrode is connected to the second electrode (see Suzumura fig. 4 and [0059]: GE1 is brought into contact with G through contact hole h1).
Regarding claim 3, Suzumura and Yamazaki disclose the display device according to claim 2,
wherein the fourth insulating film (Suzumura fig. 4, 14; see [0058]) is further disposed to overlap at least each of the first semiconductor portion and the second semiconductor portion (see Suzumura fig. 4),
and a part of the first contact hole (Suzumura fig. 4: h3, BC2, and h6; see [0061] and [0067]) and a part of the second contact hole (Suzumura fig. 4, h4; see [0066]) are provided in the fourth insulating film (see Suzumura fig. 4).
Regarding claim 4, Suzumura and Yamazaki disclose the display device according to claim 2,
wherein the fourth insulating film (Suzumura fig. 4, 14; see [0058]) is further disposed to overlap the fifth electrode (Suzumura fig. 4, GE1) or the second semiconductor portion (Suzumura fig. 4, SC1 insulating layer 14 overlaps both gate electrode GE1 and semiconductor layer SC1).
Regarding claim 5, Suzumura and Yamazaki disclose the display device according to claim 4,
wherein the fourth insulating film (Suzumura fig. 4, 14) is further disposed to overlap the fifth electrode (Suzumura fig. 4, GE1).
Regarding claim 6, Suzumura and Yamazaki disclose the display device according to claim 4,
wherein the fourth insulating film (Suzumura fig. 4, 14) is further disposed to overlap the second semiconductor portion (Suzumura fig. 4, SC1),
and a part of the second contact hole (Suzumura fig. 4, h4; see [0066]) is provided in the fourth insulating film at a position overlapping the second semiconductor portion (see Suzumura fig. 4).
Regarding claim 7, Suzumura and Yamazaki disclose the display device according to claim 1, further comprising:
a pixel electrode (Suzumura fig. 3, SP; see [0036]);
a display region (Suzumura fig. 3, DA; see [0030] and note that both fig. 3 and fig. 4 depict portions of the LCD device of fig. 1), in which the pixel electrode is disposed and in which an image is displayed (see Suzumura fig. 3 and [0030]: images are displayed in the display area DA by way of pixels PX which comprise a plurality of sub-pixels SP1-3);
a fifth electrode (Suzumura fig. 4, CA1; see [0072]-[0073]) disposed in the display region, and connected to the pixel electrode (see Suzumura [0089] and [0098]: contact electrode CA1 is electrically connected to the pixel electrode PE through contact electrode CA2; see [0042]: pixel electrode PE is connected to sub-pixel SP);
a first wiring line (Suzumura fig. 3 (specifically the circuit diagram of SP), G; see [0038]) disposed in the display region (see Suzumura fig. 3);
a second wiring line (Suzumura fig. 3 (specifically the circuit diagram of SP), S; see [0038]) disposed in the display region (see Suzumura fig. 3);
and a circuit portion (Suzumura fig. 3, DR1; see [0038]) supplying a signal to at least one of the first wiring line and the second wiring line (see Suzumura [0038]: first driver DR1 functions as a gate line drive circuit to supply a signal to gate line G),
wherein: the first semiconductor film (Suzumura fig. 4, SC2; see [0048]) comprises a polysilicon semiconductor material (semiconductor layer SC2 comprises a polycrystalline silicon (i.e. polysilicon) material),
the second semiconductor film (Suzumura fig. 4, SC1; see [0055]) comprises an oxide semiconductor material (semiconductor layer SC1 comprises an oxide semiconductor material),
the first semiconductor portion (equivalent to the first semiconductor film), the first electrode (Suzumura fig. 4, GE2; see [0051]-[0052]), and the third electrode (Suzumura fig. 4, UC2; see [0065] and [0068]) are disposed in the circuit portion (see Suzumura fig. 4, [0038], and [0051]: SC2, GE2, and UC2 are included in switching element SW2 which is included in first driver DR1),
the second semiconductor portion (equivalent to the second semiconductor film), the second electrode (Suzumura fig. 4, G; see [0051]-[0052]), and the fourth electrode (Suzumura fig. 4, S; see [0066] and [0068]) are disposed in the display region (see Suzumura fig. 3 and [0042]; c.f. fig. 4; SC1, G, and S are included in SW1 which is disposed in display area DA),
the second electrode is connected to the first wiring line (see Suzumura [0042]: gate line G included in switching element SW1 in fig. 4 is the same as gate line G in the circuit diagram(s) of fig. 3),
the fourth electrode is connected to the second wiring line (see Suzumura [0042]: source line S included in switching element SW1 in fig. 4 is the same as source line S in the circuit diagram(s) of fig. 3),
and the fifth electrode is connected to the second semiconductor portion (see Suzumura fig. 4 and [0072]).
Regarding claim 8, Suzumura discloses a display device (Suzumura fig. 4; see [0045]) comprising:
a first semiconductor portion (Suzumura fig. 4, SC2; see [0048]) comprising a first semiconductor film (see Suzumura [0048]: semiconductor layer SC2 is formed from a polysilicon film);
a first insulating film (Suzumura fig. 4, 12; see [0050]) disposed on an upper-layer side of the first semiconductor film (see Suzumura fig. 4);
a first electrode (Suzumura fig. 4, GE2; see [0051]-[0052]) comprising a first conductive film (see Suzumura [0051]-[0052]; gate electrode GE2 is formed of a titanium/aluminum bi-layer conductive film; note that gate line G is also formed of the same conductive film) disposed on an upper-layer side of the first insulating film, and the first electrode being disposed to overlap a part of the first semiconductor portion (see Suzumura fig. 4);
an insulating film (Suzumura fig. 4, 13; see [0054]) disposed on an upper-layer side of the first conductive film (Suzumura fig. 4, G; note that the insulating film 13 is disposed on both gate line G and gate electrode GE2);
a second semiconductor portion (Suzumura fig. 4, SC1; see [0055]) comprising a second semiconductor film (see Suzumuta [0055]: semiconductor layer SC1 is formed of an oxide semiconductor film), and disposed on an upper-layer side of the insulating film (see Suzumura fig. 4);
a third insulating film (Suzumura fig. 4, 14; see [0058]) disposed on an upper-layer side of the second semiconductor film (see Suzumura fig. 4);
a second electrode (Suzumura fig. 4, GE1; see [0062]) comprising a second conductive film (see Suzumura [0062]: gate electrode GE1 is formed of a titanium/aluminum/titanium tri-layer conductive film) disposed on an upper-layer side of the third insulating film (see Suzumura fig. 4), the second electrode being disposed to overlap a part of the second semiconductor portion (see Suzumura fig. 4);
a fourth insulating film (Suzumura fig. 4, 15; see [0064]) disposed on an upper-layer side of the second conductive film (See Suzumura fig. 4);
a third electrode (Suzumura fig. 4, UC2; see [0065] and [0068]) comprising a first part of a third conductive film (see Suzumura [0068]; upper contact electrode UC2 is formed of a titanium/aluminum/titanium tri-layer conductive film), the third electrode being disposed on an upper-layer side of the fourth insulating film (see Suzumura fig. 4), the third electrode being disposed at a position overlapping the first semiconductor portion, and not overlapping the first electrode (See Suzumura fig. 4: upper contact electrode UC2 overlaps semiconductor layer SC2 but does not overlap gate electrode GE2);
and a fourth electrode (Suzumura fig. 4, S; see [0066] and [0068]) comprising a second part of the third conductive film (see Suzumura [0068]; source line S, like upper contact electrode UC2, is formed of a titanium/aluminum/titanium tri-layer conductive film), the second part of the third conductive film being different from the first part of the third conductive film corresponding to the third electrode (see Suzumura fig. 4 and [0068]; source line S and upper contact electrode UC2 are composed of the same conductive film yet located in different regions (the source line S in the display area DA and the upper contact electrode UC2 in the non-display area NDA)), the fourth electrode being disposed at a position overlapping the second semiconductor portion (see Suzumura fig. 4), and not overlapping the second electrode (see Suzumura fig. 4), wherein:
the third insulating film is further disposed to overlap at least the second electrode (see Suzumura fig. 4),
a first contact hole (Suzumura fig. 4: h3, BC2, and h6; see [0061] and [0067]) connecting the third electrode to the first semiconductor portion (see Suzumura fig. 4, [0061], and [0067]: the upper contact electrode UC2 is connected to the fourth region R4 of semiconductor layer SC2 via a contact hole comprising contact hole h3, lower contact electrode BC2, and contact hole h6) is provided in the first insulating film and the third insulating film at a position overlapping the first semiconductor portion and the third electrode (see Suzumura fig. 4; applicant is reminded of the 112(b) rejection entered above),
and a second contact hole (Suzumura fig. 4, h4; see [0066]) connecting the fourth electrode to the second semiconductor portion (see [0066]: contact hole h4 connects the source line S with the semiconductor layer SC2) is provided in the fourth insulating film at a position overlapping the second semiconductor portion and the fourth electrode (see Suzumura fig. 4).
Suzumura fails to disclose wherein the second insulating film is further disposed to overlap at least the second semiconductor portion, and is not formed in a range overlapping the first semiconductor portion.
Yamazaki discloses a thin film transistor (TFT) device (Yamazaki fig. 1B; see [0092] and <Transistor Structure 1>) that can be used in a liquid crystal display device (see Yamazaki fig. 39B and c.f. fig. 1B: note that transistor 751 is similar to the transistor disclosed in fig. 1B; see [0414]), wherein the TFT has a double gate structure (see Yamazaki fig. 1B: conductor 404 functions as first gate electrode ([0094]) and conductor 310 functions as a second gate electrode ([0106])) and a gate insulating layer (Yamazaki fig. 1B, 406a; see [0124]) disposed directly below and overlapping an active semiconductor layer (Yamazaki fig. 1B, 406b; see [0123]).
The gate insulating layer of Yamazaki is incorporated into the display device of Suzumura directly below the second semiconductor portion and substantially overlapping the second electrode. The combination, thus, discloses wherein a second insulating film is further disposed to overlap at least the second semiconductor portion, and is not formed in a range overlapping the first semiconductor portion.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of Suzumura with the second insulating film of Yamazaki to better protect the second semiconductor portion against potential mechanical stress (i.e. cracking) that could occur during or after device fabrication.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNER F COLLINS whose telephone number is (571)272-5187. The examiner can normally be reached M-F, 8am-5pm.
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/HAMNER FITZHUGH COLLINS IV/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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