DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 and/or 103 rejections are provided in parenthesis.
Response to Amendment
The amendment filed April 30th, 2026, has been entered. Claims 1-3, 5-9, 11-13, 15, and 18 are currently pending in this application. Claims 1-3, 6-9, 11-13, 15, and 18 have been amended in the presently filed amendments. Applicant’s amendments to the Drawings and Specification overcome most, but not all (see below) of the objections previously set forth in the Non-final Office Action mailed January 30th, 2026. Applicant’s amendments to the Claims overcome each and every claim objection and 112(b) rejection previously set forth in said Non-final Office Action.
Drawings
The Replacement Drawing Sheets received on April 30th, 2026, are objected to because, despite applicant’s attempt to correct the inconsistency, the replacement metal gate (118 and 218) remains imprecisely indicated in figs. 2C-2H and figs. 4F-4H. In figs. 2C-2D, reference number 118 seems to indicate the top portions of the disclosed gate stacks. In figs. 2E-2H, reference number 118 is used twice to indicate two seemingly different features (i.e. part of contact material 120 and the aforementioned top portions of a disclosed gate stacks). In figs. 2E-2H, high-k dielectric 111 is indicated as filling voids 105 (shown in fig. 2C) between the nanosheet channel layers 106. However, these foregoing depictions run contrary to how Examiner understands the device to operate. In paragraph [0059], it is disclosed that a conductive material is deposited over high-k dielectric 111 to form the replacement metal gate 118. In GAAFET devices, the electric current through nanosheet channels is controlled through the application of voltage to a metal gate that wraps around said channels with the metal gate being isolated from the channels by a dielectric (such as high-k dielectric 111). Is this what Applicant intends to disclose? If so, both the replacement metal gate (i.e. conductive material) and the high-k dielectric should be clearly depicted between the nanosheet channel layers 106 in all of the relevant figs. Similar issues exist concerning the depiction of replacement metal gate 218 and high-k dielectric 211 in fig. 4F-4H; these issues should be addressed in a similar manner as described above. If it would be helpful to further clarify the structure of the present invention and how it should be depicted, Examiner encourages Applicant to request an interview.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office Action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one fig. is being amended. The fig. or fig. number of an amended drawing should not be labeled as “amended.” If a drawing fig. is to be canceled, the appropriate fig. must be removed from the replacement sheet, and where necessary, the remaining fig.s must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: in paragraph [0085], all instances of “horizontal channel layers 204” should be relabeled as “horizontal channel layers 206”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 9, and 18 (and claims 2-3, 5-8, 11-13, and 15 through dependency) are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In claim 1, applicant recites “growing an epitaxial layer on the plurality of horizontal channel layers in the source trench and in the drain trench and forming a conformal layer of silicide on the epitaxial layer to form a source region and a drain region in the source trench and in the drain trench”. However, this language does not align with the disclosed invention. For instance, see instant fig. 2G-2H. A plurality of epitaxial layers are grown on each of the plurality of horizontal channel layers and a conformal layer of silicide is formed on the epitaxial layers (plural); see [0063]-[0064]. Therefore, the aforementioned claim limitation fails to particularly point out and distinctly claim the disclosed invention. For the purposes of compact prosecution, the present limitation will be examined as if it recited “growing an epitaxial layer on each of the plurality of horizontal channel layers in the source trench and in the drain trench and forming a conformal layer of silicide on the epitaxial layers to form a source region and a drain region in the source trench and in the drain trench.
Also in claim 1, applicant recites “filling the contact trench, the source trench, and the drain trench with a metal fill layer, wherein the conformal layer of silicide and the metal layer form a metal silicide selected from the group consisting of cobalt silicide (CoSi), molybdenum silicide (MoSi), ruthenium (RuSi), and tungsten silicide (WSi)”. There is insufficient antecedent basis for the term “metal layer” as recited in the limitation. For the purposes of compact prosecution, said limitation will be examined as if it recited “wherein the conformal layer of silicide and the metal fill layer form a metal silicide” for proper antecedent basis.
In claim 9, the claim limitations reciting “growing an epitaxial layer on the plurality of horizontal channel layers in the source trench and in the drain trench; forming a conformal layer of silicide on the epitaxial layer” are indefinite for the reasons given above with regard to claim 1. For the purposes of compact prosecution, the present limitations will be examined as if they recited “growing an epitaxial layer on each of the plurality of horizontal channel layers in the source trench and in the drain trench; forming a conformal layer of silicide on the epitaxial layers.
In claim 18, the claim limitations reciting “growing an epitaxial layer on the plurality of horizontal channel layers in the source trench and in the drain trench; forming a conformal layer of silicide on the epitaxial layer” are indefinite for the reasons given above with regard to claim 1. For the purposes of compact prosecution, the present limitations will be examined as if they recited “growing an epitaxial layer on each of the plurality of horizontal channel layers in the source trench and in the drain trench; forming a conformal layer of silicide on the epitaxial layers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-8 are rejected under 35 U.S.C. 103 as being obvious over Wang (US 20210305393 A1), hereinafter referred to as “Wang”, in view of Kim et al. (KR 930011113 B1), hereinafter referred to as “Kim” (all citations to Kim refer to the copy included with this Office Action).
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Regarding claim 1, Wang discloses a method of forming a semiconductor device (Wang fig. 1), the method comprising: forming a source trench (Wang fig. 4, 218; see [0022]) and a drain trench (see Wang fig. 4, [0020], and [0022]; [0020] discloses that “the fin structure 205 also includes source/drain regions 205SD that are disposed on both sides [of] the channel region 205C along the X direction”. Thus, all of the fabrication steps performed on the region 205SD shown in figs. 2-12 (see [0006]) are also performed similarly in a region opposite the channel region 205C despite not being shown in the drawings. Therefore, the examiner will regard the region 205SD shown in figs. 2-12 as the source zone and the implied region 205SD on the opposite side of 205C (not shown) as the drain zone. Accordingly, a drain recess is formed in the opposite region 205SD analogous to the source recess 218 (see [0022])) adjacent to a superlattice structure (Wang fig. 4, 204) on a substrate (Wang fig. 4, 202; see [0014]), the superlattice structure comprising a plurality of horizontal channel layers (Wang fig. 4, 208; see [0015]-[0016] and note that the stack 204 (comprising channel layers 208 and sacrificial layers 206) in fig. 2 is the same stack 204 shown in fig. 4 except for the source and drain trenches) and a corresponding plurality of semiconductor material layers (Wang fig. 4, 206; see [0015]-[0016] and note that the stack 204 (comprising channel layers 208 and sacrificial layers 206) in fig. 2 is the same stack 204 shown in fig. 4 except for the source and drain trenches) alternatingly arranged in a plurality of stacked pairs (see Wang fig. 4 and [0016]);
depositing a sacrificial material (Wang fig. 6, 222; see [0024]; also note that [0020] implies that a dummy source/drain feature is also deposited in the drain recess in the opposite region 205SD (not shown)) in the source trench and in the drain trench;
forming a replacement metal gate structure (Wang fig. 6, 226; see [0026]-[0028]; fig. 6 shows that the functional gate structure 226 is formed on the top surface of stack 204 in the channel region 205C; also see [0020] “a gate replacement process (or gate-last process) is adopted where the dummy gate stack 210 serves as a placeholder for a functional gate structure and is to be removed and replaced by the functional gate structure”) on a top surface of the superlattice structure;
opening a contact trench (Wang fig. 7, 228; see [0029]; fig. 7 shows that source/drain opening 228 is formed in second dielectric layer 224 adjacent functional gate structure 226; source/drain opening 228 extends to a top surface of the dummy source/drain feature 222; note that [0020] implies that a source/drain opening is also formed above the drain recess in the opposite region 205SD (not shown)) adjacent the replacement metal gate structure, the contact trench extending to a top surface of the sacrificial material (see Wang Fig. 7);
selectively removing the sacrificial material through the contact trench (see Wang fig. 8 and [0029]; dummy source/drain feature 222 is selectively removed through the source/drain opening 228 to form a bottom opening 228B; note that [0020] implies that a similar dummy source/drain feature is also selectively removed through a source/drain opening in the opposite region 205SD (not shown));
growing an epitaxial layer (Wang fig. 9 230; see [0030]-[0031]) on each of the plurality of horizontal channel layers in the source trench and in the drain trench (see Wang fig. 9 and [0030]) and forming a conformal layer of silicide (Wang fig. 10, 234; see [0032]; silicide layer 234 is conformal to the thin epitaxial features 230 because it is formed from conformal metal layer 232; through the silicidation process, silicide layer 234 is formed conformally around each of the thin epitaxial feature 230; silicide layer 234 also has a unform thickness atop epitaxial layers 230 (see applicant’s Specification paragraph [0063]); see the “Response to Arguments” section below for further clarification) on the epitaxial layers to form a source region (see annotated Wang fig. 12 above; c.f. Wang fig. 9; the source region comprises thin epitaxial features 230 and silicide layers 234 within the source trench) and a drain region (see annotated Wang fig. 12 above; c.f. Wang fig. 9; the source region comprises thin epitaxial features 230 and silicide layers 234 within the drain trench) adjacent the replacement metal gate structure in the source trench and in the drain trench;
and filling the contact trench (Wang fig. 9, 228T; see [0029]: top opening 228T is identical to the source/drain opening 228 shown in fig. 7), the source trench (Wang fig. 9, 228B; see [0024] and [0029]: the dummy source/drain feature 222 is formed in source recess 218, and bottom opening 228B is formed in the same location after dummy source/drain feature 222 is selectively removed; thus source/drain recess 218 and bottom opening 228B denote the same trench), and the drain trench (see Wang fig. 9 and [0020]; [0020] implies that an opening analogous to the bottom opening 228B (shown in fig. 9) is also formed in the same location as the drain recess in the opposite region 205SD (not shown); fig. 12 shows the metal fill layers disposed within the drain opening) with a metal fill layer (Wang figs. 11-12, 236 and 238; see [0033]-[0034]: metal source/drain feature 236 and source/drain contact 238 are formed using the same metal material).
Wang fails to explicitly disclose wherein the conformal layer of silicide and the metal layer form a metal silicide selected from the group consisting of cobalt silicide (CoSi), molybdenum silicide (MoSi), ruthenium (RuSi), and tungsten silicide (WSi).
Kim discloses a method for manufacturing a contact plug (Kim fig. 2-E) for a semiconductor device wherein a conformal silicide layer (Kim fig. 2-E, 33; see fig. 2-C and page 3, lines 11-12) is formed within a contact hole (Kim fig. 2-A, 25) over a semiconductor layer (Kim fig. 2-E, 22; see page 3, lines 1-3) and a metal silicide (Kim fig. 2-E, 40; see page 3, lines 21-23) is subsequently formed from a metal-containing fill layer (Kim fig. 2-C, 35) that is deposited over the conformal silicide layer (see Kim page 3, lines 12-20; also see fig. 2-D), wherein the metal silicide comprises tungsten silicide (WSi) (see Kim page 3, line 15-23: second silicon layer 35 is implanted with high melting point metal ions which facilitate the silicidation reaction that forms second silicide layer 40; see Kim page 3, line 9: Kim acknowledges that W (tungsten) is used as a high melting point metal ion; thus, second silicide layer 40 comprises tungsten silicide (WSi)).
The overlapping silicide teachings of Kim are incorporated into the method of Wang wherein the combination discloses wherein the conformal layer of silicide and the metal layer form a metal silicide selected from the group consisting of cobalt silicide (CoSi), molybdenum silicide (MoSi), ruthenium (RuSi), and tungsten silicide (WSi).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wang with the overlapping silicide teachings of Kim in order to reduce the series parasitic resistance between the epitaxial layers and the metal silicide (see Kim page 2, lines 20-28); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known silicide contact conductor material for another to obtain predictable results (see Kim figs. 2-E and page 2, lines 20-28).
Regarding claim 2, Wang and Kim disclose the method of claim 1, wherein the sacrificial material (Wang fig. 6, 222; see [0024]) comprises one or more of silicon carbide (SiC), aluminum oxide (AIOx), silicon oxide (SiOx), and silicon oxycarbide (SiOC) (see Wang [0024]: “the dummy source/drain feature 222 may have a composition similar to that of the sacrificial layers 206”; then see [0015] which notes that epitaxial layers 206 include silicon carbide) .
Regarding claim 3, Wang and Kim disclose the method of claim 1, wherein the sacrificial material (Wang fig. 6, 222) has a thickness in a range of from 2 nm to 50 nm (see Wang figs. 7 and 9, and [0029]-[0030]; the bottom opening 228B is formed in the space formerly occupied by dummy source/drain feature 222 before it is selectively removed. Thus, the dimensions of bottom opening 228B and dummy source/drain feature 222 are effectively identical. In [0030], it is disclosed that the thickness T2 of the bottom opening 228B is between about 15 nm and 25 nm).
Regarding claim 5, Wang and Kim disclose the method of claim 1, wherein the metal fill layer (Wang figs. 11-12, 236 and 238; see [0033]-[0034]) comprises one or more of cobalt (Co), molybdenum (Mo), ruthenium (Ru), and tungsten (W) (see Wang [0033]-[0034]: both the metal source/drain feature 236 and the source/drain contact 238 are comprised of cobalt (Co)).
Regarding claim 6, Wang and Kim disclose the method of claim 1, wherein the epitaxial layer (fig. 9, 230) comprises one or more of silicon germanium (SiGe), silicon germanium doped with boron (SiGeB), silicon phosphorus (SiP), silicon phosphorus doped with carbon (SiPC), germanium (Ge), and germanium doped with boron (GeB) (see Wang [0031]: epitaxial source/drain feature 230 is comprised of silicon germanium (SiGe)).
Regarding claim 7, Wang and Kim disclose the method of claim 1, wherein the plurality of semiconductor material layers (Wang fig. 4, 206) and the plurality of horizontal channel layers (Wang fig. 4, 208) independently comprise one or more of silicon germanium (SiGe) and silicon (Si) (see Wang [0023]: channel layers 208 consist essentially of silicon (Si) and sacrificial layers 206 consist essentially of silicon germanium (SiGe)).
Regarding claim 8, Wang and Kim disclose the method of claim 1, wherein the replacement metal gate structure (Wang fig. 6, 226) comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and titanium aluminum (TiAI) (see Wang [0028]: the gate electrode of the functional gate structure 226 comprises titanium nitride (TiN)).
Claims 9, 11-13, and 15 are rejected under 35 U.S.C. 103 as being obvious over Yeong et al. (US 20220262911 A1), hereinafter referred to as “Yeong”, in view of Wang.
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Regarding claim 9, Yeong discloses a method of forming a semiconductor device (see Yeong figs. 2-23 and [0005]-[0007]), the method comprising:
forming a source trench (see annotated Yeong fig. 8A and [0043]; the indicated source trench includes source/drain openings 84) and a drain trench (see annotated Yeong fig. 8A and [0043]; the indicated drain trench includes source/drain openings 84) adjacent to a superlattice structure (see Yeong fig. 19A and [0047]: fig. 7A shows nanostructure stack 56; epitaxial source/drain regions 88 are grown adjacent to a superlattice structure which comprises what is left of nanostructure stack 56 (see fig. 7A) after the source/drain openings 84 (see [0043]) and the replacement gates (see [0059]) are formed) on a substrate (Yeong fig. 19A, 50; see [0019]), the superlattice structure comprising:
a plurality of horizontal channel layers (Yeong figs. 11A and 11C, 58 and 56B; see Yeong [0054]) and a corresponding plurality of semiconductor material layers (Yeong fig. 11A, 56A; see [0058]-[0060]: first nanostructures 56A are subsequently replaced by replacement gates (comprising gate dielectrics 102 and gate electrodes 104 as shown in fig. 19A)) alternatingly arranged in a plurality of stacked pairs (see Yeong fig. 11A);
growing an epitaxial layer (Yeong fig. 11A, 88; see [0047]; epitaxial source/drain regions 88 are grown in source/drain openings 84 around LDD regions 82 and on portions of each of the channel regions 58) on each of the plurality of horizontal channel layers in the source trench and in the drain trench;
depositing a sacrificial material (Yeong fig. 12A, 92; see [0053]: dummy layers 92 are formed on and around epitaxial source/drain regions 88 in the source trench and in the drain trench) in the source trench and in the drain trench;
forming a replacement metal gate structure (see Yeong fig. 16A and [0059]-[0060]; gate dielectrics 102 and gate electrodes 104 are formed for replacement gates; [0060] confirms that gate electrodes 104 are composed of a metal-containing material; fig. 16A shows that this replacement metal gate structure is formed on a top surface of the uppermost channel region 58 which is included in the superlattice structure) on a top surface of the superlattice structure;
opening a contact trench (Yeong fig. 17A, 106; see [0062]; source/drain contact openings 106 are formed adjacent gate dielectrics 102 and gate electrodes 104; contact openings 106 extend to a top surface of dummy layers 92) adjacent the replacement metal gate structure, the contact trench extending to a top surface of the sacrificial material (see Yeong fig. 17A);
selectively removing the sacrificial material through the contact trench (see Yeong fig. 18A and [0062]-[0063]; source/drain contact openings 106 expose the dummy layers 92, and the dummy layers are subsequently removed to expose the epitaxial source/drain regions 88);
and filling the contact trench, the source trench, and the drain trench with a metal fill layer (Yeong fig. 19A, 112A; see fig. 19C and [0065]: lower source/drain contacts 112A include a metallic conductive material that is deposited in the source/drain contact openings 106 and around silicides 108 in spaces where the source/drain openings 84 were previously located (compare Yeong fig. 8A and fig. 19A)) to form a source region (see annotated Yeong fig. 19A above; the indicated portion of the epitaxial source/drain regions 88 coupled with the silicides 108 act as a source region) and a drain region (see annotated Yeong fig. 19A above; the indicated portion of the epitaxial source/drain regions 88 coupled with silicides 108 act as a drain region) adjacent the superlattice structure, wherein the source region and the drain region comprise a metallic silicide material (see Yeong fig. 19A and [0064]; the silicides 108 are formed by annealing a conformal metal layer deposited on epitaxial source/drain regions 88; thus, the source region and drain region both comprise a metallic silicide material).
Yeong fails to disclose forming a conformal layer of silicide on the epitaxial layers immediately after growing the epitaxial layers.
Wang discloses a method of forming a semiconductor device (Wang fig. 1) that involves forming a conformal layer of silicide (Wang fig. 10, 234; see [0032]; silicide layer 234 is conformal to the thin epitaxial features 230 because it is formed from conformal metal layer 232) on the epitaxial layers (Wang fig. 9 230; see [0030]-[0031]) immediately after growing the epitaxial layers.
The silicide layer formation method step of Wang is incorporated into the method of Yeong wherein the combination discloses all of the limitations of claim 9.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yeong with the silicide layer step of Wang to protect the epitaxial layers from contamination or mechanical damage potentially caused by the sacrificial material; and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known specific silicidation step for another to obtain predictable results (see Wang fig. 10 and [0030-0032]).
Regarding claim 11, the previously combined method of Yeong and Wang disclose the method of claim 9, wherein the sacrificial material (Yeong fig. 12A, 92) comprises a dielectric material (see Yeong [0053]) such as silicon carbonitride.
The previously combined method of Yeong and Wang fails to explicitly disclose wherein the sacrificial material comprises one or more of silicon carbide (SiC), aluminum oxide (AIOx), silicon oxide (SiOx), and silicon oxycarbide (SiOC).
Wang discloses a method of forming a semiconductor device (Wang fig. 1), wherein a sacrificial material (Wang fig. 6, 222; see [0024]) comprises one or more of silicon carbide (SiC), aluminum oxide (AIOx), silicon oxide (SiOx), and silicon oxycarbide (SiOC) (see Wang [0024]: “the dummy source/drain feature 222 may have a composition similar to that of the sacrificial layers 206”; then see [0015] which notes that epitaxial layers 206 include silicon carbide) .
The sacrificial material of Wang is incorporated as the sacrificial material in the previously combined method of Yeong and Wang wherein the present combination discloses all of the limitations of claim 11.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the previously combined method of Yeong and Wang with the sacrificial material of Wang because the combination involves a simple substitution of one known element for another to obtain predictable results—simple substitution of the silicon carbonitride sacrificial material of Yeong (Yeong fig. 12A, 92) with the silicon carbide sacrificial material of Wang (Wang fig. 6, 222) to obtain predictable results (i.e. predictably protecting source/drain regions and providing mechanical support during replacement gate formation and related method steps).
Regarding claim 12, the previously combined method of Yeong and Wang disclose the method of claim 9.
Yeong fails to disclose wherein the sacrificial material has a thickness in a range of from 2 nm to 50 nm.
Wang discloses a method of forming a semiconductor device (Wang fig. 1), wherein the sacrificial material (Wang fig. 6, 222; see [0024]) has a thickness in a range of from 2 nm to 50 nm (see Wang figs. 7, 9, and 12, and [0029]-[0030]; the bottom opening 228B is formed in the space formerly occupied by dummy source/drain feature 222 before it is selectively removed. Thus, the dimensions of bottom opening 228B and those of dummy source/drain feature 222 are effectively identical. Wang [0030] discloses that the thickness T2 of the bottom opening 228B, which extends across region 205SD (see Wang fig. 12), is between about 15 nm and 25 nm).
The sacrificial material thickness of Wang is incorporated as the sacrificial material in the previously combined device of Yeong and Wang wherein the present combination discloses all of the limitations of claim 12.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yeong with the sacrificial material of Wang to better protect source/drain features and channel layers during replacement gate and dielectric layer formation; and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the sacrificial material of Yeong (Yeong fig. 12A, 92; see [0053]) with the sacrificial material of Wang (Wang fig. 6, 222; see [0024]) to obtain predictable results (see Wang [0024]).
Regarding claim 13, Yeong and Wang disclose the method of claim 9, wherein the metal fill layer (Yeong fig. 19A, 112A; see [0065]) comprises one or more of cobalt (Co), molybdenum (Mo), ruthenium (Ru), and tungsten (W) (see Yeong [0065]: lower source/drain contacts 112A include a conductive material which is comprised of cobalt).
Regarding claim 15, Yeong and Wang disclose the method of claim 9, wherein the epitaxial layer (Yeong fig. 11A, 88) comprises one or more of silicon germanium (SiGe), silicon germanium doped with boron (SiGeB), silicon phosphorus (SiP), silicon phosphorus doped with carbon (SiPC), germanium (Ge), and germanium doped with boron (GeB) (see Yeong [0048]-[0049]; epitaxial source/drain regions 88 comprise silicon germanium (SiGe)).
Claim 18 is rejected under 35 U.S.C. 103 as being obvious over Yeong in view of Colombeau et al. (US 20200152493 A1), hereinafter referred to as “Colombeau”, further in view of Wang
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Yeong discloses a method of forming a semiconductor device (see Yeong figs. 2-23 and [0005]-[0007]), the method comprising:
forming a source trench (see annotated Yeong fig. 8A and [0043]; the indicated source trench includes source/drain openings 84) and a drain trench (see annotated Yeong fig. 8A and [0043]; the indicated drain trench includes source/drain openings 84) adjacent to a superlattice structure (see Yeong fig. 19A and [0047]: fig. 7A shows nanostructure stack 56; epitaxial source/drain regions 88 are grown adjacent to a superlattice structure which comprises what is left of nanostructure stack 56 (see fig. 7A) after the source/drain openings 84 (see [0043]) and the replacement gates (see [0059]) are formed) on a substrate (Yeong fig. 19A, 50; see [0019]), the superlattice structure comprising:
a plurality of horizontal channel layers (Yeong figs. 11A and 11C, 58 and 56B; see Yeong [0054]) and a corresponding plurality of semiconductor material layers (Yeong fig. 11A, 56A; see [0058]-[0060]: first nanostructures 56A are subsequently replaced by replacement gates (comprising gate dielectrics 102 and gate electrodes 104 as shown in fig. 19A)) alternatingly arranged in a plurality of stacked pairs (see Yeong fig. 11A);
growing an epitaxial layer (Yeong fig. 11A, 88; see [0047]; epitaxial source/drain regions 88 are grown in source/drain openings 84 around LDD regions 82 and on portions of each of the channel regions 58) on each of the plurality of horizontal channel layers in the source trench and in the drain trench;
depositing a sacrificial material (Yeong fig. 12A, 92; see [0053]: dummy layers 92 are formed on and around epitaxial source/drain regions 88 in the source trench and in the drain trench) in the source trench and in the drain trench;
forming a replacement metal gate structure (see Yeong fig. 16A and [0059]-[0060]; gate dielectrics 102 and gate electrodes 104 are formed for replacement gates; [0060] confirms that gate electrodes 104 are composed of a metal-containing material; fig. 16A shows that this replacement metal gate structure is formed on a top surface of the uppermost channel region 58 which is included in the superlattice structure) on a top surface of the superlattice structure;
opening a contact trench (Yeong fig. 17A, 106; see [0062]; source/drain contact openings 106 are formed adjacent gate dielectrics 102 and gate electrodes 104; contact openings 106 extend to a top surface of dummy layers 92) adjacent the replacement metal gate structure, the contact trench extending to a top surface of the sacrificial material (see Yeong fig. 17A);
selectively removing the sacrificial material through the contact trench (see Yeong fig. 18A and [0062]-[0063]; source/drain contact openings 106 expose the dummy layers 92, and the dummy layers are subsequently removed to expose the epitaxial source/drain regions 88);
and filling the contact trench, the source trench, and the drain trench with a metal fill layer (Yeong fig. 19A, 112A; see fig. 19C and [0065]: lower source/drain contacts 112A include a metallic conductive material that is deposited in the source/drain contact openings 106 and around silicides 108 in spaces where the source/drain openings 84 were previously located (compare Yeong fig. 8A and fig. 19A)) to form a source region (see annotated Yeong fig. 19A above; the indicated portion of the epitaxial source/drain regions 88 coupled with the silicides 108 act as a source region) and a drain region (see annotated Yeong fig. 19A above; the indicated portion of the epitaxial source/drain regions 88 coupled with silicides 108 act as a drain region) adjacent the superlattice structure, wherein the source region and the drain region comprise a metallic silicide material (see Yeong fig. 19A and [0064]; the silicides 108 are formed by annealing a conformal metal layer deposited on epitaxial source/drain regions 88; thus, the source region and drain region both comprise a metallic silicide material).
Yeong fails to disclose a non-transitory computer readable medium including instructions, that, when executed by a controller of a processing chamber, causes the processing chamber to perform the disclosed method; and forming a conformal layer of silicide on the epitaxial layers immediately after growing the epitaxial layers.
Colombeau discloses a multi-chamber processing tool (Colombeau fig. 1, 100) used to fabricate horizontal gate all around field effect transistors (hGAA FETs) (see Colombeau fig. 13A and [0017]). The multi-chamber processing tool includes processing chambers (Colombeau fig. 1: 120, 122, 124, 126, 128, and 130) to perform various fabrication processes such as but not limited to wafer cleaning, etching, and epitaxial growth (see Colombeau [0027]). The multi-chamber processing tool is controlled by a system controller (Colombeau fig. 1, 190) which includes a non-transitory computer-readable medium (Colombeau fig. 1, 194; see [0029]: the memory 194 is a non-transitory computer-readable medium) and a CPU (Colombeau fig. 1, 192) for executing computer instruction code stored in the memory (see Colombeau [0029]). The system controller controls the processing chambers to perform processes in accordance with hGAA FET manufacturing methods (see Colombeau [0028]-[0029]).
The multi-chamber processing tool of Colombeau is configured to perform the method of Yeong wherein the combination discloses a non-transitory computer readable medium (Colombeau fig. 1, 194) including instructions (see Colombeau [0029]: the system controller 190 includes a CPU 192 which executes computer instruction code stored in memory 194), that, when executed by a controller of a processing chamber (Colombeau fig. 1, 190; see [0028]: system controller 190 directly controls the various processing chambers in the processing tool), causes the processing chamber (Colombeau fig. 1, 130) to perform the disclosed method of Yeong.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the multi-chamber processing tool of Colombeau to perform the method of Yeong to both increase manufacturing output and increase device reliability by reducing manufacturing errors.
Yeong and Colombeau do not explicitly disclose forming a conformal layer of silicide on the epitaxial layers
Wang discloses a method of forming a semiconductor device (Wang fig. 1) that involves forming a conformal layer of silicide (Wang fig. 10, 234; see [0032]; silicide layer 234 is conformal to the thin epitaxial features 230 because it is formed from conformal metal layer 232) on the epitaxial layers (Wang fig. 9 230; see [0030]-[0031]) immediately after growing the epitaxial layers.
The silicide layer formation method step of Wang is incorporated into the method of Yeong to be performed by the computer readable medium of Colombeau wherein the present combination discloses all of the limitations of claim 18.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yeong (to be performed by the computer readable medium of Colombeau) with the silicide layer step of Wang to protect the epitaxial layers from contamination or mechanical damage potentially caused by the sacrificial material.
Response to Arguments
Applicant’s arguments filed April 30th, 2026, have been fully considered. The majority of said arguments have been found unpersuasive.
On page 11 of applicant’s response, Applicant traverses the previous 112(b) rejection of claims 1-8. Applicant suggests that the present amendments to claim 1 and the cancellation of claim 4 overcome the previous 112(b) rejection; Examiner agrees and has withdrawn the previous 112(b) rejection. However, applicant is reminded of the new 112(b) rejections above.
Similarly on pages 11 and 12 of applicant’s response, Applicant traverses the previous 112(b) rejections of claims 14-17 and claim 20. Examiner has withdrawn all previous 112(b) rejections, but applicant is reminded of the new 112(b) rejections above.
On page 12 of applicant’s response, Applicant traverses the basis for the previous 102 rejection of claims 1-8 in view of Wang.
On page 13, Applicant suggests that the structure formed by the presently claimed method differs from the structure formed by the method of Wang in the conformal coverage of silicide over the rounded shape of the protruding S/D epitaxial features. However, the claims, as currently recited, do not require rounded epitaxial features. Furthermore, as for the conformality of the silicide layers, the claims only require: “forming a conformal layer of silicide on the epitaxial layers“. Therefore, the present claims do not require that the silicide layer be formed conformal to any surrounding dielectrics. In the method of Wang, a conformal silicide layer (Wang fig. 10, 234) is formed on the thin epitaxial feature (Wang fig. 9, 230); the silicide layer is conformal because it is formed by depositing a metal layer on the surfaces of both the thin epitaxial features 230 and the inner spacer features 220 and annealing said metal layer to form a silicide conformally isolated around the thin epitaxial features (see Wang [0032]: “due to the selective nature of the formation of the silicide layer”).
Also, on page 13 of applicant’s response, Applicant suggests that the claimed sacrificial material is removed through a contact trench opening, while Wang teaches removing dummy source/drain feature 222 (see Wang fig. 7) through a self-aligned ILD using selective etching. However, Examiner is not convinced of a difference between the claimed contact trench opening as taught by applicant (instant fig. 2E and [0061]) and the source/drain opening as taught by Wang (see Wang fig. 7 and [0029]). Both are formed by etching and both are used to remove sacrificial/dummy material from source/drain cavities.
On page 13 of applicant’s response, Applicant argues that, based on the preceding arguments, the claimed invention is not anticipated by Wang and that the basis of rejection of claims 1-8 should be withdrawn. The Examiner notes that a 103 combination of prior art is presented in light of the newly presented amendments.
Additionally, on page 13 of applicant’s response, Applicant suggests that Wang fails to disclose, teach, or suggest the sacrificial material comprising one or more of silicon carbide, aluminum oxide, silicon oxide, or silicon oxycarbide, as recited in present claim 2. Wang [0024] discloses “the dummy source/drain feature 222 may have a composition similar to that of the sacrificial layers 206”. In paragraph [0015] of Wang, Wang discloses that first epitaxial layers 206 may include silicon carbide. Therefore, dummy source/drain feature 222 (i.e. the sacrificial material) comprises silicon carbide.
On page 14 of applicant’s response, Applicant traverses the basis of the previous 102 rejection of claims 9-10 and 13-17 in view of Yeong.
On pages 14-15 of applicant’s response, Applicant suggests that Yeong fails to disclose growing an epitaxial layer on each of the plurality of horizontal channel layers in the source trench and the drain trench and forming a conformal layer of silicide on the epitaxial layers to form a source region and a drain region in the respective trenches. The Examiner notes that Yeong does disclose forming epitaxial layers (Yeong figs. 11A and 11B, 88; see Yeong [0047]) on horizontal channel layers (Yeong figs. 11A and 11C, 58 and 56B; see Yeong [0054]) in a source/drain trench (Yeong fig. 8A, 84) and forming a conformal layer of silicide (Yeong figs. 19A and 19C, 108; see Yeong [0064]) on the epitaxial layers to form a source region and a drain region. Furthermore, Examiner has incorporated the order of epitaxial growth and silicide formation as taught in Wang into the method of Yeong in light of the amended claim limitations of present claim 9.
On page 15 of applicant’s response, Applicant also suggests that the claimed method differs from the method of Yeong because the claimed sacrificial material is removed through a contact trench opening while Yeong discloses removing dummy layers 92 (See Yeong fig. 17A) through a self-aligned ILD using selective etching. The Examiner is not convinced of a difference between the claimed contact trench opening as taught by applicant (instant fig. 2E and [0061]) and the source/drain contact openings as taught by Yeong (Yeong figs. 18A and 18C, 106; see [0062]). Both are formed by etching and both are used to remove sacrificial/dummy material from source/drain cavities.
On page 15 of applicant’s response, Applicant argues that the preceding considerations suggest that the claimed invention is not anticipated by Yeong and that the indicated basis of rejection should be withdrawn. The Examiner notes that a 103 combination of prior art is presented in light of the newly presented amendments.
On page 15 of applicant’s response, Applicant traverses the basis of the 103 rejection of claims 11-12 over Yeong in view of Wang.
On page 15, Applicant suggests that Yeong fails to disclose growing an epitaxial layer on the plurality of horizontal channel layers in the source trench and in the drain trench and forming a conformal layer of silicide on the epitaxial layer to form a source region and a drain region in the source trench and in the drain trench. The Examiner notes that Yeong does discloses forming epitaxial layers (Yeong figs. 11A and 11B, 88; see Yeong [0047]) on horizontal channel layers (Yeong figs. 11A and 11C, 58 and 56B; see Yeong [0054]) in a source/drain trench (Yeong fig. 8A, 84) and forming a conformal layer of silicide (Yeong figs. 19A and 19C, 108; see Yeong [0064]) on the epitaxial layers to form a source region and a drain region.
On page 15, Applicant also suggests that the method of Yeong differs from the claimed method in that Yeong discloses removing sacrificial material (Yeong fig. 12A, 92; see fig. 17A) through a self-aligned ILD using selective-etching rather than removing said material through contact trench. The Examiner is not convinced of a difference between the claimed contact trench opening as taught by applicant (instant fig. 2E and [0061]) and the source/drain contact openings as taught by Yeong (Yeong figs. 18A and 18C, 106; see [0062]). Both are formed by etching and both are used to remove sacrificial/dummy material from source/drain cavities.
Also on page 15, Applicant suggests that the claimed invention differs from the method of Wang because (1) Wang discloses discrete silicide coverage of the channel layers rather than conformal coverage disclosed by Applicant, (2) Wang fails to disclose the rounded shape of the epitaxial layers, and (3) Wang discloses removing sacrificial material (Wang fig. 7, 222) through a self-aligned ILD using selective etching rather than through a contact trench opening as in the claimed method. As for (1) and (2), the Claims, as currently recited, do not require rounded epitaxial features. Further, as for the conformality of the silicide layers, the Claims only require: “forming a conformal layer of silicide on the epitaxial layers”. Therefore, the present claims do not require that the silicide layer be formed conformal to any surrounding dielectrics. In the method of Wang, a conformal silicide layer (Wang fig. 10, 234) is formed on the thin epitaxial feature (Wang fig. 9, 230); the silicide layer is conformal because it is formed by depositing a conformal metal layer on the surfaces of both the thin epitaxial features 230 and the inner spacer features 220 and annealing said metal layer to form a silicide conformally isolated around the thin epitaxial features (see Wang [0032]: “due to the selective nature of the formation of the silicide layer”). As for (3), Examiner is not convinced of a difference between the contact trench opening as taught by Applicant (instant fig. 2E and [0061]) and the source/drain opening as taught by Wang (see Wang fig. 7 and [0029]) or Yeong (see Yeong fig. 17A). Both are formed by etching and both are used to remove sacrificial/dummy material from source/drain cavities.
On page 16, Applicant suggests that neither Yeong nor Wang disclose, teach, or suggest the sacrificial material comprising one or more of silicon carbide (SiC), aluminum oxide (AlOx) silicon oxide (SiOx), or silicon oxycarbide (SiOC). However, Wang [0024] discloses “the dummy source/drain feature 222 may have a composition similar to that of the sacrificial layers 206”. In paragraph [0015] of Wang, Wang discloses that first epitaxial layers 206 may include silicon carbide. Therefore, dummy source/drain feature 222 (i.e. the sacrificial material raught in Wang) comprises silicon carbide. Thus, Examiner has maintained the basis of rejection of claim 11.
On page 16, Applicant argues that the preceding considerations suggest that the claimed invention is patentable over the combination of Yeong and Wang and that, accordingly, the indicated basis of rejection should be withdrawn. As shown however, Examiner is not persuaded by said arguments, and the basis of rejection for claims 11-12 is maintained.
On page 16 of applicant’s response, Applicant traverses the basis of rejection of claims 18-20 (claims 19-20 being presently cancelled) as being unpatentable over Wang ion view of Colombeau.
On page 16, Applicant reiterates arguments are repeated pertaining to Wang’s alleged deficiencies in view of the claimed invention. The Examiner notes that the same arguments are responded to in kind.
In page 16, Applicant suggests that Colombeau fails to remedy the deficiencies of Wang. As expressed above, Examiner is not convinced of the alleged deficiencies of Wang and has clarified the Office’s position in the above rejection of amended claim 18 (Examiner utilizes Yeong in view of Wang and Colombeau in the present rejection). Furthermore, while Colombeau does not explicitly teach preforming the claimed method steps with the disclosed non-transitory computer readable medium including instructions, Applicant has not suggested that PHOSITA would not have been able to combine the teachings of Colombeau before the effective filing date of the claimed invention to arrive at a non-transitory computer readable medium with instructions to perform the specific method steps of the combined method of Yeong and Wang. As shown above, the teachings of Colombeau are sufficient to enable PHOSITA in this endeavor.
On page 17, Applicant argues that the preceding considerations suggest that the claimed invention is patentable over the previous combination and that, accordingly, the indicated basis of rejection should be withdrawn. The Examiner notes that a 103 combination of prior art is presented in light of the newly presented amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SAMUEL PARK/Examiner, Art Unit 2818
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