DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/18/2026 has been entered.
Response to Amendment
Applicant’s arguments/remarks, see pgs. 8-15, with respect to the immediate allowance of the current application have been fully considered but are not persuasive.
Pertaining to the Applicant’s arguments/remarks, pgs. 8-15, regarding the newly amended limitations to at least the independent claims:
The Examiner notes that new combination(s) of prior art(s) are presented in light of the amendments such that arguments directed solely to the previously presented rejections are now moot.
Pertaining to the Applicant’s arguments/remarks pg. 12, regarding the polycrystalline silicon layer which forms the silicide compared to the epitaxial single-crystal film to form the silicide of the Applicant’s invention. The Examiner notes that crystallinity is not claimed and although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The arguments further appear to suggest that “conformally” has a meaning which distinguishes in process from a heat treatment to form silicide between silicon and a metal which is incorrect; the limitation “conformal” is provided with a definition in the Applicant’s specification [0043] “the term "conformal" means that the layer adapts to the contours of a feature or a layer” which is a description of the shape rather than the method of forming the silicide. Further, the arguments argue the shape of the epitaxial contact surface area with respect to Wang to conclude that the prior art does not disclose the sacrificial material to which the Examiner disagrees. The Wang reference is incorporated for the material of the sacrificial material of element 222 and not for other limitations which have already been disclosed by the other combination of prior arts. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 and/or 103 rejections are provided in parenthesis.
Claim Objections
Claims 1, 3, 5-9, 12-13, 15, and 18 are objected to because of the following minor informalities:
Claims 1, 9, 18 each recites, at least once, “the group consisting of” which should each be changed to along the lines of “a group consisting of” to address the minor informality. Appropriate corrections are required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 and 5-8 are rejected under 35 U.S.C. 103 as being obvious over Wang (US 20210305393 A1), hereinafter referred to as “Wang”, in view of Adusumilli et al. (US 2018/0090582 A1), hereinafter as A1, in view of Kim et al. (KR 930011113 B1), hereinafter referred to as “Kim” (all citations to Kim refer to the copy included with this Office Action).
[Bangsaruntip et al. (US 2011/0133165 A1), hereinafter as B1 is utilized herein as evidence]
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Regarding claim 1, Wang discloses a method of forming a semiconductor device (Wang fig. 1), the method comprising:
forming a source trench (Wang fig. 4, 218; see [0022]) and a drain trench (see Wang fig. 4, [0020], and [0022]; [0020] discloses that “the fin structure 205 also includes source/drain regions 205SD that are disposed on both sides [of] the channel region 205C along the X direction”. Thus, all of the fabrication steps performed on the region 205SD shown in figs. 2-12 (see [0006]) are also performed similarly in a region opposite the channel region 205C despite not being shown in the drawings. Therefore, the examiner will regard the region 205SD shown in figs. 2-12 as the source zone and the implied region 205SD on the opposite side of 205C (not shown) as the drain zone. Accordingly, a drain recess is formed in the opposite region 205SD analogous to the source recess 218 (see [0022])) adjacent to a superlattice structure (Wang fig. 4, 204) on a substrate (Wang fig. 4, 202; see [0014]), the superlattice structure comprising a plurality of horizontal channel layers (Wang fig. 4, 208; see [0015]-[0016] and note that the stack 204 (comprising channel layers 208 and sacrificial layers 206) in fig. 2 is the same stack 204 shown in fig. 4 except for the source and drain trenches) and a corresponding plurality of semiconductor material layers (Wang fig. 4, 206; see [0015]-[0016] and note that the stack 204 (comprising channel layers 208 and sacrificial layers 206) in fig. 2 is the same stack 204 shown in fig. 4 except for the source and drain trenches) with inner spacers (elements 220, see [0032] “inner spacer features 220”) alternatingly arranged in a plurality of stacked pairs (see Wang fig. 4 and [0016]);
depositing a sacrificial material (Wang fig. 6, 222; see [0024]; also note that [0020] implies that a dummy source/drain feature is also deposited in the drain recess in the opposite region 205SD (not shown)) in the source trench and in the drain trench, the sacrificial material comprises one or more of silicon carbide (SiC), aluminum oxide (AIOx), silicon oxide (SiOx), and silicon oxycarbide (SiOC) (see Wang [0024]: “the dummy source/drain feature 222 may have a composition similar to that of the sacrificial layers 206”; then see [0015] which notes that epitaxial layers 206 include silicon carbide);
forming a replacement metal gate structure (Wang fig. 6, 226; see [0026]-[0028]; fig. 6 shows that the functional gate structure 226 is formed on the top surface of stack 204 in the channel region 205C; also see [0020] “a gate replacement process (or gate-last process) is adopted where the dummy gate stack 210 serves as a placeholder for a functional gate structure and is to be removed and replaced by the functional gate structure”) having a first portion (portion at a height of element 238) on a top surface of the superlattice structure, and a second portion surrounding the plurality of horizontal channel layers (portion at a height of element 236) (see in particular Fig. 12);
opening a contact trench (Wang fig. 7, 228; see [0029]; fig. 7 shows that source/drain opening 228 is formed in second dielectric layer 224 adjacent functional gate structure 226; source/drain opening 228 extends to a top surface of the dummy source/drain feature 222; note that [0020] implies that a source/drain opening is also formed above the drain recess in the opposite region 205SD (not shown)) adjacent to the first portion of the replacement metal gate structure, the contact trench extending to a top surface of the sacrificial material (see Wang Fig. 7);
selectively removing the sacrificial material through the contact trench (see Wang fig. 8 and [0029]; dummy source/drain feature 222 is selectively removed through the source/drain opening 228 to form a bottom opening 228B; note that [0020] implies that a similar dummy source/drain feature is also selectively removed through a source/drain opening in the opposite region 205SD (not shown));
growing an epitaxial layer (Wang fig. 9 230; see [0030]-[0031]) on each horizontal channel layer in the source trench and in the drain trench (see Wang fig. 9 and [0030]) and forming a conformal layer of silicide (Wang fig. 10, 234; see [0032]; silicide layer 234 is conformal to the thin epitaxial features 230 because it is formed from conformal metal layer 232; through the silicidation process, silicide layer 234 is formed conformally around each of the thin epitaxial feature 230; silicide layer 234 also has a unform thickness atop epitaxial layers 230 (see applicant’s Specification paragraph [0063]); see the “Response to Arguments” section below for further clarification) on each epitaxial layer to form a source region (see annotated Wang fig. 12 above; c.f. Wang fig. 9; the source region comprises thin epitaxial features 230 and silicide layers 234 within the source trench) and a drain region (see annotated Wang fig. 12 above; c.f. Wang fig. 9; the source region comprises thin epitaxial features 230 and silicide layers 234 within the drain trench) adjacent the replacement metal gate structure in the source trench and in the drain trench, the conformal layer of silicide surrounding each epitaxial layer (see Fig. 12); and
filling the contact trench (Wang fig. 9, 228T; see [0029]: top opening 228T is identical to the source/drain opening 228 shown in fig. 7), the source trench (Wang fig. 9, 228B; see [0024] and [0029]: the dummy source/drain feature 222 is formed in source recess 218, and bottom opening 228B is formed in the same location after dummy source/drain feature 222 is selectively removed; thus source/drain recess 218 and bottom opening 228B denote the same trench), and the drain trench (see Wang fig. 9 and [0020]; [0020] implies that an opening analogous to the bottom opening 228B (shown in fig. 9) is also formed in the same location as the drain recess in the opposite region 205SD (not shown); fig. 12 shows the metal fill layers disposed within the drain opening) with a metal fill layer (Wang figs. 11-12, 236 and 238; see [0033]-[0034]: metal source/drain feature 236 and source/drain contact 238 are formed using the same metal material).
Wang fails to explicitly disclose the conformal layer of silicide surrounding a portion of the inner spacers; wherein the conformal layer of silicide and the metal fill layer form a metal silicide selected from the group consisting of cobalt silicide (CoSi), molybdenum silicide (MoSi), ruthenium (RuSi), and tungsten silicide (WSi).
A1 discloses the conformal layer of silicide surrounding a portion of the inner spacers (see Figs. 3-4 the conformal layer of silicide element 32 surrounding a portion of the inner spacers elements 28, see [0035] “metal silicide or metal germane-silicide wrap-around contact layers 32”; note, due to the metal element 31 covering an entire surface and silicidation of the semiconductor material protruding laterally further than the inner spacers, at least edge portions of the metal which forms the silicide element 32 are surrounding a portion of the inner spacers).
The shape of the silicide as taught by A1 is incorporated as the shape of the silicide of Wang.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of A1 with Wang because the combination can provide uniform and conformal doping for reduces contact resistance and thermodynamical benefits from reduced total energy of the system (see A1 [0029]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known silicide shape for another in a similar device to obtain predictable results (see A1 Fig. 4 and see evidentiary reference B1 Figs. 4A-B versus Figs. 4C-D which shows alternatively the silicide element 420 having varied vertical thickness to be non-overlapped or overlapped with the inner spacer elements 110, see [0019-0020])
Wang, A1 do not disclose wherein the conformal layer of silicide and the metal fill layer form a metal silicide selected from the group consisting of cobalt silicide (CoSi), molybdenum silicide (MoSi), ruthenium (RuSi), and tungsten silicide (WSi).
Kim discloses a method for manufacturing a contact plug (Kim fig. 2-E) for a semiconductor device wherein a conformal silicide layer (Kim fig. 2-E, 33; see fig. 2-C and page 3, lines 11-12) is formed within a contact hole (Kim fig. 2-A, 25) over a semiconductor layer (Kim fig. 2-E, 22; see page 3, lines 1-3) and a metal silicide (Kim fig. 2-E, 40; see page 3, lines 21-23) is subsequently formed from a metal-containing fill layer (Kim fig. 2-C, 35) that is deposited over the conformal silicide layer (see Kim page 3, lines 12-20; also see fig. 2-D), wherein the metal silicide comprises tungsten silicide (WSi) (see Kim page 3, line 15-23: second silicon layer 35 is implanted with high melting point metal ions which facilitate the silicidation reaction that forms second silicide layer 40; see Kim page 3, line 9: Kim acknowledges that W (tungsten) is used as a high melting point metal ion; thus, second silicide layer 40 comprises tungsten silicide (WSi)).
The overlapping silicide teachings of Kim are incorporated into the method of Wang wherein the combination discloses wherein the conformal layer of silicide and the metal layer form a metal silicide selected from the group consisting of cobalt silicide (CoSi), molybdenum silicide (MoSi), ruthenium (RuSi), and tungsten silicide (WSi).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wang with the overlapping silicide teachings of Kim in order to reduce the series parasitic resistance between the epitaxial layers and the metal silicide (see Kim page 2, lines 20-28); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known silicide contact conductor material for another to obtain predictable results (see Kim figs. 2-E and page 2, lines 20-28).
Regarding claim 3, Wang, A1, Kim disclose the method of claim 1, wherein the sacrificial material (Wang fig. 6, 222) has a thickness in a range of from 2 nm to 50 nm (see Wang figs. 7 and 9, and [0029]-[0030]; the bottom opening 228B is formed in the space formerly occupied by dummy source/drain feature 222 before it is selectively removed. Thus, the dimensions of bottom opening 228B and dummy source/drain feature 222 are effectively identical. In [0030], it is disclosed that the thickness T2 of the bottom opening 228B is between about 15 nm and 25 nm).
Regarding claim 5, Wang, A1, Kim disclose the method of claim 1, wherein the metal fill layer (Wang figs. 11-12, 236 and 238; see [0033]-[0034]) comprises one or more of cobalt (Co), molybdenum (Mo), ruthenium (Ru), and tungsten (W) (see Wang [0033]-[0034]: both the metal source/drain feature 236 and the source/drain contact 238 are comprised of cobalt (Co)).
Regarding claim 6, Wang, A1, Kim disclose the method of claim 1, wherein the epitaxial layer (fig. 9, 230) comprises one or more of silicon germanium (SiGe), silicon germanium doped with boron (SiGeB), silicon phosphorus (SiP), silicon phosphorus doped with carbon (SiPC), germanium (Ge), and germanium doped with boron (GeB) (see Wang [0031]: epitaxial source/drain feature 230 is comprised of silicon germanium (SiGe)).
Regarding claim 7, Wang, A1, Kim disclose the method of claim 1, wherein the plurality of semiconductor material layers (Wang fig. 4, 206) and the plurality of horizontal channel layers (Wang fig. 4, 208) independently comprise one or more of silicon germanium (SiGe) and silicon (Si) (see Wang [0023]: channel layers 208 consist essentially of silicon (Si) and sacrificial layers 206 consist essentially of silicon germanium (SiGe)).
Regarding claim 8, Wang, A1, Kim disclose the method of claim 1, wherein the replacement metal gate structure (Wang fig. 6, 226) comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and titanium aluminum (TiAI) (see Wang [0028]: the gate electrode of the functional gate structure 226 comprises titanium nitride (TiN)).
Claims 9, 12-13, and 15 are rejected under 35 U.S.C. 103 as being obvious over Yeong et al. (US 20220262911 A1), hereinafter referred to as “Yeong”, in view of Wang, in view of Adusumilli et al. (US 2018/0090582 A1), hereinafter as A1.
[Bangsaruntip et al. (US 2011/0133165 A1), hereinafter as B1 is utilized herein as evidence]
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Regarding claim 9, Yeong discloses a method of forming a semiconductor device (see Yeong figs. 2-23 and [0005]-[0007]), the method comprising:
forming a source trench (see annotated Yeong fig. 8A and [0043]; the indicated source trench includes source/drain openings 84) and a drain trench (see annotated Yeong fig. 8A and [0043]; the indicated drain trench includes source/drain openings 84) adjacent to a superlattice structure (see Yeong fig. 19A and [0047]: fig. 7A shows nanostructure stack 56; epitaxial source/drain regions 88 are grown adjacent to a superlattice structure which comprises what is left of nanostructure stack 56 (see fig. 7A) after the source/drain openings 84 (see [0043]) and the replacement gates (see [0059]) are formed) on a substrate (Yeong fig. 19A, 50; see [0019]), the superlattice structure comprising a plurality of horizontal channel layers (Yeong figs. 11A and 11C, 58 and 56B; see Yeong [0054]) and a corresponding plurality of semiconductor material layers (Yeong fig. 11A, 56A; see [0058]-[0060]: first nanostructures 56A are subsequently replaced by replacement gates (comprising gate dielectrics 102 and gate electrodes 104 as shown in fig. 19A)) with inner spacers (elements 86, see [0044] “inner spacers 86”) alternatingly arranged in a plurality of stacked pairs (see Yeong fig. 11A);
growing an epitaxial layer (Yeong fig. 11A, 88; see [0047]; epitaxial source/drain regions 88 are grown in source/drain openings 84 around LDD regions 82 and on portions of each of the channel regions 58) on each horizontal channel layer in the source trench and in the drain trench;
depositing a sacrificial material (Yeong fig. 12A, 92; see [0053]: dummy layers 92 are formed on and around epitaxial source/drain regions 88 in the source trench and in the drain trench) in the source trench and in the drain trench;
forming a replacement metal gate structure (see Yeong fig. 16A and [0059]-[0060]; gate dielectrics 102 and gate electrodes 104 are formed for replacement gates; [0060] confirms that gate electrodes 104 are composed of a metal-containing material; fig. 16A shows that this replacement metal gate structure is formed on a top surface of the uppermost channel region 58 which is included in the superlattice structure) having a first portion (portion at a height of element 80) on a top surface of the superlattice structure and a second portion surrounding the plurality of horizontal channel layers (portion at a height below element 80, see Fig. 19A);
opening a contact trench (Yeong fig. 17A, 106; see [0062]; source/drain contact openings 106 are formed adjacent gate dielectrics 102 and gate electrodes 104; contact openings 106 extend to a top surface of dummy layers 92) adjacent the first portion of the replacement metal gate structure, the contact trench extending to a top surface of the sacrificial material (see Yeong fig. 17A);
selectively removing the sacrificial material through the contact trench (see Yeong fig. 18A and [0062]-[0063]; source/drain contact openings 106 expose the dummy layers 92, and the dummy layers are subsequently removed to expose the epitaxial source/drain regions 88); and
filling the contact trench, the source trench, and the drain trench with a metal fill layer (Yeong fig. 19A, 112A; see fig. 19C and [0065]: lower source/drain contacts 112A include a metallic conductive material that is deposited in the source/drain contact openings 106 and around silicides 108 in spaces where the source/drain openings 84 were previously located (compare Yeong fig. 8A and fig. 19A)) to form a source region (see annotated Yeong fig. 19A above; the indicated portion of the epitaxial source/drain regions 88 coupled with the silicides 108 act as a source region) and a drain region (see annotated Yeong fig. 19A above; the indicated portion of the epitaxial source/drain regions 88 coupled with silicides 108 act as a drain region) adjacent the superlattice structure, wherein the source region and the drain region comprise a metallic silicide material (see Yeong fig. 19A and [0064]; the silicides 108 are formed by annealing a conformal metal layer deposited on epitaxial source/drain regions 88; thus, the source region and drain region both comprise a metallic silicide material).
Yeong fails to disclose forming a conformal layer of silicide on each epitaxial layer, the conformal layer of silicide surrounding each epitaxial layer and a portion of the inner spacers; the sacrificial material selected from the group consisting of aluminum oxide (AIOx), silicon oxide (SiOx), and silicon oxycarbide (SiOC).
Wang discloses a method of forming a semiconductor device (Wang fig. 1) that involves forming a conformal layer of silicide (Wang fig. 10, 234; see [0032]; silicide layer 234 is conformal to the thin epitaxial features 230 because it is formed from conformal metal layer 232) on each epitaxial layer (Wang fig. 9 230; see [0030]-[0031]), the conformal layer of silicide surrounding each epitaxial layer (see Fig. 10); the sacrificial material selected from the group consisting of aluminum oxide (AIOx), silicon oxide (SiOx), and silicon oxycarbide (SiOC) (see [0024]: “the dummy source/drain feature 222 may have a composition similar to that of the sacrificial layers 206”; then see [0015] which notes that epitaxial layers 206 include silicon carbide).
The silicide layer formation method step of Wang is incorporated into the method of Yeong.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yeong with the silicide layer step of Wang to protect the epitaxial layers from contamination or mechanical damage potentially caused by the sacrificial material; and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known specific silicidation step for another to obtain predictable results (see Wang fig. 10 and [0030-0032]).
Yeong and Wang do not disclose the conformal layer of silicide surrounding a portion of the inner spacers.
A1 discloses the conformal layer of silicide surrounding a portion of the inner spacers (see Figs. 3-4 the conformal layer of silicide element 32 surrounding a portion of the inner spacers elements 28, see [0035] “metal silicide or metal germane-silicide wrap-around contact layers 32”; note, due to the metal element 31 covering an entire surface and silicidation of the semiconductor material protruding laterally further than the inner spacers, at least edge portions of the metal which forms the silicide element 32 are surrounding a portion of the inner spacers).
The shape of the silicide as taught by A1 is incorporated as the shape of the silicide of Yeong and Wang.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of A1 with Wang because the combination can provide uniform and conformal doping for reduces contact resistance and thermodynamical benefits from reduced total energy of the system (see A1 [0029]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known silicide shape for another in a similar device to obtain predictable results (see A1 Fig. 4 and see evidentiary reference B1 Figs. 4A-B versus Figs. 4C-D which shows alternatively the silicide element 420 having varied vertical thickness to be non-overlapped or overlapped with the inner spacer elements 110, see [0019-0020])
Regarding claim 12, the previously combined method of Yeong and Wang disclose the method of claim 9.
Yeong fails to disclose wherein the sacrificial material has a thickness in a range of from 2 nm to 50 nm.
Wang discloses a method of forming a semiconductor device (Wang fig. 1), wherein the sacrificial material (Wang fig. 6, 222; see [0024]) has a thickness in a range of from 2 nm to 50 nm (see Wang figs. 7, 9, and 12, and [0029]-[0030]; the bottom opening 228B is formed in the space formerly occupied by dummy source/drain feature 222 before it is selectively removed. Thus, the dimensions of bottom opening 228B and those of dummy source/drain feature 222 are effectively identical. Wang [0030] discloses that the thickness T2 of the bottom opening 228B, which extends across region 205SD (see Wang fig. 12), is between about 15 nm and 25 nm).
The sacrificial material thickness of Wang is incorporated as the sacrificial material in the previously combined device of Yeong and Wang wherein the present combination discloses all of the limitations of claim 12.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yeong with the sacrificial material of Wang to better protect source/drain features and channel layers during replacement gate and dielectric layer formation; and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the sacrificial material of Yeong (Yeong fig. 12A, 92; see [0053]) with the sacrificial material of Wang (Wang fig. 6, 222; see [0024]) to obtain predictable results (see Wang [0024]).
Regarding claim 13, Yeong and Wang disclose the method of claim 9, wherein the metal fill layer (Yeong fig. 19A, 112A; see [0065]) comprises one or more of cobalt (Co), molybdenum (Mo), ruthenium (Ru), and tungsten (W) (see Yeong [0065]: lower source/drain contacts 112A include a conductive material which is comprised of cobalt).
Regarding claim 15, Yeong and Wang disclose the method of claim 9, wherein the epitaxial layer (Yeong fig. 11A, 88) comprises one or more of silicon germanium (SiGe), silicon germanium doped with boron (SiGeB), silicon phosphorus (SiP), silicon phosphorus doped with carbon (SiPC), germanium (Ge), and germanium doped with boron (GeB) (see Yeong [0048]-[0049]; epitaxial source/drain regions 88 comprise silicon germanium (SiGe)).
Claim 18 is rejected under 35 U.S.C. 103 as being obvious over Yeong in view of Colombeau et al. (US 20200152493 A1), hereinafter referred to as “Colombeau”, further in view of Wang, in view of Adusumilli et al. (US 2018/0090582 A1), hereinafter as A1.
[Bangsaruntip et al. (US 2011/0133165 A1), hereinafter as B1 is utilized herein as evidence]
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Regarding Claim 18, Yeong discloses a method of forming a semiconductor device (see Yeong figs. 2-23 and [0005]-[0007]), the method comprising:
forming a source trench (see annotated Yeong fig. 8A and [0043]; the indicated source trench includes source/drain openings 84) and a drain trench (see annotated Yeong fig. 8A and [0043]; the indicated drain trench includes source/drain openings 84) adjacent to a superlattice structure (see Yeong fig. 19A and [0047]: fig. 7A shows nanostructure stack 56; epitaxial source/drain regions 88 are grown adjacent to a superlattice structure which comprises what is left of nanostructure stack 56 (see fig. 7A) after the source/drain openings 84 (see [0043]) and the replacement gates (see [0059]) are formed) on a substrate (Yeong fig. 19A, 50; see [0019]), the superlattice structure comprising:
a plurality of horizontal channel layers (Yeong figs. 11A and 11C, 58 and 56B; see Yeong [0054]) and a corresponding plurality of semiconductor material layers (Yeong fig. 11A, 56A; see [0058]-[0060]: first nanostructures 56A are subsequently replaced by replacement gates (comprising gate dielectrics 102 and gate electrodes 104 as shown in fig. 19A)) alternatingly arranged in a plurality of stacked pairs (see Yeong fig. 11A);
growing an epitaxial layer (Yeong fig. 11A, 88; see [0047]; epitaxial source/drain regions 88 are grown in source/drain openings 84 around LDD regions 82 and on portions of each of the channel regions 58) on each horizontal channel layer in the source trench and in the drain trench;
depositing a sacrificial material (Yeong fig. 12A, 92; see [0053]: dummy layers 92 are formed on and around epitaxial source/drain regions 88 in the source trench and in the drain trench) in the source trench and in the drain trench;
forming a replacement metal gate structure (see Yeong fig. 16A and [0059]-[0060]; gate dielectrics 102 and gate electrodes 104 are formed for replacement gates; [0060] confirms that gate electrodes 104 are composed of a metal-containing material; fig. 16A shows that this replacement metal gate structure is formed on a top surface of the uppermost channel region 58 which is included in the superlattice structure) having a first portion (portion at a height of element 80) on a top surface of the superlattice structure, and a second portion surrounding the plurality of horizontal channel layers (portion at a height below element 80, see Fig. 19A);
opening a contact trench (Yeong fig. 17A, 106; see [0062]; source/drain contact openings 106 are formed adjacent gate dielectrics 102 and gate electrodes 104; contact openings 106 extend to a top surface of dummy layers 92) adjacent the first portion of the replacement metal gate structure, the contact trench extending to a top surface of the sacrificial material (see Yeong fig. 17A);
selectively removing the sacrificial material through the contact trench (see Yeong fig. 18A and [0062]-[0063]; source/drain contact openings 106 expose the dummy layers 92, and the dummy layers are subsequently removed to expose the epitaxial source/drain regions 88); and
filling the contact trench, the source trench, and the drain trench with a metal fill layer (Yeong fig. 19A, 112A; see fig. 19C and [0065]: lower source/drain contacts 112A include a metallic conductive material that is deposited in the source/drain contact openings 106 and around silicides 108 in spaces where the source/drain openings 84 were previously located (compare Yeong fig. 8A and fig. 19A)) to form a source region (see annotated Yeong fig. 19A above; the indicated portion of the epitaxial source/drain regions 88 coupled with the silicides 108 act as a source region) and a drain region (see annotated Yeong fig. 19A above; the indicated portion of the epitaxial source/drain regions 88 coupled with silicides 108 act as a drain region) adjacent the superlattice structure, wherein the source region and the drain region comprise a metallic silicide material (see Yeong fig. 19A and [0064]; the silicides 108 are formed by annealing a conformal metal layer deposited on epitaxial source/drain regions 88; thus, the source region and drain region both comprise a metallic silicide material).
Yeong fails to disclose a non-transitory computer readable medium including instructions, that, when executed by a controller of a processing chamber, causes the processing chamber to perform the disclosed method; the sacrificial material selected from the group consisting of aluminum oxide (AIOx), silicon oxide (SiOx), and silicon oxycarbide (SiOC); forming a conformal layer of silicide on each epitaxial layer, the conformal layer of silicide surrounding each epitaxial layer and a portion of the inner spacers.
Colombeau discloses a multi-chamber processing tool (Colombeau fig. 1, 100) used to fabricate horizontal gate all around field effect transistors (hGAA FETs) (see Colombeau fig. 13A and [0017]). The multi-chamber processing tool includes processing chambers (Colombeau fig. 1: 120, 122, 124, 126, 128, and 130) to perform various fabrication processes such as but not limited to wafer cleaning, etching, and epitaxial growth (see Colombeau [0027]). The multi-chamber processing tool is controlled by a system controller (Colombeau fig. 1, 190) which includes a non-transitory computer-readable medium (Colombeau fig. 1, 194; see [0029]: the memory 194 is a non-transitory computer-readable medium) and a CPU (Colombeau fig. 1, 192) for executing computer instruction code stored in the memory (see Colombeau [0029]). The system controller controls the processing chambers to perform processes in accordance with hGAA FET manufacturing methods (see Colombeau [0028]-[0029]).
The multi-chamber processing tool of Colombeau is configured to perform the method of Yeong wherein the combination discloses a non-transitory computer readable medium (Colombeau fig. 1, 194) including instructions (see Colombeau [0029]: the system controller 190 includes a CPU 192 which executes computer instruction code stored in memory 194), that, when executed by a controller of a processing chamber (Colombeau fig. 1, 190; see [0028]: system controller 190 directly controls the various processing chambers in the processing tool), causes the processing chamber (Colombeau fig. 1, 130) to perform the disclosed method of Yeong.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the multi-chamber processing tool of Colombeau to perform the method of Yeong to both increase manufacturing output and increase device reliability by reducing manufacturing errors.
Yeong and Colombeau do not explicitly disclose the sacrificial material selected from the group consisting of aluminum oxide (AIOx), silicon oxide (SiOx), and silicon oxycarbide (SiOC); forming a conformal layer of silicide on each epitaxial layer, the conformal layer of silicide surrounding each epitaxial layer and a portion of the inner spacers.
Wang discloses a method of forming a semiconductor device (Wang fig. 1) that involves the sacrificial material selected from the group consisting of aluminum oxide (AIOx), silicon oxide (SiOx), and silicon oxycarbide (SiOC) (see [0024]: “the dummy source/drain feature 222 may have a composition similar to that of the sacrificial layers 206”; then see [0015] which notes that epitaxial layers 206 include silicon carbide) forming a conformal layer of silicide (Wang fig. 10, 234; see [0032]; silicide layer 234 is conformal to the thin epitaxial features 230 because it is formed from conformal metal layer 232) on each epitaxial layer(Wang fig. 9 230; see [0030]-[0031]).
The silicide layer formation method step of Wang is incorporated with Yeong and Colombeau.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yeong (to be performed by the computer readable medium of Colombeau) with the silicide layer step of Wang to protect the epitaxial layers from contamination or mechanical damage potentially caused by the sacrificial material; and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known specific silicidation step for another to obtain predictable results (see Wang fig. 10 and [0030-0032]).
Yeong, Colombeau, Wang do not disclose the conformal layer of silicide surrounding a portion of the inner spacers.
A1 discloses the conformal layer of silicide surrounding a portion of the inner spacers (see Figs. 3-4 the conformal layer of silicide element 32 surrounding a portion of the inner spacers elements 28, see [0035] “metal silicide or metal germane-silicide wrap-around contact layers 32”; note, due to the metal element 31 covering an entire surface and silicidation of the semiconductor material protruding laterally further than the inner spacers, at least edge portions of the metal which forms the silicide element 32 are surrounding a portion of the inner spacers).
The shape of the silicide as taught by A1 is incorporated as the shape of the silicide of Yeong, Colombeau, Wang.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of A1 with Wang because the combination can provide uniform and conformal doping for reduces contact resistance and thermodynamical benefits from reduced total energy of the system (see A1 [0029]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known silicide shape for another in a similar device to obtain predictable results (see A1 Fig. 4 and see evidentiary reference B1 Figs. 4A-B versus Figs. 4C-D which shows alternatively the silicide element 420 having varied vertical thickness to be non-overlapped or overlapped with the inner spacer elements 110, see [0019-0020])
Conclusion
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/SAMUEL PARK/Examiner, Art Unit 2818
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