DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis.
Drawings
The drawings are objected to because:
the replacement metal gate (118 and 218) is imprecisely indicated in figures 2E-2H and figure 4H. In figures 2E-2H, reference number 118 seems to indicate the contact material (which is also indicated by reference number 120) and not the replacement metal gate. In figure 4H, reference number 218 seems to indicate the contact material (which is also indicated by reference number 220) and not the replacement gate. Therefore, the labeling of the replacement metal gate (118 and 218) in figures 2E-2H and figure 4H should be corrected to match the labeling of the replacement metal gate in figures 2C-2D and figures 4E-4G respectively.
in figures 2C-2H, reference number 104 (nanosheet channel layer(s)) labels a structure which the examiner understands to be the replacement metal gate (reference number 118). A similar inconsistency exists in figures 4E-4H concerning reference numbers 204 and 218. It is, therefore, unclear from the drawings which elements correspond to the nanosheet channel layers and which element corresponds to the replacement metal gate. The drawings should be corrected to clearly show both of these structures.
In paragraph [0063] of the instant specification, it is disclosed that “a source/drain material 126 is selectively grown in the source/drain trench 124 adjacent to the semiconductor material layers 106”. Furthermore, in paragraph [0058] it is disclosed that “the plurality of semiconductor material layers 106 are selectively etched between the plurality of horizontal channel layers 104 in the superlattice structure 108” (with an analogous disclosure in [0085] concerning semiconductor material layers 206 and horizontal channel layers 204). If it is intended that the epitaxial source/drain material (126 and 226) be grown adjacent to the semiconductor material layers (106 and 206), then figure 2G should be corrected to show this. If it is instead intended that the epitaxial source/drain material (126 and 226) be grown adjacent to the horizontal channel layers (104 and 204), then figure 2H and figures 4B-4H should be corrected accordingly. The examiner would also like to point out that the labeling of the semiconductor material layers (106 and 206) and the horizontal channel layers (104 and 204) appears reversed in all relevant figures; if this is the case, then the reference numbers for these elements should be swapped accordingly in all relevant figures before the aforementioned inconsistencies are corrected.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0050], the line stating “the plurality of nanosheet channel layers 104 comprising silicon germanium (SiGe), and the plurality of semiconductor materials layers comprise silicon (Si)” should be corrected to “the plurality of nanosheet channel layers 104 comprise silicon germanium (SiGe), and the plurality of semiconductor materials layers comprise silicon (Si)”.
In paragraph [0063], it is disclosed that “a source/drain material 126 is selectively grown in the source/drain trench 124 adjacent to the semiconductor material layers 106”. However, an earlier paragraph ([0058]) discloses that the semiconductor material layers 106 are selectively removed through etching. Is it intended, instead, that source/drain material 126 be grown adjacent to horizontal channel layers 104? If so, paragraph [0063] of the disclosure should be corrected accordingly.
In paragraph [0071], the line stating “FIGS. 4A-4H are the fabrication steps of operations 52 through 64 in FIG. 3” should be corrected to “FIGS. 4A-4H are the fabrication steps of operations 52 through 66 in FIG. 3” (in accordance with figure 3).
In paragraph [0079], it is disclosed that “a source/drain material 226 is selectively grown in the source/drain trench 215a/215b adjacent to the semiconductor material layers 206”. However, a later paragraph ([0085]) discloses that the semiconductor material layers 206 are selectively removed through etching. Is it intended, instead, that source/drain material 126 be grown adjacent to horizontal channel layers 204? If so, paragraph [0079] of the disclosure should be corrected accordingly.
Also in paragraph [0079], the line stating “In one or more embodiments, the source/drain material 126 comprises silicon germanium (SiGe), silicon germanium doped with boron (SiGeB), silicon phosphorus (SiP), silicon phosphorus doped with carbon (SiPC), germanium (Ge), germanium doped with boron (GeB)” should be corrected to “In one or more embodiments, the source/drain material 226 comprises silicon germanium (SiGe), silicon germanium doped with boron (SiGeB), silicon phosphorus (SiP), silicon phosphorus doped with carbon (SiPC), germanium (Ge), germanium doped with boron (GeB)” (in accordance with figure 4B).
In paragraph [0084], the line stating “on the sidewalls of the superlattice structure 108” should be corrected to “on the sidewalls of the superlattice structure 208” (in accordance with figure 4D).
In paragraph [0092], the line disclosing “In one or more embodiments, the growth of the source/drain material (operations 56 and 58), the replacement gate formation (operation 60), the opening of the contact trench (operation 62), and the filling of the contact trench (operation 64)” should be corrected to “In one or more embodiments, the growth of the source/drain material (operations 56 and 58), the replacement gate formation (operation 62), the opening of the contact trench (operation 64), and the filling of the contact trench (operation 66)” (in accordance with figure 3).
In paragraph [0093], the line stating “the deposition of the sacrificial material 116” should be changed to “the deposition of the sacrificial material 216” (in accordance with figures 4D-4F).
Appropriate correction is required.
Claim Objections
Claims 6, 15, and 17, are objected to because of the following informalities: the instant claims read “comprises one of more” but should be corrected to read “comprises one or more”. Appropriate correction is required.
Claim 17 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 15. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim 20 is objected to because of the following informalities: the instant claim reads “conformal layer of silicide layer” but should be corrected to “conformal layer of silicide”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claims 1-8 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 recites “forming a source region and a drain region adjacent the replacement metal gate structure”. However, in paragraph [0063] of the instant specification, it is disclosed that “a source/drain material 126 is selectively grown in the source/drain trench 124 adjacent to the semiconductor material layers 106”. With the current claim language, the location on which the source/drain material is selectively grown is unclear. In figure 2H, the majority of each epitaxial source/drain region seems to be formed adjacent to the regions labeled 106 which are disclosed to be semiconductor material layers. In order for this device to be functional, the epitaxial source/drain regions must be electrically coupled to nanosheet channel regions of the superlattice (or else charge carriers will not flow in the on-state). The locations and functions of both the semiconductor material layers and the horizontal channel layers are largely unclear from the disclosure, so the examiner will interpret the aforementioned claim limitation of claim 1 to require that the source region and drain region be formed adjacent to the horizontal channel layers within the source and drain trenches respectively. Is this consistent with what the applicant regards as their invention? If so, the aforementioned limitation of claim 1 should be corrected as follows: forming a source region and a drain region adjacent the horizontal channel layers.
Claim 4 recites “growing an epitaxial layer on the plurality of semiconductor material layers”. Consistent with the reasoning given above for claim 1, the examiner will interpret this limitation to require that an epitaxial layer be grown on the plurality of horizontal channel layers. Therefore, the aforementioned limitation of claim 4 should be corrected as follows: growing an epitaxial layer on the plurality of horizontal channel layers.
Claims 14-17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 14 recites “growing an epitaxial layer on the plurality of semiconductor material layers in the source trench and in the drain trench prior to depositing the sacrificial material”. The inconsistency noted above regarding the semiconductor material layers and the horizontal channel layers and the functional requirements of the device suggest that this limitation should instead require that the epitaxial layer (included in the source region and the drain region) be grown on the plurality of horizontal channel layers. Is this interpretation consistent with what the applicant intends to claim? If so, the aforementioned limitation of claim 14 should be corrected to recite “growing an epitaxial layer on the plurality of horizontal channel layers in the source trench and in the drain trench prior to depositing the sacrificial material”.
Claim 20 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 20 recites “grow an epitaxial layer on the plurality of semiconductor material layers in the source trench and in the drain trench”. The inconsistency noted above regarding the semiconductor material layers and the horizontal channel layers and the functional requirements of the device suggest that this limitation should instead require that the epitaxial layer be grown on the plurality of horizontal channel layers. Is this interpretation consistent with what the applicant intends to claim? If so, the aforementioned limitation of claim 20 should be corrected to recite “grow an epitaxial layer on the plurality of horizontal channel layers in the source trench and in the drain trench”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
PNG
media_image1.png
603
791
media_image1.png
Greyscale
PNG
media_image2.png
601
909
media_image2.png
Greyscale
Claims 1-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (US 20210305393 A1), hereinafter referred to as “Wang”.
Regarding claim 1, Wang discloses a method of forming a semiconductor device (figure 1), the method comprising: forming a source trench (figure 4, 218; see [0022]) and a drain trench (see figure 4, [0020], and [0022]; [0020] discloses that “the fin structure 205 also includes source/drain regions 205SD that are disposed on both sides [of] the channel region 205C along the X direction”. Thus, all of the fabrication steps performed on the region 205SD shown in figures 2-12 (see [0006]) are also performed similarly in a region opposite the channel region 205C despite not being shown in the drawings. Therefore, the examiner will regard the region 205SD shown in figures 2-12 as the source zone and the implied region 205SD on the opposite side of 205C (not shown) as the drain zone. Accordingly, a drain recess is formed in the opposite region 205SD analogous to the source recess 218 (see [0022])) adjacent to a superlattice structure (figure 4, 204) on a substrate (figure 4, 202; see [0014]), the superlattice structure comprising a plurality of horizontal channel layers (figure 4, 208; see [0015]-[0016] and note that the stack 204 (comprising channel layers 208 and sacrificial layers 206) in figure 2 is the same stack 204 shown in figure 4 except for the source and drain trenches) and a corresponding plurality of semiconductor material layers (figure 4, 206; see [0015]-[0016] and note that the stack 204 (comprising channel layers 208 and sacrificial layers 206) in figure 2 is the same stack 204 shown in figure 4 except for the source and drain trenches) alternatingly arranged in a plurality of stacked pairs (see figure 4 and [0016]);
depositing a sacrificial material (figure 6, 222; see [0024]; also note that [0020] implies that a dummy source/drain feature is also deposited in the drain recess in the opposite region 205SD (not shown)) in the source trench and in the drain trench;
forming a replacement metal gate structure (figure 6, 226; see [0026]-[0028]; figure 6 shows that the functional gate structure 226 is formed on the top surface of stack 204 in the channel region 205C) on a top surface of the superlattice structure;
opening a contact trench (figure 7, 228; see [0029]; figure 7 shows that source/drain opening 228 is formed in second dielectric layer 224 adjacent functional gate structure 226; source/drain opening 228 extends to a top surface of the dummy source/drain feature 222; note that [0020] implies that a source/drain opening is also formed above the drain recess in the opposite region 205SD (not shown)) adjacent the replacement metal gate structure, the contact trench extending to a top surface of the sacrificial material; selectively removing the sacrificial material through the contact trench (see figure 8 and [0029]; dummy source/drain feature 222 is selectively removed through the source/drain opening 228 to form a bottom opening 228B; note that [0020] implies that a similar dummy source/drain feature is also selectively removed through a source/drain opening in the opposite region 205SD (not shown));
forming a source region (figure 9, 230; see [0030]-[0031]: epitaxial source/drain feature 230 is formed adjacent to channel members 208) and a drain region (see figure 9, figure 12, and [0030]-[0031]; [0020] implies that an analogous epitaxial source/drain feature is formed adjacent to channel members 208 within the drain recess in the opposite region 205SD (not shown); this analogous feature acts as a drain region, and its location is shown in figure 12) adjacent the horizontal channel layers (applicant is reminded of the 112(b) rejection of claim 1 above);
and filling the contact trench (figure 9, 228T; see [0029]: top opening 228T is identical to the source/drain opening 228 shown in figure 7), the source trench (figure 9, 228B; see [0024] and [0029]: the dummy source/drain feature 222 is formed in source recess 218, and bottom opening 228B is formed in the same location after dummy source/drain feature 222 is selectively removed; thus source/drain recess 218 and bottom opening 228B denote the same trench), and the drain trench (see figure 9 and [0020]; [0020] implies that an opening analogous to the bottom opening 228B (shown in figure 9) is also formed in the same location as the drain recess in the opposite region 205SD (not shown); figure 12 shows the metal fill layers disposed within the drain opening) with a metal fill layer (figures 11-12, 236 and 238; see [0033]-[0034]: metal source/drain feature 236 and source/drain contact 238 are formed using the same metal material).
Regarding claim 2, Wang discloses the method of claim 1, wherein the sacrificial material (figure 6, 222) comprises one or more of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), aluminum oxide (AIOx), silicon oxide (SiOx), silicon oxycarbide (SiOC) (see [0024]: dummy source/drain feature is formed of silicon germanium (SiGe))
Regarding claim 3, Wang discloses the method of claim 2, wherein the sacrificial material (figure 6, 222) has a thickness in a range of from 2 nm to 50 nm (see figure 7, figure 9, and [0029]-[0030]; the bottom opening 228B is formed in the space formerly occupied by dummy source/drain feature 222 before it is selectively removed. Thus, the dimensions of bottom opening 228B and dummy source/drain feature 222 are effectively identical. In [0030], it is disclosed that the thickness T2 of the bottom opening 228B is between about 15 nm and 25 nm).
Regarding claim 4, Wang discloses the method of claim 1, wherein forming the source region (see figures 9-10 and [0030]-[0032]; the source region comprises epitaxial source feature 230 and silicide layer 234) and the drain region (see figures 9-10, figure 12, and [0030]-[0032]; [0020] implies that an analogous region (comprising an epitaxial drain feature and a silicide layer) is formed adjacent to channel members 208 in the opposite region 205SD (not shown); this analogous region acts as a drain region, and its location is shown in figure 12) comprises
growing an epitaxial layer (figure 9, 230; see [0030]) on the plurality of horizontal channel layers (figure 5, 208; applicant is reminded of the 112b rejection of claim 4 above) in the source trench (figure 9, 228B) and in the drain trench (see figure 9 and [0020]; [0020] implies that an opening analogous to the bottom opening 228B (shown in figure 9) is formed in the opposite region 205SD (not shown) and that an analogous epitaxial source/drain feature is formed in that opening; refer to figure 12) and
forming a conformal layer of silicide (figure 10, 234; see [0032] and figure 12: silicide layer 234 is disposed on epitaxial feature 230, and figure 12 shows that silicide layer 234 is conformal in that it has a thickness that is about the same over the epitaxial feature 230) on the epitaxial layer.
Regarding claim 5, Wang discloses the method of claim 1, wherein the metal fill layer (figures 11-12, 236 and 238; see [0033]-[0034]) comprises one or more of cobalt (Co), molybdenum (Mo), ruthenium (Ru), and tungsten (W) (figures 11-12, 236 and 238; see [0033]-[0034]: both the metal source/drain feature 236 and the source/drain contact 238 are comprised of cobalt (Co)).
Regarding claim 6, Wang discloses the method of claim 4, wherein the epitaxial layer (figure 9, 230) comprises one or more of silicon germanium (SiGe), silicon germanium doped with boron (SiGeB), silicon phosphorus (SiP), silicon phosphorus doped with carbon (SiPC), germanium (Ge), and germanium doped with boron (GeB) (see [0031]: epitaxial source/drain feature 230 is comprised of silicon germanium (SiGe)).
Regarding claim 7, Wang discloses the method of claim 1, wherein the plurality of semiconductor material layers (figure 4, 206) and the plurality of horizontal channel layers (figure 4, 208) independently comprise one or more of silicon germanium (SiGe) and silicon (Si) (see [0023]: channel layers 208 consist essentially of silicon (Si) and sacrificial layers 206 consist essentially of silicon germanium (SiGe)).
Regarding claim 8, Wang discloses the method of claim 1, wherein the replacement metal gate structure (figure 6, 226) comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and titanium aluminum (TiAI) (see [0028]: the gate electrode of the functional gate structure 226 is comprised of titanium nitride (TiN)).
PNG
media_image3.png
572
1078
media_image3.png
Greyscale
PNG
media_image4.png
668
1017
media_image4.png
Greyscale
Claims 9-10 and 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeong et al. (US 20220262911 A1), hereinafter referred to as “Yeong”.
Regarding claim 9, Yeong discloses a method of forming a semiconductor device (see figures 2-23 and [0005]-[0007]), the method comprising:
forming a source region (see annotated figure 19A above; the indicated portion of the epitaxial source/drain regions 88 coupled with the silicides 108 act as a source region) and a drain region (see annotated figure 19A above; the indicated portion of the epitaxial source/drain regions 88 coupled with silicides 108 act as a drain region) adjacent a superlattice structure (see figure 19A and [0047]: figure 7A shows nanostructure stack 56; epitaxial source/drain regions 88 are grown adjacent to a superlattice structure which comprises what is left of nanostructure stack 56 (see figure 7A) after the source/drain openings 84 (see [0043]) and the replacement gates (see [0059] are formed) on a substrate (figure 19A, 50), the superlattice structure comprising a plurality of horizontal channel layers (figure 19A, 58) and a corresponding plurality of semiconductor material layers (figure 11A, 56A; see [0058]-[0060]: first nanostructures 56A are replaced by replacement gates (comprising gate dielectrics 102 and gate electrodes 104 as shown in figure 19A)) alternatingly arranged in a plurality of stacked pairs (see figure 11A), wherein the source region and the drain region comprise a metallic silicide material (see figure 19A and [0064]; the silicides 108 are formed by annealing a conformal metal layer deposited on epitaxial source/drain regions 88; thus, the source region and drain region both comprise a metallic silicide material).
Regarding claim 10, Yeong discloses the method of claim 9, wherein forming the source region (see annotated figure 19A above; the indicated portion of the epitaxial source/drain regions 88 coupled with silicides 108 act as a source region) and the drain region (see annotated figure 19A above; the indicated portion of the epitaxial source/drain regions 88 coupled with silicides 108 act as a drain region) comprises:
forming a source trench (see annotated figure 8A and [0043]; the indicated source trench includes source/drain openings 84) and a drain trench (see annotated figure 8A and [0043]; the indicated drain trench includes source/drain openings 84) adjacent to the superlattice structure (see figure 8A; the superlattice structure comprises the channel regions 58 stacked alternatingly with first nanostructures 56A under the dummy gate 74) on the substrate (figure 8A, 50);
depositing a sacrificial material (figure 12A, 92; see [0053]: dummy layers 92 are formed within source/drain openings 84 (i.e. in both the source trench and the drain trench)) in the source trench and in the drain trench;
forming a replacement metal gate structure (see figure 16A and [0059]-[0060]; gate dielectrics 102 and gate electrodes 104 are formed for replacement gates; [0060] confirms that gate electrodes 104 are composed of a metal-containing material; figure 16A shows that this replacement metal gate structure is formed on a top surface of the uppermost channel region 58 which is included in the superlattice structure) on a top surface of the superlattice structure;
opening a contact trench (figure 17A, 106; see [0062]; figure 17A shows that source/drain contact openings 106 are formed adjacent gate dielectrics 102 and gate electrodes 104; contact openings 106 extend to a top surface of dummy layers 92) adjacent the replacement metal gate structure, the contact trench extending to a top surface of the sacrificial material; selectively removing the sacrificial material through the contact trench (see figure 18A and [0062]-[0063]; source/drain contact openings 106 expose the dummy layers 92, and the dummy layers are subsequently removed to expose the epitaxial source/drain regions 88);
and filling the contact trench, the source trench, and the drain trench with a metal fill layer (figure 19A, 112A; see figure 19C and [0065]: lower source/drain contacts 112A include a metallic conductive material that is deposited in the source/drain contact openings 106 and around silicides 108 in spaces where the source/drain openings 84 were previously located (compare figure 8A and figure 19A)).
Regarding claim 13, Yeong discloses the method of claim 10, wherein the metal fill layer (figure 19A, 112A; see [0065]) comprises one or more of cobalt (Co), molybdenum (Mo), ruthenium (Ru), and tungsten (W) (see [0065]: lower source/drain contacts 112A include a conductive material which is comprised of cobalt).
Regarding claim 14, Yeong discloses the method of claim 10, wherein forming the source region (see annotated figure 19A above; the indicated portion of the epitaxial source/drain regions 88 coupled with silicides 108 act as a source region) and the drain region (see annotated figure 19A above; the indicated portion of the epitaxial source/drain regions 88 coupled with silicides 108 act as a drain region) further comprises:
growing an epitaxial layer (figure 11A, 88; see [0047]; figure 11A shows that epitaxial source/drain regions 88 are grown in source/drain openings 84 on portions of channel regions 58) on the plurality of horizontal channel layers (figure 11A, 58; applicant is reminded of the 112(b) rejection of claim 14 above) in the source trench (see annotated figure 8A and 8C above and figure 11A; source/drain regions 88 are grown on portions of channel regions 58 within the source trench which includes source/drain openings 84) and in the drain trench (see annotated figure 8A and 8C above and figure 11A; source/drain regions 88 are grown on portions of channel regions 58 within the drain trench which includes source/drain openings 84) prior to depositing the sacrificial material (figure 12A, 92; see [0053]: dummy layers 92 are formed on and around epitaxial source/drain regions 88 which implies that the source/drain regions are formed prior to the formation of the dummy layers 92);
and forming a conformal layer of silicide (figure 19A, 108; see [0064]: silicides 108 are formed by annealing a metal layer that is conformally deposited on epitaxial source/drain regions 88) on the epitaxial layer.
Regarding claim 15, Yeong discloses the method of claim 14, wherein the epitaxial layer (figure 11A, 88) comprises one or more of silicon germanium (SiGe), silicon germanium doped with boron (SiGeB), silicon phosphorus (SiP), silicon phosphorus doped with carbon (SiPC), germanium (Ge), and germanium doped with boron (GeB) (see [0048]-[0049]; epitaxial source/drain regions 88 are comprised of silicon germanium (SiGe)).
Regarding claim 16, Yeong discloses the method of claim 14, wherein the metal fill layer (figure 19A, 112A; see [0065]) comprises one or more of cobalt (Co), molybdenum (Mo), ruthenium (Ru), and tungsten (W) (see [0065]: lower source/drain contacts 112A include a conductive material which is comprised of cobalt (Co)).
Regarding claim 17 (applicant is reminded of the objection to claim 17 described above), Yeong discloses the method of claim 14, wherein the epitaxial layer (figure 11A, 88) comprises one or more of silicon germanium (SiGe), silicon germanium doped with boron (SiGeB), silicon phosphorus (SiP), silicon phosphorus doped with carbon (SiPC), germanium (Ge), and germanium doped with boron (GeB) (see [0048]-[0049]; epitaxial source/drain regions 88 are comprised of silicon germanium (SiGe)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yeong in view of Wang.
PNG
media_image1.png
603
791
media_image1.png
Greyscale
Regarding claim 11, Yeong discloses the method of claim 10.
Yeong fails to disclose wherein the sacrificial material comprises one or more of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), aluminum oxide (AIOx), silicon oxide (SiOx), silicon oxycarbide (SiOC).
Wang discloses a method of forming a gate-all-around device (Wang figure 1) wherein a sacrificial material (Wang figure 6, 222; see [0024]) is formed in a source trench (Wang figure 4, 218) and a drain trench (see Wang figure 2, figure 4, and [0020]; [0020] discloses that “the fin structure 205 also includes source/drain regions 205SD that are disposed on both sides the channel region 205C along the X direction”. Thus, all of the fabrication steps performed on the region 205SD in Wang that are shown in figures 2-12 (see Wang [0006]) are also performed similarly in a region opposite the channel region 205C despite not being shown in the drawings. Therefore, the examiner will regard the region 205SD shown in figures 2-12 as the source zone and the implied region 205SD on the opposite side of 205C (not shown) as the drain zone. A drain recess is formed in the opposite region 205SD analogous to the source recess 218) and wherein the sacrificial material comprises one or more of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), aluminum oxide (AIOx), silicon oxide (SiOx), silicon oxycarbide (SiOC) (see Wang [0024]: dummy source/drain features 222 are comprised of silicon germanium (SiGe)).
The sacrificial material of Wang is incorporated as the sacrificial material for the method of Yeong (Yeong figure 12A, 92; see [0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yeong with the sacrificial material of Wang so that the sacrificial material can be selectively removed without damaging the dielectric layers, spacers, and channel regions (see Wang [0024]); and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the sacrificial material of Yeong (Yeong figure 12A, 92; see [0053]) with the sacrificial material of Wang (Wang figure 6, 222; see [0024]) to obtain predicable results (see Wang [0024]).
Regarding claim 12, Yeong discloses the method of claim 10.
Yeong fails to disclose wherein the sacrificial material has a thickness in a range of from 2 nm to 50 nm.
Wang discloses a method of forming a gate-all-around device (Wang figure 1) wherein a sacrificial material (Wang figure 6, 222; see [0024]) is formed in a source trench (Wang figure 4, 218) and a drain trench (see Wang figure 2, figure 4, and [0020]; [0020] discloses that “the fin structure 205 also includes source/drain regions 205SD that are disposed on both sides the channel region 205C along the X direction”. Thus, all of the fabrication steps performed on the region 205SD in Wang that are shown in figures 2-12 (see Wang [0006]) are also performed similarly in a region opposite the channel region 205C despite not being shown in the drawings. Therefore, the examiner will regard the region 205SD shown in figures 2-12 as the source zone and the implied region 205SD on the opposite side of 205C (not shown) as the drain zone. A drain recess is formed in the opposite region 205SD analogous to the source recess 218) and wherein the sacrificial material (Wang figure 6, 222; see [0024]) has a thickness in a range of from 2 nm to 50 nm (see Wang figure 7, figure 9, figure 12, and [0029]-[0030]; the bottom opening 228B is formed in the space formerly occupied by dummy source/drain feature 222 before it is selectively removed. Thus, the dimensions of bottom opening 228B and those of dummy source/drain feature 222 are effectively identical. Wang [0030] discloses that the thickness T2 of the bottom opening 228B, which extends across region 205SD (see Wang figure 12), is between about 15 nm and 25 nm).
The sacrificial material of Wang (with its associated dimensions) is incorporated as the sacrificial feature taught in Yeong (Yeong figure 12A, 92) wherein the combination discloses wherein the sacrificial material has a thickness in a range of from 2 nm to 50 nm. Note that the space occupied by the dummy source/drain feature 222 of Wang is similar in shape to the space occupied by the dummy layers 92 of Yeong (see Yeong figures 12A and 12C and compare with Yeong figures 11A and 11C; see Yeong [0053 ]: “The dummy layers 92 fill the remaining portions of the source/drain openings 84 that are not filled by the epitaxial source/drain regions 88”; note that dummy layers 92 fill the entire space around source/drain regions 88), so the substitution of dummy layers 92 in the semiconductor device fabrication method of Yeong with the dummy source/drain feature 222 of Wang (with its associated dimensions) is valid.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yeong with the sacrificial material of Wang to better protect source/drain features and channel layers during replacement gate and dielectric layer formation; and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the sacrificial material of Yeong (Yeong figure 12A, 92; see [0053]) with the sacrificial material of Wang (Wang figure 6, 222; see [0024]) to obtain predicable results (see Wang [0024]).
PNG
media_image1.png
603
791
media_image1.png
Greyscale
PNG
media_image2.png
601
909
media_image2.png
Greyscale
PNG
media_image5.png
660
616
media_image5.png
Greyscale
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Colombeau et al. (US 20200152493 A1), hereinafter referred to as “Colombeau”.
Regarding claim 18, Wang discloses a method of forming a semiconductor device (Wang figure 1) comprising: forming a source region (see Wang figures 9-10, figure 12, and [0030]-[0032]; the source region comprises epitaxial source/drain region 230 and silicide layer 234) and a drain region (see Wang figures 9-10, figure 12, [0020], and [0030]-[0032]; [0020] discloses that “the fin structure 205 also includes source/drain regions 205SD that are disposed on both sides the channel region 205C along the X direction”. Thus, all of the fabrication steps performed on the region 205SD in Wang that are shown in figures 2-12 (see Wang [0006]) are also performed similarly in a region opposite the channel region 205C despite not being shown in the drawings. Therefore, the examiner will regard the region 205SD shown in figures 2-12 as the source zone and the implied region 205SD on the opposite side of 205C (not shown) as the drain zone. A region analogous to the source region (comprising an epitaxial source/drain feature and a silicide layer) is formed adjacent to channel members 208 in the opposite region 205SD (not shown); this analogous region acts as a drain region, and its location is shown in figure 12) adjacent a superlattice structure (Wang figure 5, 204; stack 204 is included in channel region 205C in Wang figure 9) on a substrate (Wang figure 9, 202), the superlattice structure comprising a plurality of horizontal channel layers (Wang figure 5, 208; see [0015]-[0016] and note that the stack 204 (comprising channel layers 208 and sacrificial layers 206) in figure 2 is the same stack 204 shown in figure 5 except for the source and drain trenches and the inner spacer features 220) and a corresponding plurality of semiconductor material layers (Wang figure 5, 206; see [0015]-[0016] and note that the stack 204 (comprising channel layers 208 and sacrificial layers 206) in figure 2 is the same stack 204 shown in figure 5 except for the source and drain trenches and the inner spacer features 220) alternatingly arranged in a plurality of stacked pairs (see Wang figure 5: channel layers 208 and sacrificial layers 206 are alternatingly arranged in a plurality of stacked pairs within stack 204), wherein the source region and the drain region comprise a metallic silicide material (see Wang [0032]: the silicide layer is formed by annealing a metal layer 232 deposited on the surfaces of epitaxial source/drain region 230; [0020] implies that silicide layer 234 is formed on both sides of channel region 205C; thus, the source region and drain region both comprise a metallic silicide material).
Wang fails to disclose a non-transitory computer readable medium including instructions, that, when executed by a controller of a processing chamber, causes the processing chamber to perform the operations of: form a source region and a drain region adjacent a superlattice structure on a substrate, the superlattice structure comprising a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs, wherein the source region and the drain region comprise a metallic silicide material.
Colombeau discloses a multi-chamber processing tool (Colombeau figure 1, 100) used to fabricate horizontal gate all around field effect transistors (hGAA FETs) (see Colombeau figure 13A and [0017]). The multi-chamber processing tool includes processing chambers (Colombeau figure 1: 120, 122, 124, 126, 128, and 130) to perform various fabrication processes such as but not limited to wafer cleaning, etching, and epitaxial growth (see Colombeau [0027]). The multi-chamber processing tool is controlled by a system controller (Colombeau figure 1, 190) which includes a non-transitory computer-readable medium (Colombeau figure 1, 194; see [0029]: the memory 194 is a non-transitory computer-readable medium) and a CPU (Colombeau figure 1, 192) for executing computer instruction code stored in the memory (see Colombeau [0029]). The system controller controls the processing chambers to perform processes in accordance with hGAA FET manufacturing methods (see Colombeau [0028]-[0029]).
The multi-chamber processing tool of Colombeau is configured to perform the semiconductor device fabrication method of Wang wherein the combination discloses a non-transitory computer readable medium (Colombeau figure 1, 194) including instructions (see Colombeau [0029]: the system controller 190 includes a CPU 192 which executes computer instruction code stored in memory 194), that, when executed by a controller of a processing chamber (Colombeau figure 1, 190; see [0028]: system controller 190 directly controls the various processing chambers in the processing tool), causes the processing chamber (Colombeau figure 1, 130) to perform the operations of: form a source region and a drain region adjacent a superlattice structure on a substrate, the superlattice structure comprising a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs, wherein the source region and the drain region comprise a metallic silicide material.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the multi-chamber processing tool of Colombeau to perform the semiconductor device fabrication method of Wang to both increase manufacturing output and increase device reliability by reducing manufacturing errors.
Regarding claim 19, Wang and Colombeau disclose the non-transitory computer readable medium of claim 18, that causes the processing chamber (Colombeau figure 1, 130) to perform the further operations of:
form a source trench (Wang figure 4, 218; see [0022]) and a drain trench (see Wang figure 4, [0020], and [0022]; [0020] implies that a drain recess similar to source recess 218 is formed in the opposite region 205SD (not shown). This recess is a drain trench) adjacent to the superlattice structure (Wang figure 4, 204) on the substrate (Wang figure 4, 202);
deposit a sacrificial material (Wang figure 6, 222; see Wang [0024]: dummy source/drain feature 222 is formed in source/drain recess 218; note that Wang [0020] implies that a dummy source/drain feature is analogously formed in a drain recess in the opposite region 205SD (not shown)) in the source trench and in the drain trench;
form a replacement metal gate structure (Wang figure 6, 226; see Wang [0026]-[0028]; figure 6 shows that the functional gate structure 226 is formed on the top surface of stack 204 in the channel region 205C) on a top surface of the superlattice structure;
open a contact trench (Wang figure 7, 228; figure 7 shows that source/drain opening 228 is formed in second dielectric layer 224 adjacent functional gate structure 226; source/drain opening 228 extends to a top surface of the dummy source/drain feature 222; note that Wang [0020] implies that a source/drain opening is also formed above the drain trench in the opposite region 205SD (not shown)) adjacent the replacement metal gate structure, the contact trench extending to a top surface of the sacrificial material;
selectively remove the sacrificial material through the contact trench (see Wang figure 8 and [0029]; dummy source/drain feature 222 is selectively removed through the source/drain opening 228 to form a bottom opening 228B; note that Wang [0020] implies that a dummy/source drain feature is also selectively removed through a source/drain opening in the opposite region 205SD (not shown));
and fill the contact trench (Wang figure 9, 228T; see Wang [0029]: top opening 228T is identical to source/drain opening 228 shown in figure 7), the source trench (Wang figure 9, 228B; see Wang [0024] and [0029]: the dummy source/drain feature 222 is formed in source/drain recess 218, and bottom opening 228B is formed in the same location after dummy source/drain feature 222 is selectively removed; thus source/drain recess 218 and bottom opening 228B denote the same trench), and the drain trench (see Wang figure 9 and [0020]; [0020] implies that an opening analogous to the bottom opening 228B (shown in figure 9) is also formed in the opposite region 205SD (not shown)) with a metal fill layer (Wang figures 11-12, 236 and 238; see Wang [0033]-[0034]).
Regarding claim 20, Wang and Colombeau disclose the non-transitory computer readable medium of claim 19, that causes the processing chamber (Colombeau figure 1, 130) to perform the further operations of:
grow an epitaxial layer (Wang figure 9, 230; see [0030]: epitaxial source/drain features 230 are formed on the sidewalls of the channel members 208) on the plurality of horizontal channel layers (Wang figure 5, 208; applicant is reminded of the 112(b) rejection of claim 20 above) in the source trench (Wang figure 9, 228B) and in the drain trench (see Wang figure 9 and [0020]; [0020] implies that an opening analogous to the bottom opening 228B (shown in figure 9) is formed in the opposite region 205SD (not shown) and that an analogous epitaxial source/drain feature is formed in that opening; this is shown in Wang figure 12);
and form a conformal layer of silicide (Wang figure 10, 234; see Wang [0032]) on the epitaxial layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNER F COLLINS whose telephone number is (571)272-5187. The examiner can normally be reached M-F, 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at (571)272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HAMNER FITZHUGH COLLINS IV/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818