DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/21/2023 and 11/15/2024 were filed before the first action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-10, 12, 15 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uzoh et al. (2020/0051937). Re claim 1, Uzoh teaches a method of bonding substrates (Fig. 1), the method comprising: forming a first conductive feature (110) on a first substrate (104), comprising: depositing a conductive base layer (110) on the first substrate (104), the first substrate (104) having an opening formed therein (Fig. 1A); recessing (112) the conductive base layer (110) in the opening (Fig. 1B); and depositing a conductive surface layer (114) on the recessed conductive base layer (110); and hybrid bonding [48] the first substrate (104) to a second substrate without an intervening adhesive to connect the first conductive feature on the first substate and a second conductive feature on the second substrate ([48], Fig. 1E).
Re claim 3, Uzoh teaches the method of claim 1, wherein forming the first conductive feature further comprises: prior to depositing the conductive surface layer (114), removing an overburden of the conductive base layer using a first polishing process [32].
Re claim 4, Uzoh teaches the method of claim 3, wherein forming the first conductive feature further comprises: removing an overburden of the conductive surface layer using a second polishing process [31-32].
Re claim 5, Uzoh teaches the method of claim 4, wherein the second polishing process is different from the first polishing process [31-32].
Re claim 6, Uzoh teaches the method of claim 5, wherein: the first polishing process uses a first pad with a first hardness [31-32]; the second polishing process uses a second pad with a second hardness [31-32]; and the first hardness is greater than the second hardness [31-32]. Re claim 7, Uzoh teaches the method of claim 1, wherein the conductive base layer (110) is recessed by a depth from about 100 nm to about 500 nm [61-62]. Re claim 8, Uzoh teaches the method of claim 1, wherein the conductive base layer is recessed by a depth of less than about 25 nm [61-62].
Re claim 9, Uzoh teaches the method of claim 1, wherein the conductive surface layer (114) is deposited using a physical vapor deposition (PVD) process [40-42].
Re claim 10, Uzoh teaches the method of claim 1, wherein the conductive base layer is formed using electroplating [40-42].
Re claim 12, Uzoh teaches the method of any of claim 1, wherein depositing the conductive surface layer further comprises: concurrent with the PVD process, maintaining the first substrate at a temperature below about 100°C [35].
Re claim 15, Uzoh teaches the method of claim 1, wherein, prior to the hybrid bonding, the first conductive feature (110) is substantially co-planar with a surface of the first substrate (108, Fig. 1A).
Re claim 17, Uzoh teaches the method of claim 1, wherein the second conductive feature is recessed from a surface of the second substrate ([34], Fig. 1). Re claim 18, Uzoh teaches the method of claim 1, wherein the second conductive feature is formed by substantially the same method as the first conductive feature ([34], Fig. 1). Re claim 19, Uzoh teaches the method of claim 1, wherein: the hybrid bonding comprises directly bonding the conductive surface layer of the first conductive feature to a single conductive layer of the second conductive feature ([34], Fig. 1); and forming the second conductive feature comprises forming the single conductive layer on the second substrate using the same method as used to form the conductive base layer on the first substrate [34].
Re claim 20, Uzoh teaches the method claim 1, wherein the hybrid bonding comprises: contacting the first substrate and the second substrate to form a workpiece (118, ([48], Fig. 1E); and heating the workpiece to a temperature less than about 300°C [48].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh et al. (2020/0051937) in view of the following reasons.
Re claim 13, Uzoh teaches the method of claim 1. Uzoh does not explicitly teach wherein depositing the conductive surface layer further comprises: concurrent with the PVD process, maintaining the first substrate at a temperature below about 50°C.
However, Applicant has not shown wherein depositing the conductive surface layer further comprises: concurrent with the PVD process, maintaining the first substrate at a temperature below about 50°C has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the substrate temperature so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Re claim 14, Uzoh teaches the method of claim 1. Uzoh does not explicitly teach wherein the conductive surface layer has a surface roughness of less than about 1 nm root mean square (RMS).
However, Applicant has not shown wherein the conductive surface layer has a surface roughness of less than about 1 nm root mean square (RMS) has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the surface roughness so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Allowable Subject Matter
Claims 2, 11 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 2, Uzoh teaches the method of claim 1, yet remains explicitly silent to wherein an average grain size of the conductive base layer is larger than an average grain size of the conductive surface layer. Re claim 11, Uzoh teaches the method of any of claim 1, yet remains explicitly silent to wherein the conductive base layer has a larger grain size than the conductive surface layer.
Re claim 16, Uzoh teaches the method of claim 1, yet remains explicitly silent to wherein, prior to the hybrid bonding, the first conductive feature protrudes above a surface of the first substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897