DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 06/04/2026 have been fully considered but they are not persuasive.
The applicant argues that the prior art fails to teach “a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug under a bottommost surface of the CESL”.
The examiner respectfully submits that the limitation “a bottommost surface of the CESL” is disclosed by the prior art because the CESL layer 296 covers the raised S/D 292, and contact 236 clearly has a width adjacent to the CESL that is less than a width below a bottommost surface. In the case where the S/D is planar instead of raised, the structure would additionally meet a more specific recitation of being wider below the bottommost surface of the CESL, as disclosed by Huang2.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9 – 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang (US 2019/0371898).
Regarding claim 9, Huang teaches (FIG. 7A, 7B):
A semiconductor device, comprising:
a metal gate (226) on a substrate;
a contact etch stop layer (296) (CESL) adjacent to the metal gate;
an interlayer dielectric (297) (ILD) layer around the CESL; and
a first contact plug (236) in the ILD layer, wherein a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug under a bottommost surface of the CESL (FIG. 1A, 7B – the examiner notes that the amendment does not specify the bottommost surface, but rather a bottommost surface).
Regarding claim 10, Huang teaches (FIG. 7A, 7B):
The semiconductor device of claim 9, wherein a width of the first contact plug adjacent to the CESL is less than a width of the first contact plug above the CESL.
Regarding claim 11, Huang teaches (FIG. 7A, 7B):
The semiconductor device of claim 9, wherein a sidewall of the first contact plug comprises a non-planar surface.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2019/0371898) as applied to claim 9 above, and further in view of Huang2 (US 2020/0343135).
Regarding claim 12, Huang teaches undercut source/drain contact regions, but is silent regarding the gate contact:
The semiconductor device of claim 9, further comprising: a first hard mask on the metal gate, wherein top surfaces of the first hard mask and the ILD layer are coplanar; a second hard mask on the first hard mask; and a second contact plug on the metal gate.
However, Huang 2 (FIG. 13) teaches a metal gate structure having an undercut contact (96) along with undercut source/drain contacts (94), the gate having a hard mask (82) coplanar with ILD (60) and a second hard mask (90).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the undercut gate contact structure of Huang2 with the undercut source/drain structure of Huang for the predictable advantage of improving the uniformity of contact performance.
Regarding claim 13, Huang2 teaches (FIG. 13):
The semiconductor device of claim 12, wherein the second contact plug between the first hard mask comprises: a first width closer to the metal gate; and a second width closer to the second hard mask.
Regarding claim 14, Huang2 teaches (FIG. 13):
The semiconductor device of claim 13, wherein the second width is less than the first width.
Regarding claim 15, Huang2 teaches (FIG. 13):
The semiconductor device of claim 12, wherein a sidewall of the second contact plug comprises a non-planar surface.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 2898
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