DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species I, claims 1, and 7 – 12 in the reply filed on 06/11/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, and 7 – 9, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yuan et al. (US 2017/0338203).
Regarding claim 1, Yuan teaches (FIG. 15):
A semiconductor device, comprising:
at least one dielectric layer, comprising a stacked structure comprising a low-k dielectric layer (110a) and an etching stop layer (106a);
a conductive structure (148), disposed in the at least one dielectric layer;
a conductive layer (122), disposed in the stacked structure, between the low-k dielectric layer and the etching stop layer; and
a first insulator (140) disposed between the conductive layer and the conductive structure.
Regarding claim 7, Yuan teaches:
The semiconductor device according to claim 1, wherein a dielectric constant of the low-k dielectric layer (low-k) is smaller than a dielectric constant of the etching stop layer (Silicon dioxide).
Regarding claim 8, Yuan teaches:
The semiconductor device according to claim 1, wherein a thickness of the first insulator is between 50 angstroms and 300 angstroms ([0040]).
Regarding claim 9, Yuan teaches:
The semiconductor device according to claim 1, wherein the conductive layer comprises a semiconductor material or a metal material ([0025]).
Regarding claim 12, Yuan teaches:
The semiconductor device according to claim 1, further comprising:
a substrate (104a);
a gate structure, disposed on the substrate ([0015]); and
a plug surrounded by an interlayer dielectric layer on the substrate, below the at least one dielectric layer, wherein the plug directly contacts the conductive structure (FIG. 15).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan et al. (US 2017/0338203) as applied to claim 1 above, and further in view of Babich et al. (US 2002/0158337).
Regarding claim 10, Yuan fails to expressly disclose multiple similar stacked dielectric layers:
The semiconductor device according to claim 1, further comprising:
a plurality of the dielectric layers stacked on one over another; and
a plurality of the conductive structures, respectively disposed in the plurality of the dielectric layers, wherein each of the plurality of the dielectric layers comprises the conductive layer disposed in a middle thereof, and
the first insulator is disposed between the conductive layer and each of the conductive structures.
However, Babich teaches a conventional device having multiple metal wiring layers of similar structure.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form additional dielectric and metal layers of similar structure to that disclosed by Yuan to enable any desired circuit design and electrical connectivity as disclosed in a conventional design taught by Babich.
Additionally, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 11, Yuan fails to expressly disclose multiple similar stacked dielectric layers:
The semiconductor device according to claim 1, further comprising:
a plurality of the dielectric layers stacked on one over another; and
a plurality of the conductive structures, respectively disposed in the plurality of the dielectric layers, wherein one of the plurality of the dielectric layers comprises the conductive layer disposed in a middle thereof, and
the first insulator disposed between the conductive layer and the conductive structure disposed in the one of the plurality of dielectric layers.
However, Babich teaches a conventional device having multiple metal wiring layers of similar structure, with air gaps only is some layers.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form additional dielectric and metal layers of similar structure to that disclosed by Yuan to enable any desired circuit design and electrical connectivity as disclosed in a conventional design taught by Babich.
Additionally, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2006/0160353 – teaches modifying portions of a semiconductive SiC layer to form a dielectric at the interface with a conductive plug structure
US 2015/0104938 – teaches modifying a portion of a metal layer to form a dielectric at the interface with a conductive plug structure
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 3624
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