DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The previously issued drawing objection is hereby withdrawn in view of the
amended drawing.
Applicant’s arguments, see Page 9, filed 04/20/2026, with respect to amended claims 7 and 11, and originally presented claim 8 have been fully considered and are persuasive. The rejections of claims 7, 8 and 11 have been withdrawn.
Applicant's arguments filed 04/2026, regarding claims 3, 4, and 14 have been fully considered but they are not persuasive.
As to claim 3, Applicant argues (see Page 8) that prior art Tsai fails to teach the first gate dielectric layer along each of the sidewalls of the first opening. Prior art Wu teaches the first gate dielectric layer along each of the sidewalls. Examiner notes the claim language does not state the gate dielectric layer needs to extend entirely from top to bottom along each of the sidewalls.
As to claim 4, Applicant argues (see top of Page 9) that prior art Tsai fails to teach the channel layer contacts the bottom of the first opening and is surrounded by the first gate dielectric. Examiner disagrees, ⁋ [0030] of Tsai states the gate dielectric layer 114 extends in a first and second direction around sacrificial layer 108, which later is replaced with the channel 122.
As to claim 14, Applicant argues (see Page 11) that prior art the channel layer as taught by Xiao is different from the channel layer of the instant invention. In response to Applicant's argument, the channel layers would not need to be identical as they both are channel layers and have the same function thus it would be obvious for one of ordinary skill to make the modification. The rationale to support a conclusion that the claim would have been obvious is that "a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103."KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Applicant’s arguments with respect to claim(s) 1 and 5 have been considered but are
moot in view of new grounds of rejection.
Additionally, to claim 1, Applicant argues (see bottom of Page 10) that the recess as taught by Wu is different from the opening of the present application. Examiner notes that the claim language as recited only states “defining and opening” and makes no mention to the technique nor structure of the opening.
Claim Rejections - 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "wherein removing portions of the second spacer layer, the first gate layer, the first spacer layer, and the first semiconductor layer" in lines 13-14. A patterning process is previously mentioned to occur on the aforementioned layers but it is not previously mentioned if the patterning process is removing any portion of said layers. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4, 6, 9-10, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2021/0265358 A1), hereafter “Tsai”, and in view of Wu et al. (US 2021/0399052 A1), hereafter “Wu”, and further in view of Chen (US 2021/0408267 A1), hereafter “Chen”.
As to claim 1, Tsai teaches a method for manufacturing a semiconductor structure, comprising:
sequentially forming a first semiconductive layer (106, Fig. 2B, ⁋ [0028], “doped polysilicon”), a first spacer layer (110, Fig. 2B, ⁋ [0029]), a first gate layer (114) and a second spacer layer (116) over a substrate (100, ⁋ [0028]);
defining a first opening (121, ⁋ [0033], see annotated Fig. 2D below) penetrating the first semiconductive layer, the first spacer layer, the first gate layer and the second spacer layer; and
sequentially forming a first gate dielectric (114), a channel layer (122) within the first opening.
Tsai fails to teach defining a first opening penetrating the first semiconductor layer, and sequentially forming a first gate dielectric layer, a second gate dielectric layer and a second gate layer within the first opening.
Chen teaches a method for preparing a similar device (⁋ [0001]) wherein an opening is defined penetrating a bottom source/drain structure i.e. semiconductor layer (143a2+143a1+143b1+143b2, Fig. 14, ⁋⁋ [0067]-[069]). Examiner notes that Tsai teaches it’s semiconductor layer 106 as a source/drain layer (⁋ [0028]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of an opening penetrating a source/drain layer as taught by Chen into the method of Tsai as this particular known technique was recognized as part of the ordinary capabilities of one skilled in the art.
Tsai and Chen fail to teach sequentially forming a first gate dielectric layer, a second gate dielectric layer and a second gate layer within the first opening.
Wu teaches a method of making a similar device with a first gate dielectric layer (108, ⁋⁋ [0055]-[0056], “chalcogenide”), a channel (110, ⁋ [0035]), a second gate dielectric layer (112), and a second gate (114).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply Wu’s teaching of the formation of the gate dielectrics, additional gate and channel to the method of Tsai and Chen to form the vertical channel stackable in vertical direction to realize a 3D memory device, thereby increasing the memory density (⁋ [0094]).
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As to claim 3, Tsai in view of Wu teach the method of Claim 1, Wu teaches wherein the formation of the first gate dielectric layer comprises:
depositing a first dielectric material lining a bottom and two sidewalls of (Fig. 6, 108’, ⁋ [0030]) the first opening; and
removing a portion of the first dielectric material at the bottom of the first opening to form the first gate dielectric layer along each of the sidewalls of the first opening (108) (⁋ [0031])
As to claim 4, Tsai in view of Wu teach the method of Claim 3, Tsai further teaches wherein the channel layer (122) contacts the bottom of the first opening (Fig. 2D) and is surrounded by the first gate dielectric layer (114) (Fig. 1B, ⁋ [0030])
As to claim 6, Tsai in view of Wu teach the method of Claim 5, Tsai teaches further comprising:
forming a second semiconductive layer (124, ⁋ [0033], Fig. 2D) over the channel material, and
Wu teaches defining a second opening penetrating the second semiconductive layer and stopping in the channel material to form the channel layer (⁋ [0037], “an etching process, such as an etching back process, is performed” comparable to second opening).
Examiner notes the combination of Tsai in view of Wu would teach that forming the opening in the channel layer taught by Wu would also need to penetrate the first semiconductor layer taught by Tsai.
As to claim 9, Tsai in view of Wu teaches the method of Claim 6, Wu further teaches wherein the formation of the second gate dielectric layer comprises:
depositing a second dielectric material (⁋ [0038], “a dielectric material is deposited on the top surface of the stack structure ST and fills in the through holes 105 to cover sidewalls of the channel layer 110 and the bottom surfaces of the through holes 105.”) lining the second opening to form the second gate dielectric layer. Examiner notes the second dielectric material 112 lines the second opening.
As to claim 10, Tsai in view of Wu teaches the method of Claim 9, Wu teaches wherein a thickness of the second gate dielectric layer at a bottom of the second opening is substantially equal to a thickness of the second dielectric layer at a sidewall of the second opening (Fig. 8A shows 112 the same thickness at the bottom of the opening as the sidewall thickness).
As to claim 15, Tsai in view of Wu teaches the method of Claim 1, Wu teaches wherein the first gate layer or the second gate layer (114) includes aluminum (Al) (⁋ [0036]), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbon nitride (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tungsten nitride (WN), or combinations thereof.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai, in view of Chen and Wu, and further in view of Sills et al. (US 2022/0416088 A1), hereafter “Sills”.
As to claim 5, Tsai in view of Wu teach the method of Claim 1, Wu teaches wherein the formation of the channel layer comprises:
depositing a channel material filling the first opening after the formation of the first gate dielectric layer (Fig. 7A to Fig. 8A shows the channel 110 being formed after the first gate dielectric 108).
Tsai in view of Wu fail to teach wherein a top surface of the channel material is coplanar with a top surface of the first gate dielectric layer.
Sills teaches a similar device wherein the top surface of a channel pillar (122, Fig. 14A, ⁋ [0067]) is coplanar with a top surface of the linear oxide structures (114, ⁋⁋ [0034], [0067]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the coplanar surfaces as taught by Sills into the method of Tsai and Wu for the benefit of creating a an even top layer utilized for the accurate building of subsequent layers.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai and Wu, as applied to claim 1, and further in view of Xiao et al. (US 2023/0363136 A1), hereafter “Xiao”.
As to claim 14, Tsai in view of Wu teach the method of Claim 1, but fail to teach wherein the channel layer includes indium gallium zinc oxide (IGZO).
Xiao teaches a similar vertical transistor where the channel region is composed of IGZO (⁋⁋ [0080], [0158]; 13, Fig. 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the IGZO as taught by Xiao into the method of Tsai and Wu because the stack device has the advantages of fast access speed, low cut-off current, and low power consumption (⁋ [0158]).
Allowable Subject Matter
Claims 7, 8 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 7 (from which 8 depends), Tsai in view of Wu are the closest prior arts and fail to teach wherein the second gate layer has an upper portion disposed above the second semiconductor layer.
As to claim 11, Tsai in view of Wu are the closest prior arts and fail to teach wherein a top surface of the second gate layer is above the top surface of the first gate dielectric layer.
Claim 2 may be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 2, Tsai in view of Wu are the closest prior arts and fail to teach wherein removing portions of the second spacer layer, the first gate layer, the first spacer layer, and the first semiconductive layer are concurrently removed by an etching operation using a same mask, such that the first opening has a uniform width.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARNELL HUNTER whose telephone number is (571)270-1796. The examiner can normally be reached Monday - Friday 7:30 am - 4:30pm.
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/CARNELL HUNTER III/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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