DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
The IDS document(s) filed on 02/20/2024, 09/24/2024, 07/31/2025, and 11/11/2025 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Drawing Objection
The drawings are objected to because Applicant’s Fig. 6 should indicate reference character 241 in place of reference character 131, and reference character 121 in place of reference character 241. Reference character 131 does not appear anywhere in Applicant’s specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-10, 12-13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2021/0265358 A1), hereafter “Tsai”, and further in view of Wu et al. (US 2021/0399052 A1), hereafter “Wu”.
As to claim 1, Tsai teaches a method for manufacturing a semiconductor structure, comprising:
sequentially forming a first spacer layer (110, Fig. 2B, ⁋ [0029]), a first gate layer (114) and a second spacer layer (116) over a substrate (100, ⁋ [0028]);
defining a first opening (121, ⁋ [0033], see annotated Fig. 2D below) penetrating the first spacer layer, the first gate layer and the second spacer layer; and
sequentially forming a first gate dielectric (114), a channel layer (122) within the first opening.
Tsai fails to teach sequentially forming a first gate dielectric layer, a second gate dielectric layer and a second gate layer within the first opening.
Wu teaches a method of making a similar device with a first gate dielectric layer (108, ⁋⁋ [0055]-[0056], “chalcogenide”), a channel (110, ⁋ [0035]), a second gate dielectric layer (112), and a second gate (114).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply Wu’s teaching of the formation of the gate dielectrics, additional gate and channel to the method of Tsai to form the vertical channel stackable in vertical direction to realize a 3D memory device, thereby increasing the memory density (⁋ [0094]).
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As to claim 2, Tsai in view of Wu teaches the method of Claim 1, Tsai teaches further comprising:
performing a patterning operation on the first spacer layer, the first gate layer and the second spacer layer (⁋ [0029]).
As to claim 3, Tsai in view of Wu teach the method of Claim 1, Wu teaches wherein the formation of the first gate dielectric layer comprises:
depositing a first dielectric material (Fig. 6, 108’, ⁋ [0030]) lining the first opening; and
removing a portion of the first dielectric material at a bottom of the first opening to form the first gate dielectric layer (108) (⁋ [0031]).
As to claim 4, Tsai in view of Wu teach the method of Claim 3, Wu further teaches wherein the channel layer (110) contacts the bottom of the first opening (Fig. 8A).
As to claim 5, Tsai in view of Wu teach the method of Claim 1, Wu teaches wherein the formation of the channel layer comprises:
depositing a channel material filling the first opening after the formation of the first gate dielectric layer (Fig. 7A to Fig. 8A shows the channel 110 being formed after the first gate dielectric 108).
As to claim 6, Tsai in view of Wu teach the method of Claim 5, Tsai teaches further comprising:
forming a first semiconductive layer (124, ⁋ [0033], Fig. 2D) over the channel material, and
Wu teaches defining a second opening penetrating the first semiconductive layer and stopping in the channel material to form the channel layer (⁋ [0037], “an etching process, such as an etching back process, is performed” comparable to second opening).
Examiner notes the combination of Tsai in view of Wu would teach that forming the opening in the channel layer taught by Wu would also need to penetrate the first semiconductor layer taught by Tsai.
As to claim 7, Tsai in view of Wu teach the method of Claim 6, Wu teaches wherein the formations of the second gate dielectric layer and the second gate layer comprise:
depositing a second dielectric material (⁋ [0038], “a dielectric material is deposited on the top surface of the stack structure ST and fills in the through holes 105 to cover sidewalls of the channel layer 110 and the bottom surfaces of the through holes 105.”) filling the second opening;
defining a third opening (⁋ [0038], “an etching process, such as an etching back process, is performed” comparable to third opening) in the second dielectric material to form the second gate dielectric layer; and
depositing a gate material filling the third opening to form the second gate layer (⁋ [0038], “a conductive material is deposited over the stack structure ST and filling the remaining portions of the through holes”).
As to claim 8, Tsai in view of Wu teach the method of Claim 7, but fail to teach wherein a thickness of the second gate dielectric layer at a bottom of the second opening is greater than a thickness of the second gate dielectric layer at a sidewall of the second opening.
On the other hand, shape, size, and dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Note In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
As to claim 9, Tsai in view of Wu teaches the method of Claim 6, Wu further teaches wherein the formation of the second gate dielectric layer comprises:
depositing a second dielectric material (⁋ [0038], “a dielectric material is deposited on the top surface of the stack structure ST and fills in the through holes 105 to cover sidewalls of the channel layer 110 and the bottom surfaces of the through holes 105.”) lining the second opening to form the second gate dielectric layer. Examiner notes the second dielectric material 112 lines the second opening.
As to claim 10, Tsai in view of Wu teaches the method of Claim 9, Wu teaches wherein a thickness of the second gate dielectric layer at a bottom of the second opening is substantially equal to a thickness of the second dielectric layer at a sidewall of the second opening (Fig. 8A shows 112 the same thickness at the bottom of the opening as the sidewall thickness).
As to claim 12, Tsai in view of Wu teaches the method of Claim 1, Tsai teaches further comprising:
forming a second semiconductive material (106, ⁋ [0028]) over the substrate prior to the formation of the first spacer layer (Fig. 2A).
As to claim 13, Tsai in view of Wu teach the method of Claim 12, Tsai teaches wherein the first opening (121) stops on the second semiconductive material (106) (Fig. 2D).
As to claim 15, Tsai in view of Wu teaches the method of Claim 1, Wu teaches wherein the first gate layer or the second gate layer (114) includes aluminum (Al) (⁋ [0036]), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbon nitride (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tungsten nitride (WN), or combinations thereof.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai and Wu, as applied to claim 6, and further in view of Liu (US 2019/0123061 A1), hereafter “Liu”.
As to claim 11, Tsai in view of Wu teach the method of Claim 6, but fail to teach wherein a top surface of the second gate layer is above a top surface of the first semiconductive layer.
Liu teaches a method of forming a similar device comprising of an outer dielectric layer (21, Fig. 2+Fig. 3, ⁋ [0042]), a surrounding channel layer (22), an inner dielectric layer, 23, a conductive core gate column (24), a source layer/semiconductor layer (SL(1), ⁋⁋ [0032], [0040]), with an insulating layer (11, ⁋ [0034]), and wherein the gate 24 extends beyond the surface of the semiconductor layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Liu to extend the second gate layer beyond the surface of the semiconductor within the method of Tsai and Wu for the purpose of electrically connecting to the corresponding one of the control gates (⁋ [0052]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai and Wu, as applied to claim 1, and further in view of Xiao et al. (US 2023/0363136 A1), hereafter “Xiao”.
As to claim 14, Tsai in view of Wu teach the method of Claim 1, but fail to teach wherein the channel layer includes indium gallium zinc oxide (IGZO).
Xiao teaches a similar vertical transistor where the channel region is composed of IGZO (⁋⁋ [0080], [0158]; 13, Fig. 8).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the IGZO as taught by Xiao into the method of Tsai and Wu because the stack device has the advantages of fast access speed, low cut-off current, and low power consumption (⁋ [0158]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARNELL HUNTER whose telephone number is (571)270-1796. The examiner can normally be reached Monday - Friday 7:30 am - 4:30pm.
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/CARNELL HUNTER III/ Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893