Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/379,928 filed on 10/13/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2012/0286363 to Ando et al. (Ando).
Regarding independent claim 1, Ando discloses a method of manufacturing an electronic device (Fig. 7), the method comprising:
depositing an interfacial layer (Fig. 7: region 502 of 102) on a top surface of a channel (Although the channel region is not explicitly labeled, in a field-effect transistor structure the channel is the portion of the semiconductor substrate located between the source and drain regions through which current flows under applied bias. One of ordinary skill in the art would recognize that the semiconductor surface region between S and D inherently constitutes the channel region. Accordingly, the top surface of the substrate between the source and drain corresponds to the claimed “top surface of a channel.”) located between a source (S) and a drain (D) on a semiconductor substrate (Fig. 7: 100);
depositing a high-K dielectric layer (104) on the interfacial layer;
depositing a titanium nitride (TiN) layer (106) on the high-K dielectric layer;
depositing a metal film or a metal nitride film (108) on the titanium nitride (TiN) layer; and
depositing a capping layer (113) on the metal film or the metal nitride film.
Regarding claim 2, Ando discloses wherein the interfacial layer (102) comprises silicon oxide (SiOx) (¶0012).
Regarding claim 4, Ando discloses wherein the high-K dielectric layer (104) comprises one or more of hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx) (¶0012).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2012/0286363 to Ando et al. (Ando).
Regarding claim 3, Ando teaches the method of claim 1 (see the rejection of claim 1 above).
Ando fails to explicitly disclose wherein the interfacial layer has a thickness in a range of from 8 Å to 11Å.
However, Ando teaches that the thickness of the interfacial layer is variable which when changed, allows for different respective stacks, having different electrical properties, while maintaining the same overall thickness (¶0016). This is to improve the scalability and performance of the devices (¶0003). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to vary, through routine experimentation, the result effect variable of the thickness of the interfacial layer in order to optimize the functionality of the device (see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 5, Ando teaches the method of claim 1 (see the rejection of claim 1 above).
Ando fails to explicitly disclose wherein the high-K dielectric layer has a thickness in a range of from 10 Å to 20 Å.
However, Ando teaches that the thickness of the high-K dielectric layer is variable which when changed, allows for different respective stacks, having different electrical properties, while maintaining the same overall thickness (¶0016). This is to improve the scalability and performance of the devices (¶0003). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to vary, through routine experimentation, the result effect variable of the thickness of the high-K dielectric layer in order to optimize the functionality of the device (see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 15, Ando teaches depositing the metal film or metal nitride film by an atomic layer deposition (ALD) process (see e.g., ¶0016). However, Ando does not explicitly describe exposing the semiconductor substrate to a pulse of a metal-containing precursor and a pulse of a reactant. It would have been obvious to one of ordinary skill in the art at the time of the invention to implement the disclosed ALD process using sequential pulses of a metal-containing precursor and a reactant because pulsed, alternating precursor exposure is the conventional and well-understood manner in which ALD processes are performed. ALD is a cyclic deposition technique characterized by sequential, self-limiting surface reactions achieved by temporally separated precursor and reactant pulses. Employing such pulsed exposure represents no more than the predictable use of a known ALD process according to its established operating principles.
Therefore, modifying the ALD deposition of Ando to explicitly include exposure to pulses of a metal-containing precursor and a reactant would have been an obvious implementation of the disclosed ALD technique and would have yielded no unexpected results.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2012/0286363 to Ando et al. (Ando) in view of US Pub # 2011/0195549 to Chuang et al. (Chuang).
Regarding claim 6, Ando discloses depositing an aluminum (Al) layer as a metal film (108) or the titanium nitride (TiN) layer as a metal nitride film (110). However, it does not expressly disclose that the aluminum layer or the metal nitride film comprises a multilayer film.
Chuang teaches forming a multi-layer metal nitride stack in a field-effect transistor gate structure, including TiN/TaN multilayer configurations (¶0018 discloses a capping layer e.g., a first capping layer 216 and a second capping layer 218).
It would have been obvious to one of ordinary skill in the art to modify the TiN layer of Ando to comprise a multilayer metal nitride film as taught by Chuang in order to optimize work function tuning, adhesion, and electrical performance, since such multilayer stacks were known in HKMG technology (¶0002).
Regarding claim 7, Ando discloses wherein the electronic device comprises the metal film (108) and the metal film is selected from one or more of titanium (Ti), aluminum (Al), germanium (Ge), tantalum (Ta), zirconium (Zr), strontium (Sr), barium (Ba), or a lanthanide series metal (¶0013).
Regarding claim 8, Ando discloses wherein the electronic device comprises the metal nitride film (110) and the metal nitride film is selected from one or more of titanium nitride (TiN), aluminum nitride (AIN), germanium nitride (GeN), tantalum nitride (TaN), zirconium nitride (ZrN), strontium nitride (SrN), barium nitride (BaN), or a nitride of a lanthanide series metal (0013).
Claims 9-12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2012/0286363 to Ando et al. (Ando) in view of US Pub # 2011/0195549 to Chuang et al. (Chuang) and further in view of CN106340452 to Yu (English translation of CN106340452 has been provided by the applicant).
Regarding claim 9, Ando as previously modified discloses forming metal and metal nitride films in a MOSFET gate structure, including aluminum (Al) and titanium nitride (TiN) layers. However, Ando as previously modified do not expressly teach that the metal/metal nitride film comprises a multilayer film having a first layer of aluminum nitride (AlN) with aluminum (Al) on the AlN.
Yu discloses a metal gate structure in which a first aluminum nitride (AlN) layer is formed in the gate opening and subsequently filled with a metal aluminum (Al) layer disposed on the AlN layer, thereby teaching the claimed multilayer film comprising AlN and Al. It would have been obvious to a person of ordinary skill in the art to modify the metal/metal nitride films of the Ando as previously modified to include the AlN/Al multilayer structure as taught by Yu in order to optimize barrier properties and work function characteristics in a MOSFET gate structure, as such multilayer combinations were known in the art.
Regarding claim 10, Ando as previously modified teaches the method of claim 9 (see the rejection of claim 9 above).
Ando as previously modified fails to explicitly disclose wherein the first layer has a thickness in a range of from 5 Å to 12 Å and the second layer has a thickness in a range of from 5 Å to 12 Å.
However, the thickness of the first layer and the second layer affect the thickness of the package. It is known in the art to use thickness. It would have been obvious to one of ordinary skill in the art at the time of the invention to vary, through routine experimentation, the result effect variable of the thickness of the first layer and the second layer in order to optimize the functionality of the device (see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 11, Ando as previously modified teaches a method of forming a gate stack including an interfacial layer, a high-K dielectric layer, a titanium nitride layer, and a metal or metal nitride layer as recited in claim 1. Chuang teaches that the metal film or metal nitride film may comprise a multilayer film including a first layer of aluminum nitride (AlN) and a second layer of aluminum (Al), having thicknesses within the ranges recited in claims 9 and 10.
Claim 11 further recites that the multilayer film reduces the thickness of the interfacial layer by scavenging unbound oxygen from the interfacial layer and the high-K dielectric layer.
It is well understood in the art that aluminum-containing layers in high-K gate stacks act as oxygen scavenging layers and are capable of reducing the thickness of an interfacial oxide layer by reacting with and removing oxygen from adjacent dielectric materials. The reduction of interfacial layer thickness is a known and predictable result of incorporating reactive aluminum layers in metal gate stacks.
Therefore, in combining the multilayer AlN/Al film of Chuang with the gate stack of Ando, the resulting structure would have been necessary capable of scavenging oxygen and reducing the thickness of the interfacial layer as a predictable property of the aluminum-containing multilayer film. The recited functional language merely describes the necessary result of the obvious structural combination and does not patentably distinguish over the applied prior art.
Regarding claim 12, Ando as previously modified teaches the method of claim 11 (see the rejection of claim 11 above).
Ando as previously modified fails to explicitly disclose wherein the multilayer film reduces the thickness of the interfacial layer by 0.15 Å to 1.5 Å.
However, the thickness of the interfacial layer affect the thickness of the package. It is known in the art to use thickness. It would have been obvious to one of ordinary skill in the art at the time of the invention to vary, through routine experimentation, the result effect variable of the thickness of the interfacial layer in order to optimize the functionality of the device (see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 16, Ando as previously modified teaches the method of claim 11 (see the rejection of claim 11 above). Ando additionally discloses annealing the semiconductor substrate at a temperature of less than or equal to 1050 °C (¶0016). The recitation “to accelerate the scavenging” merely states the intended result of the annealing step. Annealing necessary increases diffusion and reaction kinetics and therefore necessary accelerates impurity scavenging processes. Where the prior art and the claimed process are identical or substantially identical, the burden shifts to applicant to show that the prior art does not necessary possess the claimed characteristic. See In re Best, 562 F.2d 1252 (CCPA 1977). Accordingly, the functional language does not distinguish over the prior art. See also MPEP §2111.04.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2012/0286363 to Ando et al. (Ando) in view of US Pub # 2022/0254640 to Yang et al. (Yang).
Regarding claim 13, Ando disclose all of the limitations of claim 1 from which this claim depends.
Ando fails to explicitly discloses wherein the capping layer comprises amorphous silicon (a-Si).
Yang discloses wherein the capping layer (sacrificial layer 150 currently considered to be the capping layer) comprises amorphous silicon (a-Si) (¶0029).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the material of the capping layer of Ando with the capping layer as taught by Yang so as to provide less diffusion of atoms as compared to polycrystalline silicon which include grain boundaries leading path for diffusion (¶0047).
Regarding claim 14, Ando disclose all of the limitations of claim 1 from which this claim depends.
Ando fails to explicitly discloses wherein the capping layer is deposited in situ.
Yang discloses wherein the capping layer is deposited in situ. It was well known in the art to deposit the capping layer in situ (MPEP §2144.03) and it would have been obvious to one of ordinary skill in the art to select a in situ as a mere selection of an art-recognized deposition technique suitable for the intended use of depositing the capping layer in the combined invention (MPEP §2144.07).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2012/0286363 to Ando et al. (Ando) in view of US Pub # 2011/0195549 to Chuang et al. (Chuang) and further in view of US Pub # 2022/0254640 to Yang et al. (Yang).
Regarding independent claim 17, Ando discloses a method of manufacturing an electronic device, the method comprising:
depositing an interfacial layer depositing an interfacial layer (Fig. 7: region 502 of 102) comprising silicon oxide (SiOx) (¶0012) on a top surface of a channel (Although the channel region is not explicitly labeled, in a field-effect transistor structure the channel is the portion of the semiconductor substrate located between the source and drain regions through which current flows under applied bias. One of ordinary skill in the art would recognize that the semiconductor surface region between S and D inherently constitutes the channel region. Accordingly, the top surface of the substrate between the source and drain corresponds to the claimed “top surface of a channel.”) located between a source (S) and a drain (D) on a semiconductor substrate (Fig. 7: 100) on a top surface of a channel located between a source and a drain on a semiconductor substrate;
depositing a high-K dielectric layer (104; ¶0012) comprising hafnium oxide (HfOx) on the interfacial layer;
depositing a titanium nitride (TiN) layer (106; ¶0013) on the high-K dielectric layer;
depositing a metal film or a metal nitride film (108; ¶0013) on the titanium nitride (TiN) layer;
depositing a capping layer (113) on the metal film or the metal nitride film; and
annealing (¶0016) the semiconductor substrate (the resultant structure) at a temperature of less than or equal to 1050 °C to accelerate the scavenging.
Ando fails to explicitly disclose the metal film or the metal nitride film including a multilayer film, the multilayer film reducing the thickness of the interfacial layer by scavenging unbound oxygen from the interfacial layer and the high-K dielectric layer, and a thickness in a range of from 8 Å to 10 Å, and a thickness in a range of from 10 Å to 20 Å, amorphous silicon (a-Si) and a thickness in a range of 0 Å to 20 Å and to accelerate the scavenging.
Chuang teaches forming a multi-layer metal nitride stack in a field-effect transistor gate structure, including TiN/TaN multilayer configurations (¶0018-0020 discloses a capping layer e.g., a first capping layer 216 and a second capping layer 218; see Fig. 6).
It would have been obvious to one of ordinary skill in the art to modify the TiN layer of Ando to comprise a multilayer metal nitride film as taught by Chuang in order to reduce leakage current and improve time dependent dielectric breakdown (TDDB) reliability and to improve overall device reliability and performance (¶0015).
The combinations of Ando and Chuang do not teach an amorphous silicon (-Si) as a capping layer.
Yang teaches wherein the capping layer (sacrificial layer 150 currently considered to be the capping layer) comprises amorphous silicon (a-Si) (¶0029).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have modify the capping layer of Ando with the capping layer as taught by Yang so as to provide less diffusion of atoms as compared to polycrystalline silicon which include grain boundaries leading path for diffusion (¶0047).
Regarding the recitation of “the multilayer film reducing the thickness of the interfacial layer by scavenging unbound oxygen from the interfacial layer and the high-K dielectric layer and to accelerate the scavenging and to accelerate the scavenging.” It is well understood in the art that metal film or a metal nitride film in high-K gate stacks act as oxygen scavenging layers and are capable of reducing the thickness of an interfacial oxide layer by reacting with and removing oxygen from adjacent dielectric materials. The reduction of interfacial layer thickness is a known and predictable result of incorporating reactive metal film or a metal nitride film in metal gate stacks.
Therefore, in combining the multilayer metal film or a metal nitride film of Chuang with the gate stack of Ando, the resulting structure would have been necessary capable of scavenging oxygen and reducing the thickness of the interfacial layer as a predictable property of the metal film or a metal nitride film. The recited functional language merely describes the necessary result of the obvious structural combination and does not patentably distinguish over the applied prior art.
Regarding the claimed thicknesses, Ando does not appear to expressly teach the individually claimed thicknesses of each respective layers. However, Ando teaches that the thickness of the individual layers is variable which when changed, allows for different respective stacks having different electrical properties while maintaining the same overall thickness. This is to allow for device scalability (¶0003), therefore one having ordinary skill in the art would find that these individual thicknesses are result effective variable in order to optimize the functionality of the device (see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2012/0286363 to Ando et al. (Ando) in view of US Pub # 2011/0195549 to Chuang et al. (Chuang) in view of US Pub # 2022/0254640 to Yang et al. (Yang) and further in view of CN106340452 to Yu (English translation of CN106340452 has been provided by the applicant).
Regarding claim 18 Ando as previously modified discloses forming metal and metal nitride films in a MOSFET gate structure, including aluminum (Al) and titanium nitride (TiN) layers. However, Ando as previously modified do not expressly teach that the metal/metal nitride film comprises a multilayer film having a first layer of aluminum nitride (AlN) with aluminum (Al) on the AlN.
Yu discloses a metal gate structure in which a first aluminum nitride (AlN) layer is formed in the gate opening and subsequently filled with a metal aluminum (Al) layer disposed on the AlN layer, thereby teaching the claimed multilayer film comprising AlN and Al. It would have been obvious to a person of ordinary skill in the art to modify the metal/metal nitride films of the Ando as previously modified to include the AlN/Al multilayer structure as taught by Yu in order to optimize barrier properties and work function characteristics in a MOSFET gate structure, as such multilayer combinations were known in the art.
Regarding claim 19, Ando as previously modified teaches the method of claim 18 (see the rejection of claim 18 above).
Ando as previously modified fails to explicitly disclose wherein the first layer has a thickness in a range of from 5 Å to 12 Å and the second layer has a thickness in a range of from 5 Å to 12 Å.
However, the thickness of the first layer and the second layer affect the thickness of the package. It is known in the art to use thickness. It would have been obvious to one of ordinary skill in the art at the time of the invention to vary, through routine experimentation, the result effect variable of the thickness of the first layer and the second layer in order to optimize the functionality of the device (see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 20, Ando as previously modified teaches the method of claim 19 (see the rejection of claim 19 above).
Ando as previously modified fails to explicitly disclose wherein the multilayer film reduces the thickness of the interfacial layer by 0.15 Å to 1.5 Å.
However, the thickness of the interfacial layer affect the thickness of the package. It is known in the art to use thickness. It would have been obvious to one of ordinary skill in the art at the time of the invention to vary, through routine experimentation, the result effect variable of the thickness of the interfacial layer in order to optimize the functionality of the device (see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub # 2008/0290400 to Jenne et al., US Pub # 2009/0212369 to Park et al. and US Pub # 2009/0152636 to Chudzik et al.
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/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896