DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 21, 2026 has been entered.
Information Disclosure Statement
An Information Disclosure Statement has not been entered. Applicant is reminded of the duty to disclose material information under 37 CFR 1.56. If applicant wishes to have an Information Disclosure Statement made of record, please submit form PTO/SB/08, along with any statements and fees required by 37 CFR 1.97, prior to or along with the payment of the issue fee.
Response to Amendment
The amendment filed January 21, 2026 has been entered. Claims 1-5 and 7-20 remain pending in this application. Claim 6 has been cancelled at Applicant’s request. Claims 1, 7-8, 13, 16, and 20 have been amended. No claims have been added. No new matter has been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 7-11, and 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0385672 A1 to Mahmut Sinangil, et al. (hereafter Sinangil) in view of US 2013/0258757 A1 to Sundar Iyer, et al. (hereafter Iyer), US 6,642,744 B2 to Zvi Or-Bach, et al. (hereafter Or-Bach), and US 5,670,897 to Thomas A. Kean (hereafter Kean).
Regarding Amended Independent Claim 1, Sinangil discloses a multi-port memory cell, comprising:
an inverter circuit cell (Inverter circuit 114: Sinangil, Figure 1 and ¶[0023]);
a hold circuit cell having an output coupled to an input of the inverter circuit cell and an input coupled to an output of the inverter circuit cell (A hold circuit cell 102 cross coupled to inverter 114: Sinangil, Figure 1 and ¶[0023]);
multiple unit circuit cells (Disclosing multiple unit circuit cells: Sinangil, Figure 5) having respective tristate drivers (Disclosing a read circuit comprising a tristate driver: Sinangil, Figure 1 and ¶[0024]),
wherein a first plurality of the multiple unit circuit cells are programmed (Note: ‘Program’ does not require software programming but may also be achieved by selective wiring: Specification, ¶[0037]) as read circuit cells having inputs coupled to the output of the inverter circuit cell (Read circuit cell 130 connected to the output of inverter 114: Sinangil, Figure 1 and ¶[0024]) and
a second plurality of the multiple unit circuit cells are programmed as write circuit cells having outputs coupled to an input of the inverter circuit cell (Write circuit 112 coupled to the input of inverter 114: Sinangil, Figure 1 and ¶[0023]).
While Sinangil discloses a multi-port circuit similar to that described in Claim 1, it does not expressly disclose a modular design wherein the circuit parts consist of identical circuit structures. Iyer, however, discloses a multi-port circuit wherein the multiple unit circuit cells have the same circuit structure (Disclosing write and read circuit cells having a standardized circuit structure: Iyer, ¶[0064]). Iyer teaches this allows custom multi-port memory arrays to be quickly designed and efficient without significant monetary costs (Iyer, ¶[0055]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the standardized circuit cells of Iyer with the multi-port circuit architecture of Sinangil, with a reasonable expectation of success. Both inventions are well known in the field of multi-port memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
While Sinangil and Iyer disclose a multi-port circuit similar to that described in Claim 1, they do not expressly disclose a modular design wherein the circuit parts are arranged in a configuration with multiple rows and columns and wherein a number of ports of the multi-port memory cell corresponds to a number of the multiple unit circuit cells. Or-Bach, however, discloses a modular circuit array as in Claim 1:
wherein the inverter circuit cell, the hold circuit cell, and the multiple unit circuit cells are arranged in a configuration with multiple rows and columns (Showing an array of circuits arranged in a configuration of multiple rows and columns: Or-Bach, Figures 1-3), and
wherein a number of ports of the multi-port memory cell corresponds to a number of the multiple unit circuit cells (Disclosing the array including a number of ports corresponding to the inputs and/or outputs of the circuitry: Or-Bach, col. 6:47-54)
Or-Bach teaches the matrix arrangement of identical circuits provides a modular logic array without the requirement of compilation (Or-Bach, col.19:13-18). Or-Bach further discloses the corresponding input/output configuration provides for a permanent customizable interconnect between various ports (Or-Bach, col.15:1-6). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the modular circuit matrix of Or-Bach with the multi-port memory cell of Sinangil, with a reasonable expectation of success. Both inventions are well known in the field of customizable memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
The previously cited prior art does not disclose a first and second node, each including a plurality of traces routed adjacent to the multiple unit circuit cells across the multiple rows or columns, wherein the signals routed from the first and second nodes are complementary. Kean, however, discloses a multi-port memory array wherein:
a first node (A first node: Kean, Figure 7) including a first plurality of traces routed adjacent to the multiple unit circuit cells across the multiple rows or columns (Including a plurality of traces routed adjacent to unit circuit cells across multiple rows or columns: Kean, Figure 4); and
a second node (A second node: Kean, Figure 7) including a second plurality of traces routed adjacent to the multiple unit circuit cells across the multiple rows or columns (Including a plurality of traces routed adjacent to unit circuit cells across multiple rows or columns: Kean, Figure 4),
wherein the second node is configured to route a signal that is complementary to a signal routed by the first node (Wherein the signal of the first and second nodes are complementary: Kean, col.29:6-11).
Kean discloses the principal advantage of this configuration is it can be implemented with standard address decoders without space and time penalties (Kean, col.28:66-29:1) while allowing simultaneous access to circuits (Kean, col.28:30-37). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the efficient matrix addressing system of Kean with the multi-port circuit of Sinangil, with a reasonable expectation of success. Both inventions are well known in the field of multi-port circuits and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2 and the substantially similar limitations of Claim 14, Sinangil discloses the multi-port memory cell of claim 1, wherein
the hold circuit cell comprises a tristate driver (Hold circuit 102 comprises a tristate driver: Sinangil, Figure 1 and ¶[0023]).
Regarding Claim 3 and the substantially similar limitations of Claim 15, Sinangil discloses the multi-port memory cell of claim 2, wherein
the tristate driver of the hold circuit cell is disabled when one of the write circuit cells is enabled (Disclosing a tristate driver where the hold circuit 102 is disabled when write circuit 112 is enabled by WL/WLB: Sinangil, Figure 1).
Regarding Amended Claim 7, Sinangil and Iyer disclose the multi-port memory cell of claim 1, wherein
the first plurality of the multiple unit circuit cells (Disclosing a first plurality of circuit cells: Iyer, Figure 7B)
are programmed as read cells by coupling the first node to an input of the tristate drivers of the first plurality of the multiple unit circuit cells (Disclosing coupling first node 116 to the input 126 of the read tristate driver 122: Sinangil, Figure 1).
Regarding Amended Claim 8, Sinangil discloses the multi-port memory cell of claim 1, wherein
the second plurality of the multiple unit circuit cells (Disclosing a second plurality of circuit cells: Iyer, Figure 7B)
are programmed as write cells by coupling the second node to an output of the tristate drivers of the second plurality of the multiple unit circuit cells (Disclosing coupling second node 108 to the output of the transmission gate 112: Sinangil, Figure 1; Modified by replacing the transmission gate with a tristate driver, as recommended by the StackExchange entry of March 24, 2022).
Regarding Claim 9 and the substantially similar limitations of Claim 17, Sinangil discloses the multi-port memory cell of claim 1, wherein
the first plurality of the multiple unit circuit cells are programmed as read cells (Read cell 122: Sinangil, Figure 1)
by coupling a read dataline to an output of each of the tristate drivers of the first plurality of the multiple unit circuit cells (Read cell 122 connected to Read Bit Line RBL: Sinangil, Figure 1).
Regarding Claim 10 and the substantially similar limitations of Claim 18, Sinangil discloses the multi-port memory cell of claim 1, wherein
the second plurality of the multiple unit circuit cells are programmed as write circuit cells (Write cell 112: Sinangil, Figure 1)
by coupling a write dataline to an input of each of the tristate drivers of the second plurality of the multiple unit circuit cells (Write cell 112 connected to bit line BL: Sinangil, Figure 1).
Regarding Claim 11, Sinangil discloses the multi-port memory cell of claim 1, wherein
the second plurality of the multiple unit circuit cells are programmed as write cells by coupling wordlines to respective enable inputs of the tristate drivers of the second plurality of the multiple unit circuit cells (Write cell 112 controlled by word line WL: Sinangil, Figure 1).
Regarding Amended Independent Claim 13, Sinangil discloses a method for multi-port memory cell processing, comprising:
programming a first plurality of multiple unit circuit cells (Disclosing multiple unit circuit cells: Sinangil, Figure 5)
as read circuit cells by coupling inputs of the first plurality of the multiple unit circuit cells to an output of an inverter circuit cell (Disclosing connecting first node 116 to the input 126 of the read tristate driver 122: Sinangil, Figure 1),
the multiple unit circuit cells comprising respective tristate drivers (Disclosing a read circuit comprising a tristate driver: Sinangil, Figure 1 and ¶[0024]); and
programming a second plurality of the multiple unit circuit cells
as write cells by coupling outputs of the second plurality of the multiple unit circuit cells to an input of the inverter circuit cell (Write circuit 112 coupled to the input of inverter 114: Sinangil, Figure 1 and ¶[0023]),
wherein an output of a hold circuit cell is coupled to an input of the inverter circuit cell and an input of the hold circuit cell is coupled to an output of the inverter circuit cell (A hold circuit cell 102 cross coupled to inverter 114: Sinangil, Figure 1 and ¶[0023]).
While Sinangil discloses a multi-port processing circuit similar to that described in Claim 13, it does not expressly disclose a modular design wherein the circuit parts consist of identical circuit structures. Iyer, however, discloses a multi-port circuit wherein the multiple unit circuit cells have the same circuit structure (Disclosing write and read circuit cells having a standardized circuit structure: Iyer, ¶[0064]). Iyer teaches this allows custom multi-port memory arrays to be quickly designed and efficient without significant monetary costs (Iyer, ¶[0055]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the standardized circuit cells of Iyer with the multi-port circuit architecture of Sinangil, with a reasonable expectation of success. Both inventions are well known in the field of multi-port memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
While Sinangil and Iyer disclose a multi-port processing circuit similar to that described in Claim 13, they do not expressly disclose a modular design wherein the circuit parts are arranged in a configuration with multiple rows and columns and wherein a number of ports of the multi-port memory cell corresponds to a number of the multiple unit circuit cells. Or-Bach, however, discloses a modular circuit array as in Claim 13:
wherein the inverter circuit cell, the hold circuit cell, and the multiple unit circuit cells are arranged in a configuration with multiple rows and columns (Showing an array of circuits arranged in a configuration of multiple rows and columns: Or-Bach, Figures 1-3), and
wherein a number of ports of the multi-port memory cell corresponds to a number of the multiple unit circuit cells (Disclosing the array including a number of ports corresponding to the inputs and/or outputs of the circuitry: Or-Bach, col. 6:47-54)
Or-Bach teaches the matrix arrangement of identical circuits provides a modular logic array without the requirement of compilation (Or-Bach, col.19:13-18). Or-Bach further discloses the corresponding input/output configuration provides for a permanent customizable interconnect between various ports (Or-Bach, col.15:1-6). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the modular circuit matrix of Or-Bach with the multi-port memory cell of Sinangil, with a reasonable expectation of success. Both inventions are well known in the field of customizable memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
The previously cited prior art does not disclose a first and second node, each including a plurality of traces routed adjacent to the multiple unit circuit cells across the multiple rows or columns, wherein the signals routed from the first and second nodes are complementary. Kean, however, discloses a multi-port memory array wherein:
a first node (A first node: Kean, Figure 7) including a first plurality of traces routed adjacent to the multiple unit circuit cells across the multiple rows or columns (Including a plurality of traces routed adjacent to unit circuit cells across multiple rows or columns: Kean, Figure 4); and
a second node (A second node: Kean, Figure 7) including a second plurality of traces routed adjacent to the multiple unit circuit cells across the multiple rows or columns (Including a plurality of traces routed adjacent to unit circuit cells across multiple rows or columns: Kean, Figure 4),
wherein the second node is configured to route a signal that is complementary to a signal routed by the first node (Wherein the signal of the first and second nodes are complementary: Kean, col.29:6-11).
Kean discloses the principal advantage of this configuration is it can be implemented with standard address decoders without space and time penalties (Kean, col.28:66-29:1) while allowing simultaneous access to circuits (Kean, col.28:30-37). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the efficient matrix addressing system of Kean with the multi-port circuit of Sinangil, with a reasonable expectation of success. Both inventions are well known in the field of multi-port circuits and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 16, Sinangil discloses the method of claim 13, wherein:
programming the first plurality of the multiple unit circuit cells as read circuit cells
includes coupling the first node to an input of the tristate drivers of the first plurality of the multiple unit circuit cells (Disclosing coupling first node 116 to the input 126 of the read tristate driver 122: Sinangil, Figure 1); and
programming the second plurality of the multiple unit circuit cells as write circuit cells
includes coupling the second node to an output of the tristate drivers of the second plurality of the multiple unit circuit cells (Disclosing coupling second node 108 to the output of the transmission gate 112: Sinangil, Figure 1).
Regarding Claim 19, Sinangil discloses the method of claim 13, wherein:
programming the second plurality of the multiple unit circuit cells as write circuit cells includes
coupling wordlines to respective enable inputs of the tristate drivers of the second plurality of the multiple unit circuit cells (Write cell 112 controlled by word line WL: Sinangil, Figure 1); and
a tristate driver of the hold circuit cell is configured to be disabled based on signals at the wordlines (Disclosing a tristate driver where the hold circuit 102 is disabled when write circuit 112 is enabled by WL/WLB: Sinangil, Figure 1).
Regarding Amended Independent Claim 20, Sinangil discloses an apparatus for multi-port memory cell processing, comprising:
a memory (Disclosing a memory cell: Sinangil, Figure 1); and
one or more processors coupled to the memory, the one or more processors being configured to:
program a first plurality of multiple unit circuit cells (Disclosing multiple unit circuit cells: Sinangil, Figure 5) as read circuit cells
by coupling inputs of the first plurality of the multiple unit circuit cells to an output of an inverter circuit cell (Disclosing connecting first node 116 to the input 126 of the read tristate driver 122: Sinangil, Figure 1),
the multiple unit circuit cells comprising respective tristate drivers (Disclosing a read circuit comprising a tristate driver: Sinangil, Figure 1 and ¶[0024]); and
program a second plurality of the multiple unit circuit cells as write cells
by coupling outputs of the second plurality of the multiple unit circuit cells to an input of the inverter circuit cell (Disclosing connecting second node 108 to the output of the transmission gate 112: Sinangil, Figure 1),
wherein an output of a hold circuit cell is coupled to an input of the inverter circuit cell and an input of the hold circuit cell is coupled to an output of the inverter circuit cell (A hold circuit cell 102 cross coupled to inverter 114: Sinangil, Figure 1 and ¶[0023]).
While Sinangil discloses a multi-port circuit similar to that described in Claim 20, it does not expressly disclose a modular design wherein the circuit parts consist of identical circuit structures. Iyer, however, discloses a multi-port circuit wherein the multiple unit circuit cells have the same circuit structure (Disclosing write and read circuit cells having a standardized circuit structure: Iyer, ¶[0064]). Iyer teaches this allows custom multi-port memory arrays to be quickly designed and efficient without significant monetary costs (Iyer, ¶[0055]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the standardized circuit cells of Iyer with the multi-port circuit architecture of Sinangil, with a reasonable expectation of success. Both inventions are well known in the field of multi-port memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
While Sinangil and Iyer disclose a multi-port circuit similar to that described in Claim 20, they do not expressly disclose a modular design wherein the circuit parts are arranged in a configuration with multiple rows and columns and wherein a number of ports of the multi-port memory cell corresponds to a number of the multiple unit circuit cells. Or-Bach, however, discloses a modular circuit array as in Claim 20:
wherein the inverter circuit cell, the hold circuit cell, and the multiple unit circuit cells are arranged in a configuration with multiple rows and columns (Showing an array of circuits arranged in a configuration of multiple rows and columns: Or-Bach, Figures 1-3), and
wherein a number of ports of the multi-port memory cell corresponds to a number of the multiple unit circuit cells (Disclosing the array including a number of ports corresponding to the inputs and/or outputs of the circuitry: Or-Bach, col. 6:47-54)
Or-Bach teaches the matrix arrangement of identical circuits provides a modular logic array without the requirement of compilation (Or-Bach, col.19:13-18). Or-Bach further discloses the corresponding input/output configuration provides for a permanent customizable interconnect between various ports (Or-Bach, col.15:1-6). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the modular circuit matrix of Or-Bach with the multi-port memory cell of Sinangil, with a reasonable expectation of success. Both inventions are well known in the field of customizable memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
The previously cited prior art does not disclose a first and second node, each including a plurality of traces routed adjacent to the multiple unit circuit cells across the multiple rows or columns, wherein the signals routed from the first and second nodes are complementary. Kean, however, discloses a multi-port memory array wherein:
a first node (A first node: Kean, Figure 7) including a first plurality of traces routed adjacent to the multiple unit circuit cells across the multiple rows or columns (Including a plurality of traces routed adjacent to unit circuit cells across multiple rows or columns: Kean, Figure 4); and
a second node (A second node: Kean, Figure 7) including a second plurality of traces routed adjacent to the multiple unit circuit cells across the multiple rows or columns (Including a plurality of traces routed adjacent to unit circuit cells across multiple rows or columns: Kean, Figure 4),
wherein the second node is configured to route a signal that is complementary to a signal routed by the first node (Wherein the signal of the first and second nodes are complementary: Kean, col.29:6-11).
Kean discloses the principal advantage of this configuration is it can be implemented with standard address decoders without space and time penalties (Kean, col.28:66-29:1) while allowing simultaneous access to circuits (Kean, col.28:30-37). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the efficient matrix addressing system of Kean with the multi-port circuit of Sinangil, with a reasonable expectation of success. Both inventions are well known in the field of multi-port circuits and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 4-5 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0385672 A1 to Mahmut Sinangil, et al. (hereafter Sinangil), US 2013/0258757 A1 to Sundar Iyer, et al. (hereafter Iyer), US 6,642,744 B2 to Zvi Or-Bach, et al. (hereafter Or-Bach), and US 5,670,897 to Thomas A. Kean (hereafter Kean) in view of US 2013/0265818 A1 to Ambica Ashok, et al. (hereafter Ashok).
Regarding Claim 4, Sinangil discloses the multi-port memory cell of claim 2, wherein the hold circuit cell further comprises
an enable input (WL to M5: Sinangil, Figure 1) and
a complementary enable input (Complementary Word Line Bar, WLB to M8: Sinangil, Figure 1 and ¶[0021])
of the tristate driver of the hold circuit cell (Of the tristate driver 102: Sinangil, Figure 1).
Sinangil does not expressly disclose an inverter coupled between the enable input and a complementary enable output. Ashok, however, discloses a memory cell as in Claim 2, including an inverter coupled between (Using an inverter to ensure complementary signals between a first and second control signal: Ashok, Figure 4 and ¶[0032]).
Ashok teaches using an inverter ensures the control signal and the inverse of the control signal are complementary (Ashok, ¶[0032]). Therefore, it would have been obvious to one having ordinary skill in the art to combine the inverter of Ashok with the complementary control inputs of Sinangil with a reasonable expectation of success. Both inventions are well known in the world of line signal controls and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 5, Sinangil discloses the multi-port memory cell of claim 1, wherein each of the multiple unit circuit cells comprises
an enable input (RWL to M11: Sinangil, Figure 1) and
a complementary enable input (Complementary Read Word Line Bar, RWLB to M10: Sinangil, Figure 1 and ¶[0021])
of a respective one of the tristate drivers (Of the tristate driver 122: Sinangil, Figure 1).
Sinangil does not expressly disclose an inverter coupled between the enable input and a complementary enable output. Ashok, however, discloses a memory cell as in Claim 2, including an inverter coupled between (Using an inverter to ensure complementary signals between a first and second control signal: Ashok, Figure 4 and ¶[0032]).
Ashok teaches using an inverter ensures the control signal and the inverse of the control signal are complementary (Ashok, ¶[0032]). Therefore, it would have been obvious to one having ordinary skill in the art to combine the inverter of Ashok with the complementary control inputs of Sinangil with a reasonable expectation of success. Both inventions are well known in the world of line signal controls and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 12, Sinangil discloses the multi-port memory cell of Claim 11, but fails to disclose the further limitations of Claim 12. Ashok, however, discloses a memory cell as in Claim 11, further comprising:
an OR gate (Disclosing an OR gate comprising a NOR gate 440 and an inverter 442: Ashok, Figure 4 and ¶[0026]),
wherein the wordlines are further coupled to inputs of the OR gate (Teaching the wordlines WWL0-WWL3 coupled to the inputs of the OR gate: Ashok, Figure 4 and ¶[0026]), and
wherein an output of the OR gate is coupled to an enable input of the hold circuit cell (Teaching the output of the OR gate, WWL0_3 coupled to the enable input of the hold circuit cell 418: Ashok, Figure 4 and ¶[0026]).
Ashok teaches using an OR gate in this manner ensures if any of the write signals WWL0 through WWL3 are asserted, the OR gate permits the data to pass while avoiding contention with other inputs (Ashok, ¶[0026]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of this application to combine the WL signal management system of Ashok with the memory cell construction of Sinangil with a reasonable expectation of success. Both inventions are well known in the field of multi-port memory circuitry and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. 2008/0005493 A1 to Jin-Il Chu, et al.: Teaching Read and Write cells comprising a transmission gate controlled by complementary lines connected by an inverter.
U.S. 2005/0005069 A1 to Mario Au, et al.: Teaching Transmit and Data Input Registers insisting of a data latch controlled by a transmission gate/inverter circuit.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 04/01/2026
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