DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10 and 12-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species 2 and 3, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/05/2026.
Applicant’s election without traverse of species 1 in the reply filed on 03/05/2026 is acknowledged.
Claim 11 is dependent on withdrawn claim 10 which reads on unelected species 2 and/or species 3. Therefore claim 11 is withdrawn from further consideration as being drawn to an unelected species.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeng et al. (US 2021/0074600 A1, hereinafter Jeng ‘600).
With respect to Claim 1 Jeng ‘600 discloses a method of manufacturing a semiconductor structure (Fig 1A-2 of Jeng ‘600), comprising:
providing a first substrate (110/112, Fig 1B, Para [0028 and 0030]) comprising a first side (110A, Fig 1B, Para [0029]) and a second side (112A, Fig 1B, Para [0031]) opposite (disclosed in Fig 1B) to the first side (110A);
etching (disclosed in Para [0040]) a recess (118, Fig 1D, Para [0039]) on the first side (110A) of the first substrate (110/112);
arranging (disclosed in Para [0041 and 0043]) a first semiconductor die (leftmost 120 as shown in Fig 1F, Para [0041]) in the recess (118) and bonding (disclosed in Para [0043]) the first semiconductor die (leftmost 120) to the first side (110A) of the first substrate (110/112);
bonding (disclosed in Para [0032]) a second semiconductor die (128, Fig 1F, Para [0032]) to the second side (112A) of the first substrate (110/112);
bonding (disclosed in Para [0046]) a first side (top of 102 as shown in Fig 1F) of a second substrate (102, Fig 1F, Para [0046]) to the first side (110A) of the first substrate (110/112); and
molding (disclosed in Fig 1F and Para [0035, 0036, 0042 and 0049]) the first substrate (110/112), the second substrate (102), the first semiconductor die (120) and the second semiconductor die (leftmost 128) (disclosed in Fig 1F and Para [0036 and 0049]).
With respect to Claim 2 Jeng ‘600 discloses all limitations of the method of claim 1, and Jeng ‘600 discloses further comprising forming an interconnect structure (111 and 112, Fig 1F, Para [0029 and 0030]) in the first substrate (110/112), wherein the interconnect structure (111 and 112) electrically couples (electrical connections are disclosed in Para [0031, 0034 and 0046]) the first semiconductor die (120) and the second semiconductor die (128) to the second substrate (102).
With respect to Claim 4 Jeng ‘600 discloses all limitations of the method of claim 1, and Jeng ‘600 discloses further comprising forming a plurality of connectors (136, Fig 1G, Para [0051]) on a second side (bottom of 102 as shown in Fig 1G) of the second substrate (102) opposite to the first side (top of 102) of the second substrate (102).
With respect to Claim 7 Jeng ‘600 discloses all limitations of the method of claim 1, and Jeng ‘600 further discloses wherein the bonding (disclosed in Para [0032]) of the second semiconductor die (128) to the second side (112A) of the first substrate (110/112) comprises:
forming a first conductive pad (conductive pads of 112 as disclosed in Para [0034], hereinafter 1CP) on the second side (112A) of the first substrate (110/112); and
bonding (disclosed in Para [0034]) the first substrate (110/112) to a first side (bottom of 128 as shown in Fig 1G) of the second semiconductor die (128) through the first conductive pad (1CP)(Para [0034] discloses boding conductive pads of 110/112 to 128).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng ‘600 in view of Park et al. (US 2018/0145044 A1, hereinafter Park ‘044), in view of the following arguments.
With respect to Claim 3 Jeng ‘600 discloses all limitations of the method of claim 2, but Jeng ‘600 fails to explicitly disclose wherein the first substrate includes a copper clad laminate including a copper foil layer, wherein the forming of the interconnect structure in the first substrate comprises patterning the copper foil layer to form a conductive line of the interconnect structure.
Nevertheless, in a related endeavor (Fig 1-5L of Park ‘044), Park ‘044 teaches wherein the first substrate (110 disclosed in Fig 5L of Park ‘044, Para [0078]) includes a copper clad laminate (disclosed in Para [0116] of Park ‘044) including a copper foil layer (thin metal layers of copper clad disclosed in Para [0116] of Park ‘044, hereinafter CF), wherein the forming (disclosed in Figs 5A-5L of Park ‘044) of the interconnect structure (112 and 135, Fig 5L of Park ‘044, Para [0117]) in the first substrate (110) comprises patterning (Para [0117] of Park ‘044 discloses patterning of copper layer and therefore the copper foil layer (CF)) the copper foil layer (CF) to form a conductive line (Para [0117] of Park ‘044 discloses patterning 112 to form wiring layer) of the interconnect structure (111A).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Park ‘044’s teaching of wherein the first substrate includes a copper clad laminate including a copper foil layer, wherein the forming of the interconnect structure in the first substrate comprises patterning the copper foil layer to form a conductive line of the interconnect structure into Jeng ‘600’s method. Jeng ‘600 discloses a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess that is disposed on a second substrate with external connectors. Further Para [0028] of Jeng ‘600 is open for the first substrate to be various types of substrates. Park ‘044 also teaches a method to fabricate a semiconductor package with a semiconductor chip that is in a substrate recess that is disposed on a second substrate with external connectors. Further the method taught by Park ‘044 of using a copper clad laminate with an additive or semi additive process to form metal lines is a well-known equivalent process to form metal lines opposed to the electroplating process of Jeng ‘600. Therefore, the ordinary artisan would have a high expectation for success in using the process of Park ‘044 instead of the process of Jeng ‘600 and would be been motivated to modify Jeng ‘600 with the teachings of Park ‘044 in the manner set forth above, at least, because, the process taught by Park ‘044 presents a well-known process to achieve the well-known advantage of forming wiring lines on a substrate and an additive or semi additive process can have cost advantages over electrolytic processes.
As incorporated, the teaching of Park ‘044 of the first substrate includes a copper clad laminate including a copper foil layer, wherein the forming of the interconnect structure in the first substrate comprises patterning the copper foil layer to form a conductive line of the interconnect structure would be used in the method of Jeng ‘600 so that the first substrate (110/112 of Jeng ‘600) would include a copper clad laminate including a copper foil layer, so that forming the interconnect structure (111/112 of Jeng ‘600) in the first substrate (110/112 of Jeng ‘600) comprises patterning the copper foil layer (as taught by Park ‘044) to form a conductive line (line of 112) of the interconnect structure (111/112).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng ‘600 in view of Chen (US 2023/0131658 A1, hereinafter Chen ‘658), in view of the following arguments.
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With respect to Claim 5 Jeng ‘600 discloses all limitations of the method of claim 4, but Jeng ‘600 fails to explicitly disclose wherein the plurality of connectors form an array occupying an area overlapping an entirety of the recess from a top-view perspective.
Nevertheless, in a related endeavor (Fig 9-12 of Chen ‘658), Chen ‘658 teaches wherein the plurality of connectors (37, Fig 9 of Chen ‘658, Para [0049]) form an array (disclosed in Fig 9 of Chen ‘658) occupying an area overlapping an entirety of the recess (recess as shown in annotated Fig 12 of Chen ‘658) from a top-view perspective (Fig 9 of Chen ‘658 discloses connectors 37 arrayed across entire substrate 3 of Chen ‘658, therefore they occupy an area overlapping the entirety of the recess show in Fig 12 of Chen ‘658).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chen ‘658’s teaching of wherein the plurality of connectors form an array occupying an area overlapping an entirety of the recess from a top-view perspective into Jeng ‘600’s method. Jeng ‘600 discloses a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess that is disposed on a second substrate with external connectors. Further Fig 1G of Jeng ‘600 discloses external connectors 136 under the recess area but does not explicitly disclose those connections occupy an area overlapping an entirety of the recess from a top-view perspective. Chen ‘658 also teaches a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess that is disposed on a second substrate with external connectors. The ordinary artisan would have been motivated to modify Jeng ‘600 with the teachings of Chen ‘658 in the manner set forth above, at least, because, the array of external connectors over the entirety of the bottom of the second substrate would provide additional I/O connections for the package and the array of external connectors would further provide a stronger attachment of the package to an external device.
As incorporated, the teaching of Chen ‘658 of the plurality of connectors form an array occupying an area overlapping an entirety of the recess from a top-view perspective would be used in the method of Jeng ‘600 so that external connectors (136 of Jeng ‘600) would overlap the entirety of the recess (118 of Jeng ‘600) from a top view perspective.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng ‘600 in view of Goto et al. (US 2011/0193203 A1, hereinafter Goto ‘203), in view of the following arguments.
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With respect to Claim 6 Jeng ‘600 discloses all limitations of the method of claim 1, but Jeng ‘600 fails to explicitly disclose wherein the recess is etched in a center of the first substrate.
Nevertheless, in a related endeavor (Fig 38 of Goto ‘203), Goto ‘203 teaches wherein the recess is etched in a center of the first substrate (Para [0154] of Goto ‘203 teaches an embodiment wherein the chip in the recess (shown in annotated Fig 38 of Goto ‘203) is centered in the substrate).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Goto ‘203’s teaching of wherein the recess is etched in a center of the first substrate into Jeng ‘600’s method. Jeng ‘600 discloses a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess. Further Para [0054] of Jeng ‘600 is open to the number of recesses in the cavity. Goto ‘203 also teaches a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess The ordinary artisan would have been motivated to modify Jeng ‘600 with the teachings of Goto ‘203 in the manner set forth above, at least, because, as Goto ‘203 teaches in Para [0154], positioning the recess and the first semiconductor chip in the recess, in the center of the embedded substrate reduces the likelihood of the substrate bending which would decrease they possibility of damage to the substrate structure.
As incorporated, the teaching of etching the recess in a center of the first substrate of Goto ‘203 would be used in the method of Jeng ‘600 so that the recess (118) of Jeng ‘600 would be in the center of the first substrate (110/112).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng ‘600 in view of Lee et al. (US 2010/0102428 A1, hereinafter Lee ‘428), in view of the following arguments.
With respect to Claim 8 Jeng ‘600 discloses all limitations of the method of claim 7, but Jeng ‘600 fails to explicitly disclose wherein the molding further causes a molding material to cover an entirety of a second side of the second semiconductor die opposite to the first side of the second semiconductor die.
Nevertheless, in a related endeavor (Fig 15 of Lee ‘428), Lee ‘428 teaches wherein the molding (disclosed in Fig 15 and Para [0027] of Lee ‘428) further causes a molding material (105, Fig 15 of Lee ‘428, Para [0027]) to cover an entirety of a second side (top of 120 as shown in Fig 15 of Lee ‘428) of the second semiconductor die (120, Fig 15 of Lee ‘428, Para [0034]) opposite to the first side (bottom of 120 as shown in Fig 15 of Lee ‘428) of the second semiconductor die (120).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘428’s teaching of wherein the molding further causes a molding material to cover an entirety of a second side of the second semiconductor die opposite to the first side of the second semiconductor die into Jeng ‘600’s method. Jeng ‘600 discloses a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess. Further Para [0038] of Jeng ‘600 is open to the molding over the top of the second semiconductor as Jeng ‘600 states that, “In some embodiments, a planarization process is applied on the protective layer 134 to partially remove the protective layer 134”, implying that an embodiment exists where planarization is not done and molding remains over second semiconductor die 128. Lee ‘428 also teaches a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess and teaches an overmolding process that covers the top of the second semiconductor die. The ordinary artisan would have been motivated to modify Jeng ‘600 with the teachings of Lee ‘428 in the manner set forth above, at least, because, the molding layer over the top of the second semiconductor device would provide additional dielectric protection to the second semiconductor die and mechanical protection to the second semiconductor die and thereby the semiconductor package.
As incorporated, the teaching of Lee ‘428 of the overmold over the top of the second semiconductor die would be used in the method of Jeng ‘600 so that the molding (134 of Jeng ‘600) would cover an entirety of the top side of second semiconductor die (128 of Jeng ‘600) that is opposite the bottom side of 128 of Jeng ‘600.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng ‘600 in view of the following arguments.
With respect to Claim 9 Jeng ‘600 discloses all limitations of the method of claim 1, and in an embodiment (Para [0036] of Jeng ‘600), Jeng ‘600 teaches wherein the molding (disclosed in Fig 1F and Para [0035, 0036, 0042 and 0049]) further causes a molding material (134, Fig 1F, Para [0036]) to fill a space (space between leftmost 128 and 112A as disclosed in Fig 1F) between the first substrate (110/112) and the second semiconductor die (128).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Jeng ‘600’s teaching of an embodiment wherein the molding further causes a molding material to fill a space between the first substrate and the second semiconductor die into Jeng ‘600’s method. Jeng ‘600 discloses in Para [0036] that underfill 132 can be omitted and the encapsulant 134 can be used to fill the space between die 128 and the top of the first substrate, “In some other embodiments, the underfill element (132) is not formed. In these cases, the protective layer (134) may be in direct contact with the conductive joints below the respective semiconductor device (128)”. The ordinary artisan would have been motivated to modify Jeng ‘600 with the additionally taught embodiment of Jeng ‘600 in the manner set forth above, at least, because using a single material to overmold and underfill the second semiconductor die 128 would reduce the process steps and the number of materials uses in production offering potential process time reduction and cost reductions.
As incorporated, the teaching of using molding (134) of Jeng ‘600 to fill the space between the second semiconductor die (128) and the top of the first substrate (110/112) would be used in the process of Jeng ‘600.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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