DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al. (US 2021/0074600 A1, hereinafter Jeng ‘600) in view of Park et al. (US 2018/0145044 A1, hereinafter Park ‘044) in further view of Lu (US 2021/0202395 A1, hereinafter Lu ‘395), in view of the following arguments.
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With respect to Claim 1 Jeng ‘600 discloses a method of manufacturing a semiconductor structure (Fig 1A-2 of Jeng ‘600), comprising:
providing a first substrate (110/112, Fig 1B, Para [0028 and 0030]) comprising a first side (110A, Fig 1B, Para [0029]) and a second side (112A, Fig 1B, Para [0031]) opposite (disclosed in Fig 1B) to the first side (110A);
etching (disclosed in Para [0040]) a recess (118, Fig 1D, Para [0039]) on the first side (110A) of the first substrate (110/112) to define a recessed surface (surface of recess 118 as shown in Fig 1F, hereinafter RS);
arranging (disclosed in Para [0041 and 0043]) a first semiconductor die (leftmost 120 as shown in Fig 1F, Para [0041]) in the recess (118) and bonding (disclosed in Para [0043]) the first semiconductor die (leftmost 120) to the first side (110A) of the first substrate (110/112);
bonding (disclosed in Para [0032]) a second semiconductor die (128, Fig 1F, Para [0032]) to the second side (112A) of the first substrate (110/112);
bonding (disclosed in Para [0046]) a first side (top of 102 as shown in Fig 1F) of a second substrate (102, Fig 1F, Para [0046]) to the first side (110A) of the first substrate (110/112); and
molding (disclosed in Fig 1F and Para [0035, 0036, 0042 and 0049]) the first substrate (110/112), the second substrate (102), the first semiconductor die (120) and the second semiconductor die (leftmost 128) (disclosed in Fig 1F and Para [0036 and 0049]).
But Jeng ‘600 fails to explicitly disclose wherein providing the first substrate comprises: embedding a first conductive line in the first side of the first substrate; embedding a second conductive line in the second side of the first substrate, wherein the second semiconductor die is electrically bonded to the second conductive line of the first substrate; and embedding a third conductive line in the recessed surface, wherein the first semiconductor die is electrically bonded to the third conductive line of the first substrate;
Nevertheless, in a related endeavor (Fig 1-6 of Park ‘044), Park ‘044 teaches wherein providing the first substrate (110 disclosed in Fig. 6 of Park ‘044, Para [0078], hereinafter FS) comprises: embedding a first conductive line (131 on 115, Fig 6 of Park ‘044, Para [0134], hereinafter FCL) in the first side (first side disclosed on annotated Fig 6 of Para ‘044) of the first substrate (110 disclosed in Fig 6 of Park ‘044, Para [0078]); embedding a second conductive line (152/153, Fig 6, Para [0098], hereinafter SCL) in the second side (second side disclosed on annotated Fig 6 of Park ‘044) of the first substrate (FS), and embedding a third conductive line (142/143, Fig 6 of Park ‘044, Para [0098], hereinafter TCL) in the recessed surface (recessed surface as disclosed in annotated Fig 6 of Park ‘044), wherein the first semiconductor die (120, Fig 6, Para [0116]) is electrically bonded (Para [0094] discloses 120 electrically connected to parts 140) to the third conductive line (TCL) of the first substrate (FS);
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Park ‘044’s teaching of wherein providing the first substrate comprises: embedding a first conductive line in the first side of the first substrate; embedding a second conductive line in the second side of the first substrate, wherein the second semiconductor die is electrically bonded to the second conductive line of the first substrate; and embedding a third conductive line in the recessed surface, wherein the first semiconductor die is electrically bonded to the third conductive line of the first substrate into Jeng ‘600’s method. Jeng ‘600 discloses a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess that is disposed on a second substrate with external connectors. Further Para [0028] of Jeng ‘600 is open for the first substrate to be various types of substrates. Park ‘044 also teaches a method to fabricate a semiconductor package with a semiconductor chip that is in a substrate recess that is disposed on a second substrate with external connectors. Further the method taught by Park ‘044 of using a copper clad laminate with an additive or semi additive process to form metal lines is a well-known equivalent process to form metal lines opposed to the electroplating process of Jeng ‘600. Therefore, the ordinary artisan would have a high expectation for success in using the process of Park ‘044 instead of the process of Jeng ‘600 and would be been motivated to modify Jeng ‘600 with the teachings of Park ‘044 in the manner set forth above, at least, because, the process taught by Park ‘044 presents a well-known process to achieve the well-known advantage of forming wiring lines on a substrate and an additive or semi additive process can have cost advantages over electrolytic processes.
As incorporated, the teaching of Park ‘044 of embedding a first conductive line (FCL) in the first side of the first substrate (FS); embedding a second conductive line (SCL) in the second side of the first substrate (FS), and embedding a third conductive line (TCL) in the recessed surface, wherein the first semiconductor die is electrically bonded to the third conductive line (TCL) of the first substrate (FS) would be used in the first substrate (110/112) of Jeng ‘600.
Jeng ‘600 as modified by Park ‘044 further teaches wherein the second semiconductor die (leftmost 128) is electrically bonded to (Para [0034] discloses dies 128 are electrically connected to top of 110) the second conductive line (SCL of Park ‘044 as incorporated above) of the first substrate (110/112);
But Jeng ‘600 as modified by Park ‘044 fails to explicitly disclose wherein bonding the first side of the second substrate to the first side of the first substrate comprises: protruding a fourth conductive line from a second side of the second substrate; protruding a fifth conductive line from the first side of the second substrate; and forming a bonding member between the first substrate and the second substrate,
Nevertheless, in a related endeavor (Fig 18-28 of Lu ‘395), Lu ‘395 teaches protruding a fourth conductive line (262, Fig 26 of Lu ‘395, Para [0083]) from a second side (top of 22/24 as shown in Fig 19 of Lu ‘395) of the second substrate (21/23, Fig 18 of Lu ‘395, Para [0080]); protruding a fifth conductive line (17, Fig 28 of Lu ‘395, Para [0101]) from the first side (bottom side of 21/23 as shown in Fig 28 of Lu ‘395) of the second substrate (21/23);
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lu ‘395’s teaching of protruding a fourth conductive line from a second side of the second substrate; protruding a fifth conductive line from the first side of the second substrate into Jeng ‘600 as modified by Park ‘044’s method. Jeng ‘600 as modified by Park ‘044 discloses a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess that is disposed on a second substrate with external connectors. Further Para [0028] of Jeng ‘600 is open for the first substrate to be various types of substrates. Lu ‘395 also teaches a method to fabricate a semiconductor package and provides manufacturing process information for the formation of a lower substrate. Therefore a person of ordinary skill in the art would be motivated to use the method of Lu ‘395 to form the first substrate, at least because, Lu ‘395 teaches a well-known method (where Jeng ‘600 as modified by Park ‘044 does not) of forming protruding conductive lines on a circuit board, so they would have an high expectation for success, to fabricate a lower substrate that would have filled in the information gaps of Jeng ‘600 as modified by Park ‘044.
As incorporated, the teaching of Lu ‘395 of protruding a fourth conductive line (262) from a second side of the second substrate (21/23); protruding a fifth conductive line (17) from the first side of the second substrate (21/23) would be used in the second substrate (102) of Jeng ‘600 as modified by Park ‘044.
Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 then discloses wherein bonding (disclosed in Para [0046]) a first side (top of 102 as shown in Fig 1F) of a second substrate (102, Fig 1F, Para [0046]) to the first side (110A) of the first substrate (110/112) comprises: and forming a bonding member (leftmost 116/108, Fig 1F of Jeng ‘600, Para [0046]) between the first substrate (110/112) and the second substrate (102) wherein the bonding member (leftmost 116/108) is in contact (Para [0046] of Jeng ‘600 discloses 116/108 connects the first and second substrates so leftmost 116/108 is in contact with FCL of Park ‘044 as incorporated into 110/112 and 262 of Lu ‘395 as incorporated into 102) between the first conductive line (FCL of Park ‘044 as incorporated above) and the fourth conductive line (262 of Lu ‘395 as incorporated above) to electrically bond (Para [0046] of Jeng ‘600 discloses leftmost 116/108 electrically connects the first and second substrates so leftmost 116/108 provides electrical contact with FCL of Park ‘044 as incorporated into 110/112 and 262 of Lu ‘395 as incorporated into 102) the first substrate (110/112) to the second substrate (102).
With respect to Claim 2: Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 discloses all limitations of the method of claim 1, and Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 further discloses wherein the first substrate (110/112 as modified above) comprises:
a first conductive via (leftmost 111, Fig 1G of Jeng ‘600, Para [0029]) extended between the first side (110A) of the first substrate (110/112) and the second side (112A) of the first substrate (110/112), and integrally extended between the first conductive line (FCL of Park ‘044 as incorporated above) and the second conductive line (262 of Lu ‘395 as incorporated above)(Para [0029] of Jeng ‘600 discloses 111 extend through 110, therefore 111 extends between FCL of Park ‘044 and 262 of Lu ‘395 as they are incorporated above);
and Park ‘044 further teaches a second conductive via (115 as disclosed in annotated Fig 6 of Park ‘044) extended between the second side (second side disclosed on annotated Fig 6 of Park ‘044) of the first substrate (FS) and the recessed surface (recessed surface as disclosed in annotated Fig 6 of Park ‘044) of the first substrate (FS), and integrally extended (disclosed in annotated Fig 6 of Park ‘044) between the second conductive line (SCL) and the third conductive line (TCL);
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Park ‘044’s further teaching of a second conductive via extended between the second side of the first substrate and the recessed surface of the first substrate, and integrally extended between the second conductive line and the third conductive line into Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395’s method. Therefore, the ordinary artisan would have a high expectation for success in using the process of Park ‘044 as the process taught by Park ‘044 presents a well-known process to achieve the well-known advantage of forming connecting wiring lines in a substrate and an additive or semi additive process can have cost advantages over electrolytic processes.
As incorporated, the further teaching of Park ‘044 of a second conductive via (115) extended between the second side of the first substrate (FS) and the recessed surface of the first substrate (FS) would be used to integrally extended between the second conductive line (SCL of Park ‘044 as incorporated above) and the third conductive line (TCL as incorporated above) in the method of Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395.
Lu ‘395 further teaches wherein the second substrate (21/23) comprises a third conductive via (leftmost 22/24 as shown in annotated Fig 28 of Lu ‘395, Para [0080 and 0082]) extended between (disclosed in annotated Fig 28 of Lu ‘395) the first side (bottom side of 21/23 as shown in Fig 28 of Lu ‘395) of the second substrate (21/23) and the second side (top of 22/24 as shown in Fig 19 of Lu ‘395) of the second substrate (21/23), and integrally extended between (disclosed in annotated Fig 28 of Lu ‘395) the fourth conductive line (262) and the firth conductive line (17).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lu ‘395’s further teaching of wherein the second substrate comprises a third conductive via extended between the first side of the second substrate and the second side of the second substrate, and integrally extended between the fourth conductive line and the firth conductive line into Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395’s method. Therefore, the ordinary artisan would have a high expectation for success in using the process of Lu ‘395 as the process taught by Lu ‘395 presents a well-known process to achieve the well-known advantage of forming connecting wiring lines in a substrate which can lead to cost advantages over an R&D process to develop a process.
As incorporated, the further teaching of Lu ‘’395 of wherein the second substrate comprises a third conductive via (leftmost 22/24) extended between the first side of the second substrate (21/23) and the second side of the second substrate (21/123), would be used and integrally extended between the fourth conductive line (262 of Lu ‘395 as incorporated above) and the firth conductive line (17 of Lu ‘395 as incorporated above) in the method of Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395.
With respect to Claim 4 Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 discloses all limitations of the method of claim 1, and Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 discloses further comprising forming a plurality of connectors (leftmost 116/108, Fig 1F of Jeng ‘600, Para [0046])(Note examiner used leftmost 116/108 as bonding member above therefore that structure is not included in the connectors) on a second side (top of 102 as shown in Fig 1G) of the second substrate (102 as modified above) opposite to the first side (bottom of 102) of the second substrate (102 as modified above), wherein one of the connectors (second from left 116/108 as shown in Fig 1G of Jeng ‘600) is electrically bonded to (Para [0046] of Jeng ‘600 discloses 116/108 electrically connects the first and second substrates so second from left 116/108 provides electrical contact with FCL of Park ‘044 as incorporated into 110/112 and 262 of Lu ‘395 as incorporated into 102) the fifth conductive line (FCL of Lu ‘395 as incorporated above) on the first side (bottom of 102 as shown in Fig 1G) of the second substrate (102 as modified above), and configured to electrically couple (Para [0046] of Jeng ‘600 discloses 116/108 electrically connects the first and second substrates so 116/108 provides electrical contact with FCL of Park ‘044 as incorporated into 110/112 and 262 of Lu ‘395 as incorporated into 102) the first substrate (110/112 as modified above) to the second substrate (102 as modified above).
With respect to Claim 6 Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 discloses all limitations of the method of claim 1, and Park ‘044 further teaches wherein the recess (recess shown in annotated Fig 6 of Park ‘044) is etched in a center (etching of recess in substrate disclosed in Para [0120] and Fig 5E of Park ‘044) of the first substrate (110 of Park ‘044), wherein a thickness (thickness of 120 shown in annotated Fig 6 of Park ‘044) of the first semiconductor die (120) is less than a depth of the recess (depth of die 120 less than the depth of the recess disclosed in annotated Fig 6 of Park ‘044), such that first semiconductor die (120) is embedded in the center of the first substrate (110)(120 embedded in center of first substrate 110 disclosed in annotated Fig 6 of Park ‘044).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Park ‘044’s further teaching of wherein the recess is etched in a center of the first substrate, wherein a thickness of the first semiconductor die is less than a depth of the recess, such that first semiconductor die is embedded in the center of the first substrate into Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395’s method. The ordinary artisan would be motivated to modify Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 with the further teachings of Park ‘044 in the manner set forth above, at least, because, using a die with a thickness less than the thickness of the substrate recess would help to reduce the vertical size of the package saving valuable real estate.
As incorporated, the teaching of Park ‘044 of a thickness of the first semiconductor die (120) is less than a depth of the recess, such that first semiconductor die is embedded in the center of the first substrate would be used in the first substrate would be used so that the first semiconductor die (leftmost 120) thickness would be less than the thickness of recess (118) of the first substrate of Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395.
With respect to Claim 7 Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 discloses all limitations of the method of claim 1, and Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 further discloses wherein the bonding (disclosed in Para [0032] of Jeng ‘600) of the second semiconductor die (leftmost 128) to the second side (112A) of the first substrate (110/112 as modified above) comprises:
forming a first conductive pad (leftmost conductive pads of 112 as disclosed in Para [0034], hereinafter 1CP) on the second side (112A) of the first substrate (110/112 as modified above), wherein the first conductive pad (1CP) is in contact with (as incorporated above SCL of Park ‘044 is on top of second substrate, therefore SCL is in contact with 1CP as 1CP would be formed on SCL) the second conductive line (SCL of Park ‘044 as incorporated above) of the first substrate (110/112 as modified above); and
bonding (disclosed in Para [0034]) the first substrate (110/112 as modified above) to the first side (bottom of 128 as shown in Fig 1G) of the second semiconductor die (leftmost 128) through the first conductive pad (1CP)(Para [0034] discloses boding conductive pads of 110/112 to 128).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng ‘600 in view of Park ‘044 in view of Lu ‘395 and in further view of Origuchi et al. (US 2009/0237900 A1, hereinafter Origuchi ‘900), in view of the following arguments.
With respect to Claim 3 Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 discloses all limitations of the method of claim 2, and Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 further discloses wherein the first substrate (110/112 as modified above) includes a copper clad laminate (disclosed in Para [0116] of Park ‘044)
But Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 fails to explicitly disclose including a copper foil layer to form the first conductive line, the second conductive line, and the third conductive line.
Nevertheless, in a related endeavor (Fig 1-12 of Origuchi ‘900), Origuchi ‘900 teaches a copper foil layer to form the first conductive line, the second conductive line, and the third conductive line (Origuchi ‘900 teaches forming conductive lines using the copper foil of a copper clad laminate in Fig 7 and Para [0080] of Origuchi ‘900).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Origuchi ‘900’s teaching of a copper foil layer to form the first conductive line, the second conductive line, and the third conductive line into Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395’s method. Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 discloses a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess that is disposed on a second substrate with external connectors and uses a copper clad lamination for forming the substrate (Park ‘044). Further Para [0028] of Jeng ‘600 is open for the first substrate to be various types of substrates. Origuchi ‘900 teaches a method for forming a substrate with a recess that includes a semiconductor die and uses copper clad laminate to form the wiring layers. Therefore, the ordinary artisan would have a high expectation for success in using the process of Origuchi ‘900 instead of the process of Jeng ‘600 and would be been motivated to modify Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 with the teachings of Origuchi ‘900 in the manner set forth above, at least, because, the process taught by Origuchi ‘900 presents a well-known process to achieve the well-known advantage of forming wiring lines on a substrate and an additive or semi additive process can have cost advantages over electrolytic processes.
As incorporated, the teaching of Origuchi ‘900 of forming conductive lines using the copper foil of a copper clad laminate would be used to form the first conductive line (FCL as incorporated above), the second conductive line (SCL as incorporated above), and the third conductive line (TCL as incorporated above) of Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng ‘600 in view of Park ‘044 in view of Lu ‘395 and in further view of Chen (US 2023/0131658 A1, hereinafter Chen ‘658), in view of the following arguments.
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With respect to Claim 5 Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 discloses all limitations of the method of claim 4, but Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 fails to explicitly disclose wherein the plurality of connectors form an array occupying an area overlapping an entirety of the recess from a top-view perspective.
Nevertheless, in a related endeavor (Fig 9-12 of Chen ‘658), Chen ‘658 teaches wherein the plurality of connectors (37, Fig 9 of Chen ‘658, Para [0049]) form an array (disclosed in Fig 9 of Chen ‘658) occupying an area overlapping an entirety of the recess (recess as shown in annotated Fig 12 of Chen ‘658) from a top-view perspective (Fig 9 of Chen ‘658 discloses connectors 37 arrayed across entire substrate 3 of Chen ‘658, therefore they occupy an area overlapping the entirety of the recess show in Fig 12 of Chen ‘658).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chen ‘658’s teaching of wherein the plurality of connectors form an array occupying an area overlapping an entirety of the recess from a top-view perspective into Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395’s method. Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 discloses a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess that is disposed on a second substrate with external connectors. Further Fig 1G of Jeng ‘600 discloses external connectors 136 under the recess area but does not explicitly disclose those connections occupy an area overlapping an entirety of the recess from a top-view perspective. Chen ‘658 also teaches a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess that is disposed on a second substrate with external connectors. The ordinary artisan would have been motivated to modify Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 with the teachings of Chen ‘658 in the manner set forth above, at least, because, the array of external connectors over the entirety of the bottom of the second substrate would provide additional I/O connections for the package and the array of external connectors would further provide a stronger attachment of the package to an external device.
As incorporated, the teaching of Chen ‘658 of the plurality of connectors form an array occupying an area overlapping an entirety of the recess from a top-view perspective would be used in the method of Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 so that external connectors (136 of Jeng ‘600) would overlap the entirety of the recess (118 of Jeng ‘600) from a top view perspective.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Jeng ‘600 in view of Park ‘044 in view of Lu ‘395 and in further view of Lee et al. (US 2010/0102428 A1, hereinafter Lee ‘428), in view of the following arguments.
With respect to Claim 8 Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 method of claim 7, and Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 discloses further comprising a second conductive pad (leftmost 123 of leftmost 120, Fig 1F, Para [0043], hereinafter SCPC) formed the first side (top side of leftmost 120 as shown in Fig 1F) of the first semiconductor die (leftmost 120) facing the recessed surface (RS)(SCPC facing the recessed surface shown in Fig 1F) of the first substrate (110/112 as modified above) within the recess (118) thereof, wherein the first conductive line (FCL of Park ‘044 as incorporated above), the second conductive line (SCL of Park ‘044 as incorporated above), the third conductive line (TCL of Park ‘044 as incorporated above), the fourth conductive line (262 of Lu ‘395 as incorporated above), and the fifth conductive line (17 of Lu ‘395 as incorporated above) are parallel with each other (annotated Fig 6 of Park ‘044 discloses first, second and third conductive lines are parallel to each other and are horizontal and annotated Fig 28 of Lu ‘395 discloses fourth and fifth conductive lines are parallel to each other and are horizontal, therefore, as incorporated, the lines are all parallel as the first and second substrates of Jeng ‘600 are parallel);
wherein the second conductive pad (SCPC) is electrically bonded (Para [0043] discloses SCPC bonds die 120 to substrate) to the third conductive line (TCL of Park ‘044 as incorporated above) embedded in the recessed surface (RS) of the first substrate (110/112 as modified above), such that the second conductive pad (SCPC) is between (Fig 1F of Jeng ‘600 discloses pads SCPC are between the top of die 120 and the recessed surface of the first substrate) the first side(top side of leftmost 120 as shown in Fig 1F) of the first semiconductor die (leftmost 120) and the recessed surface (RS) of the first substrate (110/112 as modified above).
But Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 fails to explicitly disclose wherein the molding further causes a molding material to cover an entirety of a second side of the second semiconductor die opposite to the first side of the second semiconductor die, wherein the second conductive pad is encapsulated by the molding material.
Nevertheless, in a related endeavor (Fig 15 of Lee ‘428), Lee ‘428 teaches wherein the molding (disclosed in Fig 15 and Para [0027] of Lee ‘428) further causes a molding material (105, Fig 15 of Lee ‘428, Para [0027]) to cover an entirety of a second side (top of 120 as shown in Fig 15 of Lee ‘428) of the second semiconductor die (120, Fig 15 of Lee ‘428, Para [0034]) opposite to the first side (bottom of 120 as shown in Fig 15 of Lee ‘428) of the second semiconductor die (120), wherein the second conductive pad (150, Fig 15 of Lee ‘428, Para [0026]) is encapsulated by (Fig 15 of Lee ‘428 discloses pads 150 are encapsulated by molding material 105) the molding material (105).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘428’s teaching of wherein the molding further causes a molding material to cover an entirety of a second side of the second semiconductor die opposite to the first side of the second semiconductor die, wherein the second conductive pad is encapsulated by the molding material into Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395’s method. Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 discloses a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess. Further Para [0038] of Jeng ‘600 is open to the molding over the top of the second semiconductor as Jeng ‘600 states that, “In some embodiments, a planarization process is applied on the protective layer 134 to partially remove the protective layer 134”, implying that an embodiment exists where planarization is not done and molding remains over second semiconductor die 128. Lee ‘428 also teaches a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess and teaches an overmolding process that covers the top of the second semiconductor die. Both Jeng ‘600 and Lee ‘428 teach the use of molding materials (Jeng ‘600 uses materials 126/132/134 and Lee ‘428 uses material 105) to encapsulate and protect sensitive electronic components. The ordinary artisan would have been motivated to modify Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 with the teachings of Lee ‘428 in the manner set forth above, at least, because, Lee ‘428 teaches the use of a single molding material (105) to provide protection to the semiconductor device. The person of ordinary skill in the art would be motivate then to use one material to protect their semiconductor device as taught by Lee ‘428, instead of the three protective materials of Jeng ‘600 because using a single protective material would save process steps (uses a single process step instead of the three of Jeng ‘600).
As incorporated, the teaching of Lee ‘428 of the overmold over the top of the second semiconductor die would be used in the method of Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 so that the molding (134 of Jeng ‘600) would cover an entirety of the top side of second semiconductor die (128 of Jeng ‘600) that is opposite the bottom side of 128 and the conductive pads of the first semiconductor die in the recessed area of Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395.
With respect to Claim 9 Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 discloses all limitations of the method of claim 1, and Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 further discloses wherein the first conductive line (FCL of Park ‘044 as incorporated above), the second conductive line (SCL of Park ‘044 as incorporated above), the third conductive line (TCL of Park ‘044 as incorporated above) are parallel with each other (annotated Fig 6 of Park ‘044 discloses first, second and third conductive lines are parallel to each other and are horizontal, therefore, as incorporated, the lines are all parallel as the first and second substrates of Jeng ‘600 are parallel);
wherein the fourth conductive line (262 of Lu ‘395 as incorporated above), and the fifth conductive line (17 of Lu ‘395 as incorporated above) are parallel with each other (annotated Fig 28 of Lu ‘395 discloses fourth and fifth conductive lines are parallel to each other and are horizontal, therefore, as incorporated, the lines are all parallel as the first and second substrates of Jeng ‘600 are parallel).
But Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 fails to explicitly disclose wherein the molding further causes a molding material to fill a space between the first substrate and the second semiconductor die, a space between the first substrate and the first semiconductor die, and a space between the first substrate and the second substrate;
wherein the bonding member and the fourth conductive line are encapsulated by the molding material;
Nevertheless, in a related endeavor (Fig 15 of Lee ‘428), Lee ‘428 teaches wherein the molding (disclosed in Fig 15 and Para [0027] of Lee ‘428) further causes a molding material (105, Fig 15 of Lee ‘428, Para [0027]) to fill a space (space between 112 and 120 as shown in Fig 15 of Lee ‘428) between the first substrate (112, Fig 15 of Lee ‘428, Para [0030]) and the second semiconductor die (120, Fig 15 of Lee ‘428, Para [0026]), a space (space between 112 and 130 as shown in Fig 15 of Lee ‘428) between the first substrate (112) and the first semiconductor die (130, Fig 15 of Lee ‘428, Para [0026]), and a space (space between 112 and 140 as shown in Fig 15 of Lee ‘428) between the first substrate (112) and the second substrate (140, Fig 15 of Lee ‘428, Para [0029]);
wherein the bonding member (leftmost 170, Fig 15 of Lee ‘428, Para [0035]) and the fourth conductive line (leftmost 116, Fig 15 of Lee ‘428, Para [0026]) are encapsulated by (disclosed by Fig 15 of Lee ‘428) the molding material (105);
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘428’s teaching of wherein the molding further causes a molding material to fill a space between the first substrate and the second semiconductor die, a space between the first substrate and the first semiconductor die, and a space between the first substrate and the second substrate; wherein the bonding member and the fourth conductive line are encapsulated by the molding material into Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395’s method. Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 discloses a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess. Further Para [0038] of Jeng ‘600 is open to the molding over the top of the second semiconductor as Jeng ‘600 states that, “In some embodiments, a planarization process is applied on the protective layer 134 to partially remove the protective layer 134”, implying that an embodiment exists where planarization is not done and molding remains over second semiconductor die 128. Lee ‘428 also teaches a method to fabricate a semiconductor package with a semiconductor chip over a semiconductor chip that is in a substrate recess and teaches an overmolding process that covers the top of the second semiconductor die. Both Jeng ‘600 and Lee ‘428 teach the use of molding materials (Jeng ‘600 uses materials 126/132/134 and Lee ‘428 uses material 105) to encapsulate and protect sensitive electronic components. The ordinary artisan would have been motivated to modify Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 with the teachings of Lee ‘428 in the manner set forth above, at least, because, Lee ‘428 teaches the use of a single molding material (105) to provide protection to the semiconductor device. The person of ordinary skill in the art would be motivate then to use one material to protect their semiconductor device as taught by Lee ‘428, instead of the three protective materials of Jeng ‘600 because using a single protective material would save process steps (uses a single process step instead of the three of Jeng ‘600).
As incorporated, the teaching of Lee ‘428 to use a single molding layer method to encapsulate the entire semiconductor device would be used in the method of Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395 so that the molding (105) fills a space between the first substrate and the second semiconductor die, a space between the first substrate and the first semiconductor die, and a space between the first substrate and the second substrate; wherein the bonding member and the fourth conductive line are encapsulated by the molding material in the method of Jeng ‘600 as modified by Park ‘044 and further modified by Lu ‘395.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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