DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Rejections - 35 USC § 112 3
A. Claims 1-8 and 10 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. 3
B. Claims 1-8 and 10 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. 4
III. Claim Rejections - 35 USC § 103 5
A. Claims 1, 2, 6, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0391261 (“Liao”) in view of US 2022/0415804 (“Yao”). 5
B. Claims 1, 2, and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over US 6,423,630 (“Catabay”) in view of US 2021/0098292 (“Nguyen”). 10
C. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Catabay in view of Nguyen, as applied to claim 1 above, and further in view of US 2024/0038528 (“Cheng”). 20
IV. Response to Arguments 21
Conclusion 21
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
A. Claims 1-8 and 10 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
Claim 1, as amended, reads in pertinent part:
a first interconnect structure and a second interconnect structure disposed over the second dielectric layer;
a first dielectric liner portion disposed adjacent to the first interconnect structure;
a second dielectric liner portion disposed adjacent to the second interconnect structure;
…
a third interconnect structure and a fourth interconnect structure disposed over the second dielectric layer
to form a first opening between the first interconnect structure and the third interconnect structure and a second opening between the fourth interconnect structure and the second interconnect structure,
wherein
the first dielectric liner portion is disposed between the first interconnect structure and the third interconnect structure and within the first opening, and
the second dielectric liner portion is disposed between the second interconnect structure and the fourth interconnect structure and within the first opening;
Thus, claim 1 requires the second opening to be formed by the space between the second and fourth interconnect structures, but contradictorily, for the second dielectric liner portion to be in the first opening formed by the space between the first and third interconnect structures. There is not support in the Instant Application to show that the Instant Inventors were in possession of this configuration.
For the purposes of examination, it will be presumed that Applicant meant, instead, the following:
the second dielectric liner portion is disposed between the second interconnect structure and the fourth interconnect structure and within the second opening;
Claims 2-8 and 10 are rejected for including the same indefinite feature by depending from claim 1 either directly or indirectly.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
B. Claims 1-8 and 10 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites the limitation “the interconnect structure” in each of lines 5, 25, and 28. There is insufficient antecedent basis for this limitation in the claim, as well as unclear antecedent basis because there are first, second, third, and fourth interconnect structures recited in the claim. It is presumed that Applicant intended, instead, the limitation, “the first interconnect structure”.
Claims 2-8 and 10 are rejected for including the same indefinite feature by depending from claim 1 either directly or indirectly.
III. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1, 2, 6, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0391261 (“Liao”) in view of US 2022/0415804 (“Yao”).
Claim 1 reads,
1. (Currently Amended) A semiconductor device structure, comprising:
[1] a first dielectric layer disposed over a semiconductor substrate;
[2] a second dielectric layer disposed over the first dielectric layer;
[3a] a first interconnect structure and a second interconnect structure disposed over the second dielectric layer,
[3b] wherein a bottom surface of the [first] interconnect structure and a bottom surface of the second interconnect structure are in contact with a top surface of the second dielectric layer;
[4] a first dielectric liner portion disposed adjacent to the first interconnect structure;
[5] a second dielectric liner portion disposed adjacent to the second interconnect structure;
[6] a first filling portion surrounded by the first dielectric liner portion;
[7a] a second filling portion surrounded by the second dielectric liner portion, wherein
[7b] a material of the first filling portion is the same as a material of the second filling portion, and
[7c] a width of the second filling portion is greater than a width of the first filling portion; and
[8a] a third interconnect structure and a fourth interconnect structure disposed over the second dielectric layer
[8b] to form a first opening between the first interconnect structure and the third interconnect structure and a second opening between the fourth interconnect structure and the second interconnect structure,
wherein
[9a] the first dielectric liner portion is disposed between the first interconnect structure and the third interconnect structure and within the first opening, and
[9b] the second dielectric liner portion is disposed between the second interconnect structure and the fourth interconnect structure and within the first opening;
[10] wherein a material of the first dielectric liner portion is the same as a material of the second dielectric liner portion;
[11] wherein a width of the second opening is greater than a width of the first opening;
[12] wherein the width of the first opening is greater than the width of the first filling portion while the width of the second opening is greater than the width of the first filling portion;
[13] wherein the bottom surface of the [first] interconnect structure, the bottom surface of the second interconnect structure, a bottom surface of the first dielectric liner portion, and a bottom surface of the second dielectric liner portion are coplanar with each other;
[14] wherein a top surface of the [first] interconnect structure, a top surface of the second interconnect structure, a top surface of the first filling portion, a top surface of the second filling portion, a top surface of the first dielectric liner portion, and a top surface of the second dielectric liner portion are coplanar with each other.
With regard to claim 1, Liao discloses, generally in Figs. 3 and 14,
1. (Currently Amended) A semiconductor device structure, comprising:
[1] … a semiconductor substrate 102 [¶ 22];
[2] a second dielectric layer 110 [¶ 22] disposed over the … [semiconductor substrate 102] …
[3a] a first interconnect structure [leftmost 114 in Fig. 14 (¶ 23)] and a second interconnect structure [e.g. 114 with overlying contact 126] disposed over the second dielectric layer 110,
[3b] wherein a bottom surface of the [first] interconnect structure [leftmost 114] and a bottom surface of the second interconnect structure [114 with overlying contact 126] are in contact with a top surface of the second dielectric layer 110;
[4] a first dielectric liner portion [116 between leftmost 114 and directly adjacent 114] disposed adjacent to the first interconnect structure [leftmost 114];
[5] a second dielectric liner portion [116 between rightmost 114 and 114 with overlying contact 126] disposed adjacent to the second interconnect structure [114 with overlying contact 126];
[6] a first filling portion [117, 118 between leftmost 114 and directly adjacent 114 (¶¶ 63, 66)] surrounded by the first dielectric liner portion [116 between leftmost 114 and directly adjacent 114];
[7a] a second filling portion [117, 118 between rightmost 114 and 114 with overlying contact 126] surrounded by the second dielectric liner portion [116 between rightmost 114 and 114 with overlying contact 126], wherein
[7b] a material of the first filling portion is the same as a material of the second filling portion [¶¶ 63, 66], and
[7c] a width of the second filling portion [117, 118 between rightmost 114 and 114 with overlying contact 126] is greater than a width of the first filling portion [117, 118 between leftmost 114 and directly adjacent 114 (¶¶ 63, 66)] [as shown in Figs. 3 and 14 and “… the first ILD layer 118 may have separate segments comprising different widths. As a result, a pitch between some of the plurality of first metal lines 114 may vary throughout the integrated chip 200.” (¶ 29)]; and
[8a] a third interconnect structure [second 114 from left in Fig. 14] and a fourth interconnect structure [rightmost 114 in Fig. 14] disposed over the second dielectric layer 110
[8b] to form a first opening between the first interconnect structure [leftmost 114] and the third interconnect structure [second 114 from left] and a second opening between the fourth interconnect structure [rightmost 114] and the second interconnect structure [114 with overlying contact 126],
wherein
[9a] the first dielectric liner portion [116 between leftmost 114 and directly adjacent 114] is disposed between the first interconnect structure and the third interconnect structure and within the first opening, and
[9b] the second dielectric liner portion [116 between rightmost 114 and 114 with overlying contact 126] is disposed between the second interconnect structure and the fourth interconnect structure and within the first [sic, should be “second”] opening;
[10] wherein a material of the first dielectric liner portion [116 between leftmost 114 and directly adjacent 114] is the same as a material of the second dielectric liner portion [116 between rightmost 114 and 114 with overlying contact 126];
[11] wherein a width of the second opening is greater than a width of the first opening [¶ 29, as shown in Figs. 3 and 14];
[12] wherein the width of the first opening is greater than the width of the first filling portion [117, 118 between leftmost 114 and directly adjacent 114 (¶¶ 63, 66)] while the width of the second opening [117, 118 between rightmost 114 and 114 with overlying contact 126] is greater than the width of the first filling portion [¶ 29, as shown in Figs. 3 and 14];
[13] wherein the bottom surface of the [first] interconnect structure 114, the bottom surface of the second interconnect structure 114, a bottom surface of the first dielectric liner portion 116, and a bottom surface of the second dielectric liner portion 116 are coplanar with each other [as shown in Fig. 14, the bottom surfaces of all 114 and 116 are coplanar];
[14] wherein a top surface of the [first] interconnect structure 114, a top surface of the second interconnect structure 114, a top surface of the first filling portion 117, 118, a top surface of the second filling portion 117, 118, a top surface of the first dielectric liner portion 116, and a top surface of the second dielectric liner portion 116 are coplanar with each other [as shown in Fig. 14, the tops surfaces of all 114, 116, 117, and 118 are coplanar].
With regard to features [1] and [2] of claim 1,
[1] a first dielectric layer disposed over a semiconductor substrate;
[2] a second dielectric layer disposed over the first dielectric layer,
Liao does not disclose a first dielectric layer over the semiconductor substrate and below the second dielectric layer 110.
Yao shares both common inventors and a common assignee with Liao. Yao, like Liao, teaches a semiconductor device including metal lines 110a, 110b formed over a second dielectric layer 106d over semiconductor devices 104 formed in/on a semiconductor substrate 102, wherein metal contacts 106c are made to the semiconductor devices 104 (Yao: Figs. 1A-1B, 2; ¶¶ 41, 43, 45, 49-50, 53, 76-78). Yao further teaches forming a first dielectric layer, i.e. an etch stop 106e, on the substrate 102 over the semiconductor devices 104 to protect the semiconductor device features during the etching of the openings in which the contacts 106c are formed (Yao: ¶ 41, 44, 45, 53, 78).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form an etch stop layer on the semiconductor substrate 102 of and semiconductor devices 104 of Liao before forming the second dielectric layer 110 of Liao, in order to provide an etch stop layer to protect the semiconductor devices 104 during the etching of the contacts 112 of Liao. As such, Yao may be seen as an improvement to Liao in this aspect. (See MPEP 2143.)
This is all of the limitations of claim 1.
With regard to claim 2, Liao further discloses,
2. (currently amended) The semiconductor device structure of claim 1,
[1] wherein a bottom width of the second dielectric liner portion [116 between rightmost 114 and 114 with overlying contact 126] is greater than a bottom width of the first dielectric liner portion [116 between leftmost 114 and directly adjacent 114],
[2] wherein the top surface of the first filling portion 117, 118 is exposed from the top surface of the first dielectric liner portion 116 while the top surface of the second filling portion 117, 118 is exposed from the top surface of the second dielectric liner 116 portion [as shown in Fig. 14, all top surfaces of the filling portions 117, 118 are exposed from between the liner portions 116].
With regard to claim 6, Liao further discloses,
6. (currently amended) The semiconductor device structure of claim 1, further comprising: a cover layer 122 [¶ 38; Fig. 16] disposed over and in direct contact with the top surface of the first interconnect structure 114, the top surface of the second interconnect structure 114, the top surface of the first dielectric liner portion 116, the top surface of the second dielectric liner portion 116, the top surface of the first filling portion 118, and the top surface of the second filling portion 118 [Fig. 16 shows that the cover layer, i.e. etch stop 122, contacts the top surfaces of each of the fill 118, the liner 116, and the metal lines 114].
With regard to claim 10, Liao further discloses,
10. (original) The semiconductor device structure of claim 1, wherein the material of the first filling portion 117 and the material of the second filling portion 117 include an energy removable material [¶¶ 46, 63, 68 (e.g. thermal energy)].
B. Claims 1, 2, and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over US 6,423,630 (“Catabay”) in view of US 2021/0098292 (“Nguyen”).
Claim 1 reads,
1. (Currently Amended) A semiconductor device structure, comprising:
[1] a first dielectric layer disposed over a semiconductor substrate;
[2] a second dielectric layer disposed over the first dielectric layer;
[3a] a first interconnect structure and a second interconnect structure disposed over the second dielectric layer,
[3b] wherein a bottom surface of the [first] interconnect structure and a bottom surface of the second interconnect structure are in contact with a top surface of the second dielectric layer;
[4] a first dielectric liner portion disposed adjacent to the first interconnect structure;
[5] a second dielectric liner portion disposed adjacent to the second interconnect structure;
[6] a first filling portion surrounded by the first dielectric liner portion;
[7a] a second filling portion surrounded by the second dielectric liner portion, wherein
[7b] a material of the first filling portion is the same as a material of the second filling portion, and
[7c] a width of the second filling portion is greater than a width of the first filling portion; and
[8a] a third interconnect structure and a fourth interconnect structure disposed over the second dielectric layer
[8b] to form a first opening between the first interconnect structure and the third interconnect structure and a second opening between the fourth interconnect structure and the second interconnect structure,
wherein
[9a] the first dielectric liner portion is disposed between the first interconnect structure and the third interconnect structure and within the first opening, and
[9b] the second dielectric liner portion is disposed between the second interconnect structure and the fourth interconnect structure and within the first opening;
[10] wherein a material of the first dielectric liner portion is the same as a material of the second dielectric liner portion;
[11] wherein a width of the second opening is greater than a width of the first opening;
[12] wherein the width of the first opening is greater than the width of the first filling portion while the width of the second opening is greater than the width of the first filling portion;
[13] wherein the bottom surface of the [first] interconnect structure, the bottom surface of the second interconnect structure, a bottom surface of the first dielectric liner portion, and a bottom surface of the second dielectric liner portion are coplanar with each other;
[14] wherein a top surface of the [first] interconnect structure, a top surface of the second interconnect structure, a top surface of the first filling portion, a top surface of the second filling portion, a top surface of the first dielectric liner portion, and a top surface of the second dielectric liner portion are coplanar with each other.
With regard to claim 1, Catabay discloses, generally in Fig. 7B,
1. (Currently Amended) A semiconductor device structure, comprising:
[1] … [not taught] …
[2] … [not taught] …
[3a] a first interconnect structure [e.g. left of two 6/50 in Fig. 7B] and a second interconnect structure [not shown but would be to the right of the rightmost (liner 20)/(fill 30); see explanation below] disposed over the … [integrated circuit structure 2] … [“Closely spaced apart metal lines 6 are shown formed over an integrated circuit structure 2” (col. 5, lines 25-26); and “protective caps 50; which may comprise … an electrically conductive material, may be formed over the top surfaces of metal lines 6” (col. 7, lines 49-52)]
[3b] wherein a bottom surface of the [first] interconnect structure 6/50 and a bottom surface of the second interconnect structure 6/50 are in contact with a top surface of the … [integrated circuit structure 2] … [as shown in Fig. 7B];
[4] a first dielectric liner portion 20 [i.e. “first low k dielectric material 20” (col. 5, line 27)] disposed adjacent to the first interconnect structure 6/50;
[5] a second dielectric liner portion 20 disposed adjacent to the second interconnect structure 6/50;
[6] a first filling portion 30 [i.e. “second low k dielectric material 30” (col. 6, lines 42-44)] surrounded by the first dielectric liner portion 20;
[7a] a second filling portion 30 surrounded by the second dielectric liner portion 20, wherein
[7b] a material of the first filling portion 30 is the same as a material of the second filling portion 30, and
[7c] … [not taught] …
[8a] a third interconnect structure [right of two 6/50 in Fig. 7B] … disposed over the … [integrated circuit structure 2] …
[8b] to form a first opening between the first interconnect structure [left of two 6/50 in Fig. 7B] and the third interconnect structure [right of two 6/50 in Fig. 7B] …
[9a]-[9b] … [not taught] …
[10] wherein a material of the first dielectric liner portion 20 is the same as a material of the second dielectric liner portion 20;
[11] … [not taught] …
[12] … [not taught] …
[13] wherein the bottom surface of the [first] interconnect structure 6/50, the bottom surface of the second interconnect structure 6/50, a bottom surface of the first dielectric liner portion 20, and a bottom surface of the second dielectric liner portion 20 are coplanar with each other [as shown in Fig. 7B];
[14] wherein a top surface of the [first] interconnect structure 6/50, a top surface of the second interconnect structure 6/50, a top surface of the first filling portion 30, a top surface of the second filling portion 30, a top surface of the first dielectric liner portion 20, and a top surface of the second dielectric liner portion 20 are coplanar with each other [as shown in Fig. 7B; col. 8, lines 36-49].
With regard to feature [3a] of claim 1, the voids 24 only occur due to pinch-off of the dielectric layer 20 between sufficiently closely-spaced metal lines 6/50, as explained in Catabay:
FIG. 2 illustrates the first step of the process of the invention. Closely spaced apart metal lines 6 are shown formed over an integrated circuit structure 2 with a layer of a first low k dielectric material 20 resistant to via poisoning shown formed between and over metal lines 6. Voids 24 are shown formed in first low k dielectric material 20 between metal line 6. By use of the term “closely spaced apart” with respect to the spacing of the metal lines is meant a spacing as small as 200 nanometers (nm) between adjacent metal lines.
(Catabay: col. 5, lines 24-33; emphasis added)
As previously mentioned, PECVD-formed low k dielectric material [20] forms voids [24] when deposited in high aspect ratio regions. The formation of such voids 24 are shown in FIG. 2 in the spaces between closely spaced apart metal lines 6.
(Catabay: col. 6, lines 2-6; emphasis added)
Because the rightmost void 24 in Fig. 2 or the rightmost void filled with dielectric 30 in Fig. 7B can only happen if adjacent to a closely spaced metal line, there are inherently necessarily two additional metal lines 6/50, one to the left of the left metal line 6/50 in Fig. 7B and the other to the right of the right 6/50 in Fig. 7B, albeit not shown. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
With regard to features [1], [2], [3a], [3b], and [8a] of claim 1,
[1] a first dielectric layer disposed over a semiconductor substrate;
[2] a second dielectric layer disposed over the first dielectric layer;
While Catabay states that element 2 is an “integrated circuit structure 2” (col. 4, line 17), Catabay does not give the structural information of the integrated circuit structure 2 and does not, consequently, disclose the first and second dielectric layers or the semiconductor substrate.
Nguyen, like Catabay, teaches an integrated circuit structure 102/104 (Nguyen: ¶ 20) including a plurality of metal lines 114A-114D (Nguyen: Fig. 10; ¶ 37) including closely spaced metal lines, i.e. 114A is closely spaced to 114B, and 114C is closely spaced to 114D, leading to a void 126 caused by the pinch off 124 in the liner dielectric 116' at the opening between said closely spaced metal lines, as explained in Nguyen (id.).
Nguyen further teaches that the integrated circuit structure 102/104 includes a semiconductor substrate 102 on which is formed a front end of line (FEOL) on the substrate and a middle end of line (MOL) on the FEOL, collectively denoted with reference character 104 (¶¶ 19-21). The FEOL includes the semiconductor devices such as transistors (¶ 21), and the MOL includes a pre-metal dielectric (PMD) with “conductive via contacts” to the semiconductor devices of “the integrated circuitry of the FEOL layer” (id.). Nguyen further teaches forming a dielectric “capping layer 106”, i.e. a second dielectric, on the FEOL/MOL 104 and therefore on the PMD, i.e. a first dielectric.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the semiconductor substrate 102 and FEOL/MOL 104 on the semiconductor substrate as well as the dielectric capping layer 106 because Catabay is merely silent as to the elements of the integrated circuit structure 2, such that one having ordinary skill in the art would include well-known elements of an integrated circuit structure, such as those taught to be known in Nguyen, again, sequentially, the semiconductor substrate 102, the FEOL/MOL 104 and the dielectric capping layer 106. As such, Nguyen may be seen a merely providing missing descriptive details regarding the well-known elements of an integrated circuit structure that Catabay simply fails to discuss.
So modified, each of the semiconductor substrate, the first dielectric and the second dielectric are taught and the claimed interconnect structures are over and contacting the second dielectric layer 106 of Nguyen used in Catabay, as shown in Fig. 10 of Nguyen, as required by features [3a], [3b], and [8a].
With regard to feature [7c], [8a]-[9b], [11], and [12] of claim 1, Catabay does not explicitly show metal lines spaced apart wider than those considered to be “closely spaced”, i.e. “By use of the term ‘closely spaced apart’ with respect to the spacing of the metal lines is meant a spacing as small as 200 nanometers (nm) between adjacent metal lines.” (Catabay: col. 5, lines 30-33) Because Catabay does not explicitly show metal lines both closely spaced and spaced apart wider than closely spaced, Catabay does not teach the limitations of features [7c], [8a]-[9b], [11], and [12].
Nguyen further teaches that it is known in making the interconnect to electrically connect semiconductor elements in an integrated circuit device to include both closely spaced metal lines (supra), as well as lines spaced wider apart than closely spaced, e.g. between 114B and 114C or between 114D and 114E:
[0037] In another illustrative embodiment, an air-gap integration process can be implemented to form air gaps between closely spaced metal lines 114A-114E. For example, with reference to FIG. 10, the semiconductor structure 300 includes a barrier 116′ having additional layers formed in accordance with the process outlined in FIGS. 1-7 to provide a thicker barrier 116′. In one methodology, the ILD layer 118 may be deposited over the semiconductor structure 300 shown in FIG. 10 using a non-conformal deposition process (e.g., chemical vapor deposition (CVD) or Plasma-enhanced chemical vapor deposition (PECVD), which results in the formation of “pinch-off” regions 124 in the layer of dielectric material above the small spaces between closely spaced metal lines 114A-114E. The wider spaces between the metal lines 114A-114E will be filled.
(Nguyen: ¶ 37; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include additional metal lines in Catabay having a wider spacing than closely spaced” that would be not have pinch-off regions (shown in Fig. 2 of Catabay), as taught in Nguyen, because Nguyen teaches that it is known in making the interconnect to electrically connect semiconductor elements in an integrated circuit device to include both closely spaced metal lines and relatively wider-spaced metal lines, as shown in Fig. 10 of Nguyen.
So modified features [7c], [8a]-[9b], [11], and [12] are taught, as follows:
[7c] a width of the second filling portion is greater than a width of the first filling portion [because the space between the additional wider-spaced lines would have a wider filling portion of dielectric 118, as shown in Fig. 10 of Nguyen, which would equate to dielectric filling 30 in Catabay]; and
[8a] a third interconnect structure [right of the two metal lines 6/50] and a fourth interconnect structure [additional 6/50 of Catabay as taught by Nguyen] disposed over the second dielectric layer [106 of Nguyen used in Catabay]
[8b] to form a first opening between the first interconnect structure [left of two 6/50 in Fig. 7B] and the third interconnect structure [right of two 6/50 in Fig. 7B] and a second opening between the fourth interconnect structure and the second interconnect structure [i.e. not-shown 6/50 to right of rightmost dielectric 20/30, as explained above],
wherein
[9a] the first dielectric liner portion 20 is disposed between the first interconnect structure [left of the two metal lines 6/50] and the third interconnect structure [right of the two metal lines 6/50] and within the first opening, and
[9b] the second dielectric liner portion 20 is disposed between the second interconnect structure [i.e. not-shown 6/50 to right of rightmost dielectric 20/30, as explained above] and the fourth interconnect structure [i.e. additional 6/50 of Catabay as taught by Nguyen] and within the first [sic, should be “second”] opening;
[11] wherein a width of the second opening is greater than a width of the first opening [as taught by Nguyen, as explained above];
[12] wherein the width of the first opening is greater than the width of the first filling portion [otherwise the first filling portion 30 would not fit in the first opening] while the width of the second opening is greater than the width of the first filling portion [because the second opening is wider than the first opening, as taught by Nguyen, as explained above];
This is all of the limitations of claim of claim 1.
With regard to claim 2, Catabay modified according to Nguyen, as explained above, further teaches,
2. (currently amended) The semiconductor device structure of claim 1,
[1] wherein a bottom width of the second dielectric liner portion 20 is greater than a bottom width of the first dielectric liner portion 20 [because the second opening is wider than the first opening, as taught by Nguyen, as explained above],
[2] wherein the top surface of the first filling portion 30 is exposed from the top surface of the first dielectric liner portion 20 while the top surface of the second filling portion 30 is exposed from the top surface of the second dielectric liner portion 20 [as shown in Fig. 7B of Catabay].
Because the wider-spaced metal lines 6/50 of Catabay/Nguyen, i.e. the claimed second and fourth interconnect structures, have a wider opening that would not pinch off to form voids 24 and even the voids 24 in Catabay be closely spaced lines 6/50 are filled with dielectric fill 30, the filling portion 30 between the wider-spaced metal lines, would necessarily be filled with the dielectric fill 30 which would have an exposed to surface adjacent to the liner dielectric 20 upon the CMP planarization process of Catabay.
With regard to claims 4 and 5, Catabay modified according to Nguyen, as explained above, further teaches,
4. (original) The semiconductor device structure of claim 1, wherein
[1] the first filling portion 30 is separated from the second dielectric layer [106 of Nguyen used in Catabay, supra] by the first dielectric liner portion 20 [as shown in Fig. 7B of Catabay and Fig. 10 of Nguyen], and
[2] the second filling portion 30 is separated from the second dielectric layer [106 of Nguyen used in Catabay, supra] by the second dielectric liner portion 20 [as shown in Fig. 7B of Catabay and Fig. 10 of Nguyen].
5. (original) The semiconductor device structure of claim 4, wherein
[1] the first filling portion 30 is separated from the first interconnect structure [left 6/50 in Fig. 7B of Catabay] by the first dielectric liner portion 20 [as shown in Fig. 7B of Catabay], and
[2] the second filling portion 30 is separated from the second interconnect structure [i.e. not-shown 6/50 to right of rightmost dielectric 20/30, as explained above] by the second dielectric liner portion 20 [as shown in Fig. 7B of Catabay].
With regard to claims 6 and 7, Catabay further discloses,
6. (currently amended) The semiconductor device structure of claim 1, further comprising: a cover layer 40 [Catabay Fig. 7B; col. 8, lines 48-49] disposed over and in direct contact with the top surface of the first interconnect structure, the top surface of the second interconnect structure, the top surface of the first dielectric liner portion, the top surface of the second dielectric liner portion, the top surface of the first filling portion, and the top surface of the second filling portion.
7. (original) The semiconductor device structure of claim 6, wherein the cover layer 40 includes silicon nitride (Si3N4), silicon oxynitride (SiON), silicon dioxide (SiO2), or carbonitride.
Catabay states that “Third low k dielectric material 40 may comprise the same material as first low k dielectric material 20 or any other low k dielectric material through which vias may be etched without damage to the third low k dielectric material such as the previously described via poisoning.” (sentence bridging col. 6 line 65 to col. 7, line 3). The first low k dielectric material 20 can be carbon doped silicon oxide, which includes silicon dioxide.
With regard to claim 8, Catabay modified according to Nguyen, as explained above, further teaches,
8. (currently amended) The semiconductor device structure of claim 1, wherein
[1] the first dielectric liner portion 20 is in direct contact with the first interconnect structure [left 6/50] and the third interconnect structure [right 6/50] [as shown in Fig. 7B of Catabay], and
[2] the second dielectric liner portion 20 is in direct contact with the second interconnect structure [i.e. not-shown 6/50 to right of rightmost dielectric 20/30, as explained above] and the fourth interconnect structure [additional 6/50 of Catabay as taught by Nguyen] [as shown in Fig. 7B of Catabay and Fig. 10 of Nguyen];
[3] wherein the first dielectric liner 20 has a U-shaped cross section and forms a third opening to receive the first filling portion 30 therein [as shown in Fig. 7B of Catabay];
[4] wherein the second dielectric liner 20 has a U-shaped cross section and forms a fourth opening to receive the second filling 30 portion therein [as shown in Fig. 10 of Nguyen, for example between wider-spaced metal lines 114B and 114D or between 114D and 114E, bearing in mind the CMP planarization step of Catabay];
[5] wherein a width of the third opening is less than a width of the fourth opening [because the third opening is between closely-spaced metal lines 6/50, while the fourth opening is between relatively wider spaced metal lines 6/50 of Catabay/Nguyen, as explained above].
C. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Catabay in view of Nguyen, as applied to claim 1 above, and further in view of US 2024/0038528 (“Cheng”).
Claim 3 reads,
3. (original) The semiconductor device structure of claim 1, wherein the material of the first dielectric liner portion and the material of the second dielectric liner portion include boron carbonitride (BCN).
Catabay in view of Nguyen teaches, e.g., carbon-doped silicon oxide for the dielectric liner 20. (See claim 7, supra). Catabay does not teach BCN.
Cheng, like Catabay, teaches a metallization structure including metal lines 50' having air gaps 80 between the metal lines 50' (Cheng: Fig. 12; ¶¶ 37, 48). Cheng further teaches that the dielectric layer 20 can be BCN (Cheng: ¶ 30).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the dielectric liner 20 of Catabay from BCN because Cheng teaches that BCN is suitable for a dielectric material formed between metallization structures in which air gaps are to formed, such that the substitution of carbon-doped silicon oxide for BCN would be the substitution of one known dielectric material for another, known to be suitable for the same purpose of enclosing air gaps in the dielectric formed between metallization structures. As such, the selection of BCN amounts to obvious material choice. (See MPEP 2144.07.)
IV. Response to Arguments
Applicant’s arguments filed 03/13/2026 have been fully considered but they are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814