Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment filed on 4/3/26 has been entered.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Applicant’s Argument:
Applicant contends (see page 7 of the Remarks) that the “native n-type regions” disclosed by Salcedo cannot be considered “intrinsic regions.” Applicant asserts that an intrinsic semiconductor must be an extremely pure material free from impurities, i.e., without any significant dopant species.
Examiner’s Response:
The Examiner respectfully disagrees. Under the broadest reasonable interpretation consistent with the Specification, the claimed “intrinsic layer”, unless specifically claimed otherwise, does not require the absolute absence of impurities or dopants. In the present application, paragraph [0018] of the specification describes a “low-doped intrinsic layer,” which indicates that the Applicant does not limit the term “intrinsic” to a perfectly impurity-free material. The specification does not provide a definition requiring complete absence of dopants or impurities as asserted in the Remarks.
Furthermore, Salcedo’s disclosure of a “native region” is reasonably interpreted as corresponding to an intrinsic. This interpretation is consistent with the understanding in the art that “native” regions may refer to intrinsic. For example, Kapur (U.S. 20150129030) describes “intrinsic (native) semiconductors,” supporting that such terminology may be used interchangeably or at least overlap in scope.
Accordingly, Applicant’s arguments have been fully considered but are not persuasive. The rejection is therefore maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Salcedo (US 20140346563).
Regarding claim 1. Fig 7C of Salcedo discloses A structure 330 comprising:
a plurality of wells (94a/94b, PW) of a first conductivity type (P-type);
a well (92a, NW) of a second conductivity type (N-type) which is different than the first conductivity type (N vs P);
an intrinsic semiconductor region (302a/302b, which are Nt_n; Note that the ‘Nt_n’ is ‘native n-type region [0049] has very low doping centration [0060], and thus, a native n-type semiconductor with a very low doping concentration will behave like an intrinsic semiconductor because the natively added electrons don't significantly alter the overall electron/hole balance or conductivity compared to the naturally generated carriers) between the well of the second conductivity type and the plurality of wells; and
contacts (98a/97a/97b/98b) within the plurality of wells of the first conductivity type.
Regarding claim 2. Salcedo discloses The structure of claim 1, wherein the intrinsic semiconductor region has a dopant concentration lower than the plurality of wells of the first conductivity type and the well of the second conductivity type ([0060]/[0061]: 1x1015 cm-3 vs 7.5x1016 cm-3).
Regarding claim 3. Salcedo discloses The structure of claim 1, wherein the plurality of wells comprise P-wells and the well of the second conductivity type comprises an N-well (Fig 7C).
Regarding claim 4. Salcedo discloses The structure of claim 1, further comprising a highly-doped region (306a/306b, P+) of the first conductivity type at an interface (the interface between 94a and 302a, or between 94b and 302b) between the plurality of wells and the intrinsic semiconductor region (Fig 7C).
Regarding claim 5. Salcedo discloses The structure of claim 4, wherein the highly-doped region of the first conductivity type comprises a higher dopant concentration than the plurality of wells of the first conductivity type ([0060]/[0061]: 10x1020 cm-3 vs 7.5x1016 cm-3).
Allowable Subject Matter
Claims 13-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “an N+ type region at an interface between the N-well and the intrinsic semiconductor”.
Regarding claim 20. the cited prior art of record does not teach or fairly suggest, along with the other claimed features “the plurality of wells of the first conductivity type, the well of the second conductivity type and the intrinsic semiconductor region comprise a top semiconductor layer of a semiconductor-on-insulator substrate”.
Claims 6-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “a highly-doped region of the second conductivity type at an interface between the well of the second conductivity type and the intrinsic semiconductor region”.
Regarding claim 8. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the plurality of wells of the first conductivity type, the well of the second conductivity type and the intrinsic semiconductor region comprise a top semiconductor layer of a semiconductor-on-insulator substrate”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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