DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Claim Objections 3
IV. Claim Rejections - 35 USC § 103 3
A. Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0067278 (“Seo”) in view of US 2019/0259839 (“Ryu-839”) and US 2020/0152753 (“Huh”). 4
V. Allowable Subject Matter 8
VI. Pertinent Prior Art 8
Conclusion 9
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant’s election without traverse of species group I in the reply filed on 03/05/2026 is acknowledged. Claims 1-10 read on the elected species group.
III. Claim Objections
Claim 1 is objected to because of the following informalities:
In line 6 of claim 1, replace “in” with “into” for clarity.
Appropriate correction is required.
IV. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0067278 (“Seo”) in view of US 2019/0259839 (“Ryu-839”) and US 2020/0152753 (“Huh”).
Claim 1 reads,
1. A method for fabricating a semiconductor device, comprising:
[1] providing a substrate;
[2] forming a capping mask layer on the substrate;
[3] forming a first trench along the capping mask layer and extending to the substrate;
[4] conformally forming a layer of first insulating material in the first trench;
[5] forming a first work function layer on the layer of first insulating material and in the first trench;
[6] forming a first conductive layer on the first work function layer and in the first trench; and
[7] forming a first capping layer on the first conductive layer;
[8] wherein the first capping layer comprises germanium oxide.
With regard to claims 1-4, Seo discloses,
1. A method for fabricating a semiconductor device, comprising:
[1] providing a substrate 100 [¶ 61; Fig. 3A-3B];
[2] … [not taught] …
[3] forming a first trench 132 … extending [in]to the substrate 100 [¶ 64; Figs. 3A-3B];
[4] conformally forming a layer of first insulating material 210 in the first trench 132 [¶ 65; Figs. 4A-4B];
[5] forming a first work function layer 220 [e.g. “p-type polysilicon” (¶ 43)] on the layer of first insulating material 210 and in the first trench 132 [¶ 66; Figs. 4A-4B];
[6] forming a first conductive layer 240 [e.g. “doped germanium” (¶ 47); ¶¶ 46-47] on the first work function layer 220 and in the first trench [¶ 67; Figs. 5A-5B]; and
[7] forming a first capping layer 250 on the first conductive layer 240 [¶ 85; Figs. 2A-2B, 7A-7B];
[8] … [not taught] …
2. The method for fabricating the semiconductor device of claim 1, wherein the first conductive layer 240 comprises germanium [e.g. “doped germanium”; ¶¶ 46-47].
3. The method for fabricating the semiconductor device of claim 2, wherein the first work function layer 220 comprises silicon and/or germanium with substantially no oxygen and nitrogen [e.g. “p-type polysilicon” (¶ 43)].
4. The method for fabricating the semiconductor device of claim 3, wherein the first gate insulating layer 210 comprises silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, a high-k material, or a combination thereof [¶ 42].
With regard to features [2]-[3] of claim 1 and claim 5,
[2] forming a capping mask layer on the substrate;
[3] forming a first trench along the capping mask layer and extending to the substrate;
5. The method for fabricating the semiconductor device of claim 4, wherein the capping mask layer comprises silicon oxide, silicon oxycarbide, silicon oxycarbonitride, silicon oxynitride, silicon nitride oxide, or a combination thereof.
Fig. 10 of Seo does not show a capping mask layer having the gate insulating layer 210 positioned along said capping mask layer, as required by features [2] and [3] or the materials of the capping mask layer, as required by claim 5.
Seo does, however, disclose etching the shallow 132 and deep 134 trenches in which the gate electrodes are formed using a patterned mask (Seo: ¶ 64).
Ryu-839, like Seo, teaches a U-shaped trench gate electrode including multiple conductive layers 18, 20 stacked within a gate trench 15 and having a capping layer 21 on the upper conductive layer 20 (Ryu-839: Fig. 4H; ¶¶ 95, 100, 104, 109). Also like Seo, Ryu-839 teaches that the gate trenches 15 are etched in the substrate 11 using a patterned mask HM (Ryu-839: ¶ 95; Fig. 4A).
In addition, Ryu-839 teaches features [2] and [3] of claim 1 and claim 5, as follows:
[2] forming a capping mask layer HM positioned on the substrate 11 [Ryu-839: ¶ 95; Figs. 4A, 4H];
[3] forming a first trench 15 along the capping mask layer HM and extending [in]to the substrate 11 [¶ 95; Fig. 4A];
5. (original) The semiconductor device of claim 4, wherein the capping mask layer 15 comprises silicon oxide, silicon oxycarbide, silicon oxycarbonitride, silicon oxynitride, silicon nitride oxide, or a combination thereof [Ryu-839: ¶ 95].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the patterned silicon oxide hardmask HM of Ryu-839 to etch the gate trenches 132, 134 of Seo along the hardmask HM—as required by features [2] and [3] of claim 1 and claim 5—because Seo is merely silent as to the details such that one having ordinary skill in the art would use known processes suitable for achieving the same objective, such as the processes and structure taught in Ryu-839. (See MPEP 2143(I)(C) and (D).)
This is all of the limitations of features [2] and [3] of claim 1 and claim 5.
With regard to feature [8] of claim 1 and claim 5,
[8] wherein the first capping layer comprises germanium oxide.
Neither of Seo and Ryu-839 teaches that the capping layer 250, 21, respectively, comprises germanium oxide.
Huh, like each of Seo and Ryu-839, teaches a trench gate structure 80 including a multi-layered gate conductor 34/36/45a with a gate capping layer 60/70 filling a gate trench 25 (Huh: ¶¶ 40-44; Figs. 3A-3B). Also like each of Seo and Ryu-839, Huh teaches that the gate conductor can be multilayered, i.e. 34/36/45 (Huh: ¶¶ 43-44). Also like Seo, Huh uses a semiconductor as the gate conductor material 45a (Huh: Fig. 11B, 11C), albeit doped silicon (Huh: ¶ 37), rather than doped germanium, as used in Seo (Seo: ¶ 47, supra). However, Seo also teaches that the gate conductor 240 can be made of doped silicon (Seo: ¶ 47), as in Huh; therefore, the gate electrode materials in each of Seo and Huh overlap.
Huh further teaches that the first part 60 of the gate capping layer 60/70 may be formed by oxidizing the top surface of the upper silicon gate layer 45 to form a silicon oxide portion 60 (Huh: abstract; ¶¶ 6, 38, 84-85). Huh teaches that the oxidation process is a “thickness control process 55” (Huh: Fig. 11C; ¶¶ 84-85) that “may precisely control the thickness of the preliminary conductive pattern (indicated as 45 in FIG. 11B) to form the upper gate electrode 45a having a reference thickness.” (Huh: ¶ 84). Once the gate control process 55 is formed, the capping layer 60/70 is completed by over-filling the remaining portion of the gate trench 25 with the insulating gap fill layer 70 to be planar with the top surface of the gate dielectric 30 (Huh: Fig. 3B; ¶ 86).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the oxidation control process of Huh on the upper doped germanium gate electrode 240 of Seo, thereby forming a first gate capping layer of germanium oxide, in order to precisely control the thickness of the germanium gate electrode 240, as taught by Huh. Once complete, the remaining cap layer 250 of Seo would be formed, as taught in Seo. Thus, Huh may be seen as an improvement to Seo by providing precise thickness control. (See MPEP 2143(I)(C) and (D).)
This is all of the limitations of claims 1-5.
V. Allowable Subject Matter
Claims 6-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 reads,
6. The method for fabricating the semiconductor device of claim 5, wherein forming the first capping layer on the first conductive layer comprises:
[1] alternately and sequentially introducing a germanium precursor and an oxygen source to form a layer of first capping material filling the first trench; and
[2] performing a planarization process until a top surface of the capping mask layer is exposed to turn the layer of first capping material into the first capping layer.
While ALD is known as a process for depositing semiconductor oxides, as effectively delineated in claim 6, it is not clear that one having ordinary skill in the art would use ALD given the teaching of oxidation in Huh used in Seo (supra).
Claims 7-10 would be allowable at least for including the allowable limitations by depending from claim 6 either directly or indirectly.
VI. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2022/0122991 (“Chen”) is cited for disclosing all of the process steps of at least claim 1 but does not teach that the capping layer 307 is made of germanium oxide as required by feature [8] of claim 1. See Figs. 1-19 and associated text.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814