Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to Election/Restrictions, applicant elected claims 1-10. Election was made without traverse in the reply filed on 02/23/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Marin et al. (US 2024/0113087, hereinafter Marin) in view of Thompson.
With respect to claim 1, Marin discloses a semiconductor device (Fig. 1), comprising: an interposer (102) having a first surface (108) and a second surface (104) opposite to the first surface (Fig. 1), wherein the interposer defines a first cavity (there will be a cavity/opening to create 106, e.g. cavity/recess in the middle of 102 to create 106) and a second cavity (112) extending between the first surface and the second surface (112 extends between the top and bottom surface of the interposer); a through via (106) disposed within the first cavity (106 is inside the opening); a first electronic component (126) disposed on the second surface of the interposer (126 is on 104) and electrically connected to the TIV (126 is connected to 106); a second electronic component (114) disposed within the second cavity (114 is disposed within 112); an insulation layer disposed within the first cavity and penetrating the interposer (Para 0016 -Vias 106 may also be lined and/or filled with additional dielectric material to provide electrical insulation).
Marin does not explicitly disclose that the via is a through insulation via; and an encapsulant disposed within the second cavity and encapsulating the second electronic component.
In an analogous art, Thompson discloses that the via is a through insulation via (para 0063); and an encapsulant (Para 0057 – encapsulant 450) disposed within the second cavity (Para 0008) and encapsulating the second electronic component (Para 0008; 0057). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Marin’s device by having Thompson’s disclosure in order to protect the device during manufacturing process.
With respect to claim 2, Marin discloses a first protection layer covering the insulation layer (Para 0019 – interlayer dielectric layer formed on vias 106; wherein vias 106 may also be lined and/or filled with additional dielectric material to provide electrical insulation).
With respect to claim 3, Marin discloses a conductive pillar disposed within the second cavity and electrically connected to the second electronic component (Para 0018 – 114 may comprise of a stack of multiple devices which are electrically connected to each other).
With respect to claim 4, Marin does not explicitly disclose wherein the conductive pillar is encapsulated by the encapsulant.
In an analogous art, Thompson discloses wherein the conductive pillar is encapsulated by the encapsulant (Para 0008; 0057). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Marin’s device by having Thompson’s disclosure in order to protect the device during manufacturing process.
With respect to claim 5, Marin discloses a second protection layer (136 of fig. 1) disposed on the second surface of the interposer, wherein the second protection layer has a third surface substantially coplanar with the first surface of the interposer (top surface of 136 is coplanar with first surface of 102).
With respect to claim 6, Marin discloses wherein the third surface of the second protection layer is substantially coplanar with a fourth surface of the TIV (top surface of 136 is coplanar with top surface of 106)).
With respect to claim 7, Marin discloses a third electronic component (128) disposed on the second surface of the interposer (128 is disposed on 104), wherein the third electronic component is connected to the interposer through an adhesive layer (132 – Para 0021).
With respect to claim 8, Marin discloses wherein the third electronic component is free from overlapping the first cavity and the second cavity of the interposer (128 does not overlap 112 and a cavity to create 106 in the center of 102).
With respect to claim 9, Marin discloses a mother board (306 of fig. 3) facing the first surface of the interposer (306 faces the bottom surface of 308); and a conductive wire electrically connecting the third electronic component and the mother board (Para 0019; 0043; and 0052) .
With respect to claim 10, Marin discloses wherein the TIV is electrically connected to the mother board (Fig. 3 – vias 313 are connected to 306).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
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