Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2-4, 11-13 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Taking claim 2 as exemplary, subject matter regarding “reset” (line 8) does not appear to be properly described in the application as filed. Consequently, this raises doubt as to possession of the claimed invention at the time of filing.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-10 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Zasio et al. [US 4,924,430].
Taking claim 1 as exemplary of claims 1, 10 and 19 [column 1, line 14 by a computer, column 8, line 25 host computer connote a processing system and medium], Zasio et al. teach a method for performing timing analysis of a circuit design, the method comprising:
determining delays of devices and wires of the circuit design [column 3, lines48-58 useful combinations of delay values, for a delay-calculation equation, column 4, lines 11-27 pointer field of information, data field, column 4, lines 36-column 5, line 36 the present invention accumulated delay values, column 5, line 55-column 6, line 44, column 7, lines 4-21 it is therefore desirable to calculate and accumulated information about circuit delays];
performing clock and arrival propagations for the circuit design based on the delays of the devices and wires [column 4, lines 29-35 set-up clock violation check];
identifying latch loops in the circuit design [Fig. 9C Feedback Loop Break-Up Algorithm, FIG. 16 ];
performing latch analysis on latches of the latch loops [Fig. 9C Feedback Loop Break-Up Algorithm, FIG. 12a, FIG. 13a Latch Model Timing, FIG. 14a Latch Delay Timing, FIG. 16a Latch Delay Timing, FIG. 15];
performing arrival propagation for circuit elements of the circuit design impacted by the latch analysis performed on the latches of the latch loops [Fig. 9c Has Every Cell in the Design Been Completely Processed?, FIG. 12f Done with Feedback Loop Break-Up Algorithm, FIG. 13a for each path];
performing latch analysis on latches of the circuit design external to the latch loops [Fig. 9c Has Every Cell in the Design Been Completely Processed? Fig. 11 for each path specified, FIG. 12c Multi-Chip Timing, FIG. 13a for each path, FIG. 14b Multi-Chip Timing, FIGS. 17-19]; and
performing required time and slack calculations on the circuit design [column 9, lines 1-3, column 10, lines 16-45]. In other words, to create the latch timing model for latch analysis latch loops are identified for the feedback loop breakup algorithm to perform arrival propagation for elements impacted with each path and all paths in the design subject to multi-chip timing for analysis of the circuit design external to the latch loops processed, resulting in performing the required time and slack calculations on the circuit design through all levels.
However, Zasio et al. do not teach building a timing graph and determining delays based on the timing graph. Yet, static timing analysis is known to be based on graphs which provide the data structures for the timing information. Zasio et al. do teach a net list [FIG. 7 netlist creation, which is known as a representation of the design. Thus, using a timing graph, which is also known as a version of a netlist that has been augmented with timing information, can be interpreted as essential and understood for performing timing analysis. The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains because the information greatly facilitates rapid identification of paths in excess of selected delay limits, can designate the fastest clock cycle time at which the proposed logic design can be operated without design-rule failures or logic failures, facilitate logic design modifications prior to fabricating [column 12, lines 12-31].
Taking claim 5 as exemplary of claims 5 and 14, wherein performing the latch analysis on the latches of the latch loops comprises performing iterations of latch timing calculations and propagating data arrivals across the circuit design associated with the latch loops until latch timing converges for the latches of the latch loops [Fig. 9C Feedback Loop Break-Up Algorithm, FIG. 12a, FIG. 13a Latch Model Timing, FIG. 14a Latch Delay Timing, FIG. 16a Latch Delay Timing, FIG. 15].
Taking claim 6 as exemplary of claims 6 and 15, wherein performing the latch analysis on the latches of the latch loops comprises performing maximum data arrival propagation on the latch loops, and wherein minimum data arrival propagation is disabled when performing the latch analysis on the latches of the latch loops [column 1, lines 49-52 indications best- and worst-case operating condition, column 6, lines 19-44 Worst-Case].
Taking claim 7 as exemplary of claims 7 and 16, wherein the latch timing converges for a latch when arrival at an input data pin of the latch does not worsen or a maximum amount of time has been borrowed for the latch [until timing converges is broadly interpreted as does not worsen].
Taking claim 8 as exemplary of claims 8 and 17, wherein performing the arrival propagation for the impacted circuit elements comprises performing maximum data arrival propagation and minimum data arrival propagation on the impacted circuit elements of the circuit design based on the latch analysis on the latches of the latch loops [column 1, lines 49-52 indications best- and worst-case operating condition, column 6, lines 39-44, Best-Case to Worst-Case, column 6, line 59-column 7, line 15 Best-Case conditions, Worst-Case conditions].
Taking claim 9 as exemplary of claims 9 and 18, wherein performing latch analysis on the latches of the circuit design external to the latch loops comprises performing iterations of latch timing calculations and propagating data arrivals across the latches external to the latch loops based on the latch analysis performed on the latch loops and subsequent arrival propagation until timing converges for the latches external to the latch loops [Fig. 9c Has Every Cell in the Design Been Completely Processed? Fig. 11 for each path specified, FIG. 12c Multi-Chip Timing, FIG. 13a for each path, FIG. 14b Multi-Chip Timing, FIGS. 17-19].
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Segal et al. [US 6,023,568] disclose a latch timing model for timing borrowing and chains (see entire document). Sutherland et al. [US 12,475,286 B1] disclose timing graphs and tags (see entire document). Spyrou et al. [US 10,223,493 B1] discloses dynamic tag allocation in timing analysis (see entire document). Moon et al. [US 6,928,630 B2] disclose timing graph reduction (see entire document). Becker et al. [US 2003/0088838 A1] disclose time borrowing in timing analysis (see at least FIGS. 4 and 9). Hathaway et al. [US 2002/0112195 A1] disclose timing analysis and timing graph (see entire document).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEIGH M GARBOWSKI whose telephone number is (571)272-1893. The examiner can normally be reached M-F 9-5 EST.
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/LEIGH M GARBOWSKI/ Primary Examiner, Art Unit 2851
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