DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 17 is objected to because of the following informalities: Aluminum oxide is not Al. It should be AlO, or Al2O3.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dubin et al. (U.S. Patent No. 7,008,872).
Regarding to claim 16, Dubin teaches semiconductor structure, comprising:
a first interlayer dielectric (ILD) layer (Fig. 14, element 104);
a first metal layer, embedded in the first interlayer dielectric layer (Fig. 14, element 112);
a metal capping layer, disposed on the first metal layer (Fig. 14, element 114);
an etching stop bi-layer structure, including:
a self-aligned etching stop layer, disposed on the metal capping layer (Fig. 14, column 6, lines 5-8, please also see Fig. 11, portion of layer 114 under the opening 128. The portion prevents the metal 112 from being etched when the opening 128 is formed); and
a conformal etching stop layer, disposed on the first interlayer dielectric layer and the self-aligned etching stop layer (Fig. 14, please also see Fig. 11, element 108. The portion of layer 108 prevents the metal 112 from being etched when the opening 128 is formed);
a second interlayer dielectric (ILD) layer, disposed on the etching stop bi-layer structure (Fig. 14, element 116);
a via, embedded in the second interlayer dielectric layer (Fig. 14, element 138); and
a second metal layer, embedded in the second interlayer dielectric layer and disposed on the via (Fig. 14, element 144).
Regarding to claim 18, Dubin teaches a thickness of the self-aligned etching stop layer is 1 A to 100 um (column 6, lines 3-5).
Examiner’s note: the claimed upper limit and lower limit are unrealistic because one Angstrom is smaller than dimension of a metal atom, and metal layers in semiconductor chip is never to be 100 microns. Typically, it is in the range of 500A to 5000A (less than one micron). The claimed range is too broad such that it is inherently met by any metal layer in a chip.
Regarding to claim 19, Dubin teaches the self-aligned etching stop layer only covers the metal capping layer (column 6, lines 5-9, portion of cap layer 114 becomes self-aligned etching stop layer, thus this portion only covers the metal capping layer).
Regarding to claim 20, Dubin teaches the etching stop bi-layer structure further includes:
a first hermetic layer, disposed between the first interlayer dielectric layer and the conformal etching stop layer, and disposed between the self-aligned etching stop layer and the conformal etching stop layer (Fig. 12, portion of layer 132 between layer 114 and 108); and
a second hermetic layer, disposed on the conformal etching stop layer (Fig. 12, portion of layer 132 on layer 108).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Dubin et al. (U.S. Patent No. 7,008,872) in view of Lee et al. (U.S. Patent No. 7,101,790).
Regarding to claim 1, Dubin teaches a manufacturing method of a semiconductor structure, comprising:
forming a trench in a first interlayer dielectric (ILD) layer (Fig. 1; column 4, lines 4-5, forming trench 106 in first interlayer dielectric 104);
filling a metal conductor in the trench (Figs. 2-3, element 112; column 4, lines 53-55);
performing planarization on the metal conductor (Fig. 4, element 112; column 5, lines 10-13);
performing a thermal treatment, a photo treatment or a bias-assist treatment on the metal conductor (column 7, lines 54-56, thermal treatment);
forming a metal capping, etching stop layer on a first metal layer (Fig. 5, element 114; column 6, lines 5-7);
forming a via (Fig. 8, element 118B), a second interlayer dielectric (ILD) layer (Fig. 7, element 116) and a second metal layer (Fig. 9, element 124) on the etching stop bi-layer structure, wherein the via is embedded in the second interlayer dielectric layer and the via is disposed between the first metal layer and the second metal layer (Fig. 7, the via is embedded in the second interlayer dielectric layer 116 and the via is disposed between the first metal layer 112 and the second metal layer 124).
Dubin does not disclose the metal conductor is with metal dopants, the thermal treatment on
the metal conductor with the metal dopants to form a self-forming metal capping layer
on a first metal layer, and the etching stop layer is an etching stop bi-layer structure.
Lee discloses filling a metal conductor with metal dopants in the trench (Fig. 1, column 6, lines 32-36), performing a thermal treatment to form a self-forming metal capping layer on a first metal layer (column 6, lines 44-49), and forming an etching stop bi-layer structure (Fig. 1F, elements 14A and 14B; column 4, line 37). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dubin in view of Lee to dope the metal conductor with metal dopants so that the anneal process self-form metal capping layer on a first metal layer, and to form the etching stop layer as a bi-layer structure in order to increase reliability with a simpler fabrication process.
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Regarding to claim 2, Lee discloses a selection of metal dopants (column 5, lines 26-29). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to select Vanadium (V), Niobium (Nb), Molybdenum (Mo), Tungsten (W) or Manganese (Mn), as metal dopant for obtain desired resistivity, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
Regarding to claim 3, Lee discloses in the filling the metal conductor with the metal dopants in the trench, the metal conductor with the metal dopants is filled by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Electro Chemical Plating (ECP) or Electroless plating (column 6, lines 21-25).
Regarding to claim 4, Lee discloses in the filling the metal conductor with the metal dopants in the trench, a process temperature is 10°C to 400 °C (column 7, lines 20-25, PVD or CVD is known at 300 °C to 400 °C, ECD process in known at near room temperature).
Regarding to claim 5, Lee discloses the thermal treatment is performed by a hotplate, the photo treatment is performed by a laser, and the bias-assist treatment is performed by applying a voltage (column 6, lines 44-49).
Regarding to claim 6, Lee discloses in the performing the thermal treatment, the photo treatment or the bias-assist treatment on the metal conductor with the metal dopants to form the self-forming metal capping layer on the first metal layer, a process temperature is 10 °C to 400 °C (column 67, lines 46-48).
Regarding to claim 7, Lee discloses a process temperature in the filling the metal conductor with the metal dopants in the trench is lower than a process temperature in the performing the thermal treatment, the photo treatment or the bias-assist treatment on the metal conductor with the metal dopants to form the self-forming metal capping layer on the first metal layer (column 6, lines 16, lines 44-47, the metal conductor with the metal dopants in the trench is near room temperature, the thermal treatment is at 200 °C to 350 °C).
Regarding to claim 8, Lee discloses a thickness of the self-forming metal capping layer is 1A to 100 µm (column 5, lines 50-55).
Examiner’s note: the claimed upper limit and lower limit are unrealistic because one Angstrom is much smaller than dimension of an atom, and metal layers in semiconductor chip is never to be 100 microns. Typically, it is in the range of 500A to 5000A (less than one micron). The claimed range is too broad such that it is inherently met by any metal layer in a chip.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Dubin et al. (U.S. Patent No. 7,008,872), as applied to claim 16 above, in view of Rainville et al. (U.S. Patent No. 9,859,153).
Regarding to claim 17, Dubin is silent as to material of the self-aligned etching stop layer. Rainville discloses a material of an etching stop layer is Zirconium oxide or Aluminum oxide (column 3, lines 63-64). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dubin in view of Rainville to configure aluminum oxide as material of the self-aligned etching stop layer in order to increase resisting to etching chemicals.
Allowable Subject Matter
Claims 9-15 are allowed. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 9, the prior art fails to anticipate or render obvious the combination of limitations including “performing a thermal treatment, a photo treatment or a bias-assist treatment on the metal conductor with the metal dopants to form a self-aligned etching stop layer and a first metal layer, wherein the self-aligned etching stop layer is formed on the metal capping layer; forming a conformal etching stop layer on the first interlayer dielectric layer and the self-aligned etching stop layer to form an etching stop bi-layer structure”.
Comparing to the prior-art of the record, the most relevant prior art is Dubin et al. (U.S. Patent No. 7,008,872).
Dubin discloses a manufacturing method of a semiconductor structure, comprising:
forming a trench in a first interlayer dielectric (ILD) layer (Fig. 1, element 106; column 4, lines 4-5);
filling a metal conductor in the trench (Figs. 2-3, element 112; column 4, lines 53-55; column 6, lines 26-30, copper doped with nickel);
performing planarization on the metal conductor with the metal dopants (Fig. 4, element 112; column 5, lines 10-13);
forming a metal capping layer on the metal conductor with the metal dopants (Fig. 5, element 114);
performing a thermal treatment, a photo treatment or a bias-assist treatment on the metal conductor with the metal dopants (column 7, lines 57-56, thermal treatment);
forming a via (Fig. 7, element 118), a second interlayer dielectric (ILD) layer (Fig. 7, element 116) and a second metal layer (Fig. 9, element 124) on the etching stop bi-layer structure, wherein the via is embedded in the second interlayer dielectric layer and the via is disposed between the first metal layer and the second metal layer (Fig. 7, the via is embedded in the second interlayer dielectric layer 116 and the via is disposed between the first metal layer 112 and the second metal layer 124).
US-20210407852-A1US-9859153-B1, US-11145751-B2, US-10304729-B2US-12394716-B2, US-9406555-B2US-6258710-B1, US-7776743-B2, US-20220293512-A1, and US-6130161-A, are cited as teaching some of the elements and features of the claimed invention. However, the cited references, and the pertinent prior art, when taken alone or in combination, cannot be reasonably construed as adequately teaching or suggesting all of the elements and features of the claimed invention as arranged in the manner as claimed by the Applicants.
Claims 10-15 are allowable for, at least, the same reasons with claim 9 which they are dependent from.
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897