Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Election was made without traverse in the reply filed on 1/23/2026. Applicant has elected Group II, corresponding to claims 1-7. Invention Group I, corresponding to 8-20, is withdrawn from further consideration. The examiner acknowledges the applicant’s cancellation of claims 8-20.
Specification
The specification revisions submitted 1/23/2026 have been accepted by the examiner.
Drawings
The drawings submitted on 10/19/2023 have been accepted by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Hwu (US # 20210057488) in view of Guo (US # 20240339457).
Regarding Claim 1, Hwu (US # 20210057488) teaches a structure (see Fig. 10F and corresponding text) with a capacitor (C) and a fin transistor (T), comprising:
a substrate (110) comprising a capacitor region (region corresponding to C) and a fin transistor region (region corresponding to T);
PNG
media_image1.png
422
753
media_image1.png
Greyscale
a mesa (118) disposed within the capacitor region of the substrate, wherein the mesa protrudes from a surface of the substrate (shown), the mesa comprises a top surface (uppermost surface of 118) and two sloping surfaces (the side surfaces of 118 are inherently not perfectly vertical), and each of the sloping surfaces connects to the top surface of the mesa and the surface of the substrate (side surfaces are shown as recited);
a capacitor electrode (190) only disposed on the top surface of the mesa (shown indirectly on the top surface); and
a capacitor dielectric layer (252) disposed between the capacitor electrode and the doping region.
Although Hwu discloses much of the claimed invention, it does not explicitly teach the structure comprising a doping region disposed within the mesa.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
For example, Guo (US # 20240339457) is in the same or analogous field, and it teaches a capacitor structure (see Fig. 1B; region 120) comprising a lower conductive feature (NWELL 122) which is a doping region (N-doped) within a silicon layer (116).
A person having ordinary skill in the art would have recognized that modifying the doping of the semiconductor mesa of Hwu with the doping region suggested by Guo would be obvious. Specifically, the modification suggested by Guo would be to employ a structure comprising a doping region disposed within the mesa. The rationale for this obvious modification is that doping provides conductive characteristic for a functional capacitor. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of doping silicon for a capacitor are well known in the art (see MPEP 2144.01).
Regarding Claim 2, Hwu teaches the structure with a capacitor and a fin transistor of claim 1, further comprising a spacer (140) disposed on one side of the capacitor electrode, wherein the spacer is only disposed on the top surface of the mesa (shown).
Regarding Claim 5, Hwu teaches the structure with a capacitor and a fin transistor of claim 1, further comprising a shallow trench isolation (120) disposed on the surface of the substrate and contacts one of the two sloping surfaces (shown in Fig. 10F).
Regarding Claim 7, Guo, as applied to claim 1, teaches the structure with a capacitor and a fin transistor of claim 1, wherein the doping region comprises phosphorus or arsenic ([0024]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hwu (US # 20210057488) in view of Guo (US # 20240339457) and Yang (US # 20230378376).
Regarding Claim 6, Hwu teaches the structure with a capacitor and a fin transistor of claim 1, further comprising:
a fin structure (116) disposed in the fin transistor region, wherein the fin structure protrudes from the surface of the substrate (shown);
a conductive gate (184) crossing the fin structure; and
a gate dielectric layer (182) disposed between the conductive gate and the fin structure.
Although Hwu discloses much of the claimed invention, it does not explicitly teach the structure wherein the conductive gate and the capacitor electrode have the same stacked material layer.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
For example, Yang (US # 20230378376) is in the same or analogous field, and it teaches a structure (see Fig. 5 and corresponding text) wherein a conductive gate (120’) and a capacitor electrode (120) have the same stacked material layer (see [0043-44]).
A person having ordinary skill in the art would have recognized that modifying the conductive materials of Hwu in view of Guo with the stacked materials suggested by Yang would be obvious. Specifically, the modification suggested by Yang would be to employ a structure wherein the conductive gate and the capacitor electrode have the same stacked material layer. The rationale for this obvious modification is that using the same materials provides a more efficient manufacturing flow. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of minimizing materials variety are well known in the art (see MPEP 2144.01).
Allowable Subject Matter
Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, although the prior art shows substantial features of the claimed invention, the prior art reviewed by the examiner neither teaches nor reasonably suggests all the claimed limitations, including wherein the spacer covers the top surface of the mesa and one of the two sloping surfaces of the mesa.
Regarding Claim 4, although the prior art shows substantial features of the claimed invention, the prior art reviewed by the examiner neither teaches nor reasonably suggests all the claimed limitations, including wherein the capacitor dielectric layer comprises a silicon oxide layer, and the silicon oxide layer contacts and covers the top surface of the mesa and the two sloping surfaces of the mesa.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899