Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group II in the reply filed on 01/29/26 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 14-20 and 28-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., US 2021/0233997 in view of Park et al., US 2023/0253307.
Chen et al. shows the invention substantially as claimed including a manufacturing method for a semiconductor device, comprising:
Forming a stack structure 64 on a substrate, wherein the stack structure comprises an active channel sheet layer (52,54);
Forming a first dielectric layer material (80/81) over the stack structure;
Removing a portion of the stack structure and a portion of the first dielectric layer material to form an active structure and the first dielectric layer, wherein the active structure comprises the active channel sheet having a first lateral surface, and the first dielectric layer has a recess recessed with respect to the first lateral surface of the active channel sheet; and forming a second dielectric layer (82/83) within the recess, wherein the second dielectric layer that forms a spacer (83) can be silicon oxycarbonitride (see paragraphs 0017-0042 and figs. 3-9B).
Chen et al. does not expressly disclose where the silicon oxycarbonitride layer has a dielectric constant of less than 3.9. Park et al. discloses the formation of a silicon oxycarbonitride spacer that has a dielectric constant of from 2.8-3.5 (see paragraph 0034). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the process of Chen et al. so as to form the second dielectric silicon oxycarbonitride layer to have a dielectric constant less than 3.9 because Park et al. discloses the suitability and conventionality of forming silicon oxycarbonitride spacers having a dielectric constant within the claimed range.
Regarding dependent claims 15 and 30, note that Chen et al. further discloses the method further comprises:
Forming a third dielectric layer (78) over the first dielectric layer (81); and
Forming an epitaxy layer (92) adjacent to the active structure; wherein
After forming the epitaxy layer adjacent to the active structure, the manufacturing method further comprises removing the third dielectric layer (see, for example, figs. 12B-13B).
Concerning dependent claims 16 and 31, note that Chen et al. discloses wherein in forming the third dielectric layer over the first dielectric layer, the third dielectric layer is formed of a material different from that of the first dielectric layer material (see paragraphs 0034 and 0038-0039).
As to dependent claims 17 and 32, note that in Chen et al. wherein in removing the portion of the stack structure and the portion of the first dielectric layer material to form the active structure and the first dielectric layer, the first lateral surface and the second lateral surface are flushed with each other (see fig. 9B and its description).
Concerning dependent claims 18 and 33, note that the semiconductor device comprises a plurality of active structures and there is a trench (for example, (68)) between adjacent two of a plurality of the active structures; the manufacturing method comprises: forming an isolation layer on a bottom of the trench to form shallow trench isolation regions 68; wherein in forming the epitaxy layer (92) adjacent to the active structure, the epitaxy layer (92) is formed on the isolation layer (see, for example, fig. 11C).
With respect to dependent claim 19, note that in Chen et al. in forming the second dielectric layer within the recess, the second dielectric layer comprises a first portion and a second portion, the first portion is formed within the recess and extends in a first direction, and the second portion is connected with the first portion and extends in a second direction perpendicular to the first direction (see, for example, figs. 7B and 9B).
Regarding dependent claim 20, note that in Chen et al. in forming the second dielectric layer (82/83) within the recess, the second dielectric layer protrude beyond the first lateral surface of the active channel sheet (see, for example, fig. 10B).
As to independent claim 28, Chen et al. shows the invention substantially as claimed including a manufacturing method for a semiconductor device, comprising:
Forming a stack structure 64 on a substrate, wherein the stack structure comprises an active channel sheet layer (52,54);
Forming a dummy gate structure 76 on the stack structure (see paragraph 0035 and fig. 6);
Forming a first dielectric layer material (80/81) over the stack structure;
Removing a portion of the stack structure and a portion of the first dielectric layer material to form an active structure and the first dielectric layer, wherein the active structure comprises the active channel sheet having a first lateral surface, and the first dielectric layer has a recess recessed with respect to the first lateral surface of the active channel sheet; and forming a second dielectric layer (82/83) within the recess, wherein the second dielectric layer that forms a spacer (83) can be silicon oxycarbonitride (see paragraphs 0017-0042 and figs. 3-8B).
Chen et al. does not expressly disclose where the silicon oxycarbonitride layer has a dielectric constant of less than 3.9. Park et al. discloses the formation of a silicon oxycarbonitride spacer that has a dielectric constant of from 2.8-3.5 (see paragraph 0034). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the process of Chen et al. so as to form the second dielectric silicon oxycarbonitride layer to have a dielectric constant less than 3.9 because Park et al. discloses the suitability and conventionality of forming silicon oxycarbonitride spacers having a dielectric constant within the claimed range.
Regarding dependent claim 29, note that Chen et al. discloses wherein in removing the portion of the stack structure and the portion of the first dielectric layer material to form the active structure and the first dielectric layer, the first dielectric layer comprises a lateral portion and a bottom portion, the lateral portion covers sidewall of the dummy gate structure, and the bottom portion covers a top of the active structure (see, for example, fig. 7B and its description).
Allowable Subject Matter
Claims 21-27 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, particularly US 2021/0233997, either singly or in combination, fails to anticipate or render obvious, the following limitations in combination with the claimed limitations: forming a third dielectric layer over the first dielectric layer; forming an epitaxy layer adjacent to the active structure, wherein a plurality of nodules remain on a sidewall of the third dielectric layer; and removing the nodules, as required by independent claim 21. Chen, US 2021/0233997 does not disclose the presence or removal of nodules from the third dielectric layer as claimed.
Additional Cited Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2026/0090052 discloses the formation of an active channel sheet and source/drain epitaxy layer (see abstract), and Lee et al., US 2026/0006845, discloses the formation of a recessed source/drain layer adjacent an active channel sheet layer (see fig. 6A and paragraphs 0063-0099).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
May 14, 2026
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