Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species II (reading on the method of Fig. 3K) and Subspecies I(b) (reading on the layer configuration of Fig. 3L) in the reply filed on 2/26/2026 is acknowledged.
Claims 5-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/26/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/14/2024 and 10/15/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "236" and "336" have both been used to designate the same dielectric layer. More specifically: Fig. 4G uses reference character 336 while all other figures in figure set 4 use reference character 236. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: Paragraph [0110] of the written description designates reference character 426 for the solid low-k layer. However, this designation is inconsistent with the drawings, which use reference character 246.
Appropriate correction is required.
Claim Objections
Claim 13 is objected to because of the following informalities: “sidewalls of the first trench” in line 3. For the sake of compact prosecution, claim 13 is interpreted in the instant Office action as follows: “sidewalls of the first trench” is found to be a typographical error and is believed to be equivalent to “the sidewalls of the first trench” based on antecedence for this term in claim 1, line 5; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-4, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20220223601 A1) in view of Okamura (US 20250169217 A1) and Kim (US 20180145080 A1).
Regarding claim 1, Lin discloses a method of manufacturing a memory device, comprising:
providing a substrate (Fig. 1A: 102) including an upper surface;
performing a first etching operation (Fig. 1B) to form a first trench (106) in the substrate;
depositing a first dielectric layer (Fig. 1C: 108; [0020]: “silicon oxide, silicon nitride, silicon oxynitride, and/or high-k dielectric material”) on sidewalls of the first trench;
forming a first gate electrode (112) in the first trench and laterally surrounded by the first dielectric layer;
depositing a second dielectric layer (Fig. 1K: 120; [0034]: “silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and/or a combination thereof”) and forming a low-k layer (Fig. 1O: 128) in the first trench over the first gate electrode,
wherein the low-k layer includes a dielectric constant ([0039]: “air gaps”) less than that of the first dielectric layer and the second dielectric layer (See additional remarks below);
depositing a capping layer (126) over the first gate electrode to fill the first trench; and
depositing a third dielectric layer to cover the low-k layer.
Illustrated below is Fig. 1O of Lin.
PNG
media_image1.png
470
357
media_image1.png
Greyscale
Lin teaches the first and second dielectric layers and the low-k layer; and teaches material compositions for these layers. However, Lin fails to explicitly teach the dielectric constants for these layers (physical properties). Thus, Lin fails to explicitly teach “the low-k layer includes a dielectric constant less than that of the first dielectric layer and the second dielectric layer”. Nevertheless, dielectric constants for each of these compositions is known in the art.
Okamura discloses the dielectric constant of silicon oxide is 3.9 ([0197]: “the relative dielectric constant of silicon oxide (SiO2) forming the insulating film 414 is 3.9”) and the dielectric constant of air is 1.0 ([0197]: “the relative dielectric constant of air is 1.0”). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success having the claimed dielectric constants (of Okamura) because Lin teaches using these same material compositions: the composition of the first and second dielectric layers may include silicon oxide ([0020]: “silicon oxide”; [0034]: “silicon oxide”); and the composition of the low-k layer may include air ([0039]: “air gaps”). Therefore, the claimed dielectric constant configuration would have been obvious to one of ordinary skill in the art before the effective filing date because these physical properties were known in the prior art. MPEP 2112 (III).
Lin in view of Okamura fails to teach “depositing a third dielectric layer to cover the low-k layer”.
Kim discloses a method comprising: depositing a third dielectric layer (Fig. 17: 151a) to cover the low-k layer (140a). Modifying the method of Lin in view of Okamura by including the third dielectric layer of Kim in the same way would arrive at the claimed method configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation an air gap is formed in a trench (Lin: Fig. 1O: air gap 128; Kim: Fig. 5: air gap 140a). Kim provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the third dielectric layer in that it would improve the formation of the low-k layer (Kim: [0066]: “the first air gap 140a may be formed more easily… poor step coverage”; [0109]: “poor step coverage”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the method include the claimed third dielectric layer because it would improve the formation of the low-k layer. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 17 of Kim.
PNG
media_image2.png
367
278
media_image2.png
Greyscale
Regarding claim 2, Lin in view of Okamura and Kim discloses the method of claim 1, wherein the low-k layer includes an air gap (Lin: [0039]: “air gaps”).
Regarding claim 3, Lin in view of Okamura and Kim discloses the method of claim 2 (Kim: Fig. 17), wherein the depositing of the third dielectric layer is performed using chemical vapor deposition ([0109]: “a chemical vapor deposition (CVD) method”) to close the air gap ([0109]: “the first air gap 140a may remain”).
Regarding claim 4, Lin in view of Okamura and Kim discloses the method of claim 2 (Kim: Fig. 17), wherein the third dielectric layer comprises non-uniform thicknesses (thicknesses A and B, See annotated figure) across a first location over the air gap and a second location over the capping layer or the second dielectric layer (thicknesses A and B are different, thus the layer comprises “non-uniform thicknesses”).
Regarding claim 13, Lin in view of Okamura and Kim discloses the method of claim 1, wherein the depositing of the second dielectric layer is performed using atomic layer deposition ([0034]: “may be deposited using CVD and/or ALD”) to form the second dielectric layer on sidewalls of the first trench in a conformal manner (at least indirectly on).
Claims 1 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Kim, Kang (US 20160315088 A1), and Okamura.
Note that claim 1 was previously addressed above, however, it’s being addressed differently here based on the reading of the reference, particularly to the assignment of the second dielectric layer in order to address the dependent claim 14.
Regarding claim 1, Lin discloses a method of manufacturing a memory device, comprising:
providing a substrate (Fig. 1A: 102) including an upper surface;
performing a first etching operation (Fig. 1B) to form a first trench (106) in the substrate;
depositing a first dielectric layer (Fig. 1C: 108; [0020]: “silicon oxide, silicon nitride, silicon oxynitride, and/or high-k dielectric material”) on sidewalls of the first trench;
forming a first gate electrode (112) in the first trench and laterally surrounded by the first dielectric layer;
depositing a second dielectric layer and forming a low-k layer (Fig. 1O: 128) in the first trench over the first gate electrode,
wherein the low-k layer includes a dielectric constant ([0039]: “air gaps”) less than that of the first dielectric layer and the second dielectric layer (See additional remarks below);
depositing a capping layer (126) over the first gate electrode to fill the first trench; and
depositing a third dielectric layer to cover the low-k layer.
Lin fails to teach “depositing a third dielectric layer to cover the low-k layer”.
Kim discloses a method comprising: depositing a third dielectric layer (Fig. 17: 151a) to cover the low-k layer (140a). Modifying the method of Lin by including the third dielectric layer of Kim in the same way would arrive at the claimed method configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation an air gap is formed in a trench (Lin: Fig. 1O: air gap 128; Kim: Fig. 5: air gap 140a). Kim provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the third dielectric layer in that it would improve the formation of the low-k layer (Kim: [0066]: “the first air gap 140a may be formed more easily… poor step coverage”; [0109]: “poor step coverage”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the method include the claimed third dielectric layer because it would improve the formation of the low-k layer. MPEP 2143 (I)(G).
Lin in view of Kim fails to teach “depositing a second dielectric layer”.
Kang discloses a method of manufacturing a memory device (Fig. 17), comprising: depositing a second dielectric layer (816). Modifying the method of Lin and Kim by including the second dielectric layer of Kang would arrive at the claimed method and layer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Lin teaches the method of manufacturing the memory device includes additional steps subsequent to those illustrated (Lin: [0040]: “additional features…”). Kang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the claimed method and layer configuration in that it would enable producing a functional memory device (Kang: [0275]: “memory cell 800 is applied to DRAM”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed method and layer configuration because it would enable producing a functional memory device. MPEP 2143 (I)(G).
Illustrated below is Fig. 17 of Kang.
PNG
media_image3.png
376
379
media_image3.png
Greyscale
Lin in view of Kim and Kang teaches the first and second dielectric layers and the low-k layer; and teaches material compositions for these layers. However, Lin and Kim fail to explicitly teach the dielectric constants for these layers (physical properties). Thus, Lin, Kim, and Kang fail to explicitly teach “the low-k layer includes a dielectric constant less than that of the first dielectric layer and the second dielectric layer”. Nevertheless, dielectric constants for each of these compositions is known in the art.
Okamura discloses the dielectric constant of silicon oxide is 3.9 ([0197]: “the relative dielectric constant of silicon oxide (SiO2) forming the insulating film 414 is 3.9”) and the dielectric constant of air is 1.0 ([0197]: “the relative dielectric constant of air is 1.0”). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success having the claimed dielectric constants (of Okamura) because Lin and Kim teach using these same material compositions: the composition of the first and second dielectric layers may include silicon oxide (Lin: [0020]: “silicon oxide”; Kang: [0270]: “silicon oxide”); and the composition of the low-k layer may include air (Lin: [0039]: “air gaps”). Therefore, the claimed dielectric constant configuration would have been obvious to one of ordinary skill in the art before the effective filing date because these physical properties were known in the prior art. MPEP 2112 (III).
Regarding claim 14, Lin in view of Kim, Kang, and Okamura discloses the method of claim 1, wherein the depositing of the capping layer is performed prior to the depositing of the second dielectric layer (Kang teaches depositing a capping layer Fig. 17: 809 prior to the 2nd dielectric layer 816. This sequence corresponds to the capping layer of Lin).
Allowable Subject Matter
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claim 15 is the inclusion of the limitation “etching an upper portion of the first dielectric layer to form a second trench, wherein the second dielectric layer and the low-k layer are formed in the second trench” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “second dielectric layer” and “formed in the second trench” in combination with all other limitations in claims 15, 14, and 1. More specifically, the method requires the second dielectric layer to be formed with a particular sequence in relation to other layers, as well as with a particular spatial configuration in relation to trenches. The combination of these limitations when considered with all other limitations of the claim was not found or rendered obvious within the prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM H ANDERSON/ Examiner, Art Unit 2817