CTFR 18/381,889 CTFR 98357 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendment Applicant’s amendments filed 4/13/2026 have been entered and considered. The amendments to claims 1, 5, 6, and 8 are acknowledged. Response to Arguments 07-37 AIA Applicant's arguments filed 4/13/2026 regarding a dicing path have been fully considered but they are not persuasive. Applicant alleges that Chen fails to anticipate a dicing path formed on the scribe line region and arranged for being diced along the dicing path to separate the scribe line region from the die region. The examiner disagrees for the following reasons: Chen teaches in para. 0049 that "a dicing region may include markers (e.g., dicing lines, optical alignment structures, etc.) arranged for separating the dies during a wafer dicing process". This suggests that a dicing apparatus follows the markers along the “dicing regions 120” so that the dies are separated. Furthermore, the application fails to teach what structure comprises the dicing path, but instead says that dicing path is defined. Lines and areas can be arbitrarily defined and are not considered a structure. Applicant’s arguments with respect to the limitation “each die region comprises functional circuitry located under the bump pads” have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument . Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre - AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim recites that “a dicing path is formed on the scribe line”. Though the examiner acknowledges the indication of “dicing path 122” in para. 0071 FIG. 3A, there is not passage in the specification that teaches the formation of a dicing path, but rather that the “dicing path 122” is defined on the “scribe line region 121”. There is no indication that the dicing path is a structural feature of or on the scribe line. For purposes of examination, the dicing path will be considered as the path along which the means of dicing is meant to pass. Claims 2-9 are rejected based on the dependency on claim 1. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1-3, 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. US 20230120504 A1 (hereinafter referred to as Chen), in view of Rashid et al. US 20070275539 A1 (hereinafter referred to as Rashid) . Regarding claim 1 , Chen teaches A semiconductor device (“example wafer 100”, para. 0049 FIG. 1A-1C), comprising: a plurality of die regions (“plurality of dies 110aa, 110ab, 110ba, 110bb”, para. 0049 FIG. 1B-1C), disposed on a semiconductor wafer (“semiconductor substrate 102” para. 0049); a scribe line region ("dicing region 120" para. 0049), disposed between the plurality of die regions ("dicing region 120" is between the “plurality of dies 110aa, 110ab, 110ba, 110bb”), wherein a dicing path is formed on the scribe line region and is arranged for being diced along the dicing path to separate the scribe line region from the die region ("a dicing region may include markers (e.g., dicing lines, optical alignment structures, etc.) arranged for separating the dies during a wafer dicing process", para. 0049, such that it is understood dicing is conducted along a path in the “dicing region 120”.) a plurality of bump pads (“device pads 160” para. 0050), disposed on a first top surface of an edge region of each die region (“device pads 160” are disposed on an edge portion of the surface of “die 110aa”), wherein the bump pads are disposed within one of the die regions (“device pads 160” are within the area of each die); a plurality of circuit probing pads (“test pads 170”), disposed on a second top surface of the scribe line region (“testing pads 170” are in the “dicing region 120” on “example wafer 100”); and a plurality of metal wires (“wiring structures 180” para. 0054), disposed on the first top surface of each die region and the second top surface of the scribe line region, and configured to electrically connect the plurality of bump pads to the corresponding circuit probing pads (“wiring structures 180” extend along the top surface of “example wafer 110” to connect “device pads 160” in the “die 110aa” to the “testing pads 170” in the “dicing region 120”, para. 0054); wherein each die region comprises functional circuitry (each die includes an “active area 140” that includes one or more active devices, such that it is understood that the circuitry in “dies 110aa, 110ab, 110ba, 110bb, etc.” comprises functional circuitry), and the scribe line region is a non-functional region (no active devices are taught in the “dicing region 120”, such that the region may be considered non-functional after a dicing operation); wherein a center of each circuit probing pad is disposed on a center line of the scribe line region (FIG. 1C suggests that “testing pads 170” are aligned in a substantially central area of “dicing region 120”). However, Chen fails to expressly teach wherein each die region comprises functional circuitry located under the bump pads. Nevertheless, Rashid teaches wherein each die region (“die 12 and 14” para. 0013 FIG. 1 and 3) comprises functional circuitry (“die circuitry 28” para. 0018) located under the bump pads (“bond pads 20” para. 0018). Chen and Rashid teach scribe line regions with probing pads. The “device pads 160” in Chen are connected to the active devices in “active area 140” but Chen is silent respect to the vertical disposition of the active devices and their spatial relationship to “device pads 160”. Rashid teaches “bond pads 20” connected to “die circuitry 28” through “die conductive layers 30” formed through a “dielectric 36” (Rashid para. 0018 FIG. 3). The “dielectric 36” covers the “die circuitry 28”, such that the circuitry is protected against the outside. Also, while Chen appears to suggest that “device pads 160” and “active area 140” are spaced apart in plan view within each die regio, Rashid teaches that the circuitry can be directly underneath the “bond pads 20” (Rashid para. 0018); this enables more dense and compact packaging of the die. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that forming the “die circuitry 28” below the “bond pads 20” as in Rashid allows for the “die circuitry 28” to be isolated and reduces the die footprint. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Chen with the functional circuitry arrangement taught in Rashid. Dielectric material can cover the functional circuitry and bond pads can be formed above the circuitry, minimizing the footprint of the die. Regarding claim 2 , Chen, modified by Rashid, teaches the semiconductor device of Claim 1, wherein the bump pads are electrically connected to the functional circuitry of the die region (“device pads 160” are electrically coupled to the circuitry in “active area 140”, para. 0050). Regarding claim 3 , Chen, modified by Rashid, teaches the semiconductor device of Claim 2, wherein the functional circuitry of each die region is tested via a plurality of circuit probing needles electrically connected to external test equipment and placed on the circuit probing pads (“device pads 160” are coupled to the “active area 140” and “testing pads 170” are connected to “device pads 160” and are “arranged to receive one or more external probes for determining one or more characteristics of the one or more first active devices of the plurality of testing dies 110aa, 110ab”, para. 0054) . 07-21-aia AIA Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, modified by Rashid, as applied to claim 1 above, in view of Sakumoto et al US 5239191 A (hereinafter referred to as Sakumoto) . Chen, modified by Rashid, teaches the scribe line structure of Claim 1 but fails to teach wherein each circuit probing pad is larger than each bump pad. Nevertheless, Sakumoto teaches wherein each circuit probing pad (“testing pad 15” col 3 lines 6-7 FIG. 2) is larger than each bump pad (“pad 13” col 3 line 13). Chen, modified by Rashid, and Sakumoto teach the use of circuit probing pads in scribe line regions. Each “testing pad 15” is connected to a plurality of “pads 13” of each “chip area 12” (col 3 lines 12- 13). Because of this, “testing pad 15” acts as a common testing pad and its size can be made larger as long as it can fit in the “dicing line area 11” (col 3 lines 13-20). Furthermore, the examiner understands that a larger “testing pad 15” is easier to contact with a probe needle than a smaller testing pad since there is more area to make contact with. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that large “testing pads 15” can be used as common test pad for a plurality of the “pads 13” that is easier to contact with probing equipment. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scribe line structure taught between Chen and Rashid with the circuit probing pads taught in Sakumoto. A circuit probing pad can contact multiple bump pads and be made larger so that the bump pads can be tested by a common pad and the larger size makes it easier for probing equipment to contact the circuit probing pad . 07-21-aia AIA Claim s 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, modified by Rashid, as applied to claim 1 above, in view of Ishii US 20190164923 A1 (hereinafter referred to as Ishii) . Regarding claim 5 , Chen, modified by Rashid, teaches the semiconductor device of Claim 1 but fails to teach further comprising: a plurality of copper pillar bumps disposed on and in contact with the bump pads. Nevertheless, Ishii teaches A plurality of copper pillar bumps (“metal post 25” para. 0041 FIG. 1) disposed on and in contact with the bump pads (“electrode pads 21” para. 0041). Chen, modified by Rashid, and Ishii teach semiconductor die regions with interconnections for external devices. Ishii teaches “metal posts 25” on “electrode pads 21” that are used for external connection. A “solder ball 21” is formed on each “metal post 25” for interconnection with “wiring substrate 40” (para. 0050). Such a connection establishes a large enough gap between the devices so that sealing resin can be poured in the gap, improving the bonding strength between “semiconductor substrate 20” and “wiring substrate 40” (para. 0051). The plurality of dies in Chen can include these “metal posts 25” and “solder balls 31” so that they bond to other devices after they are singulated. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “metal posts 25” are rigid conductive structures that help establish a gap between bonded devices, such as dies. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scribe line structure taught between Chen and Rashid with the copper pillar bumps taught in Ishii. Copper pillar bumps offer a minimum standoff between bonded chips. Regarding claim 6 , Chen, modified by Rashid and Ishii, teach the semiconductor device of Claim 5, wherein the dicing path is formed on the scribe line region across the circuit probing pads ("a dicing region may include markers (e.g., dicing lines, optical alignment structures, etc.) arranged for separating the dies during a wafer dicing process", para. 0049, such that it is understood dicing is conducted along a path in the “dicing region 120”.) Regarding claim 7 , Chen, modified by Rashid and Ishii, teach the semiconductor device of Claim 6, wherein the die region, the bump pads, and the copper pillar bumps are packaged into a semiconductor chip package (After combining, the “die 110aa, 110ab, 110ba, 110bb” with “die pads 160” from Chen, each with corresponding “metal posts 25” from Ishii, can be considered a semiconductor chip package). Regarding claim 8 , Chen, modified by Rashid and Ishii, teach the semiconductor device of claim 7, wherein a diameter of the copper pillar bump is equal to or slightly less than a width of the bump pad (“electrode pads 21” remain covered during the formation of “metal posts 25” and “solder balls 31” to avoid exposure of the seed layer under “electrode pads 21, para. 0059 FIG. 4-12. From this, the examiner understands the diameter of “metal posts 25” are at least slightly greater than “electrode pads 21”.) Regarding claim 9 , Chen, modified by Rashid and Ishii, teach the semiconductor device of Claim 7, wherein the die region (“semiconductor substrate 20” in Ishii is analogous to the region containing “die 110a” in Chen, para. 0038 FIG. 2) is electrically connected to a substrate of a printed circuit board (“wiring substrate 40” para. 0050) through the one or more copper pillar bumps (metal posts 25” para. 0041) using flip-chip packaging on the die region (“semiconductor substrate 20” and “wiring substrate 40” are packaged in a flip-chip manner as seen in FIG. 2, para. 0050). Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898 Application/Control Number: 18/381,889 Page 2 Art Unit: 2898
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