DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention 1 in the reply filed on 3/9/2026 is acknowledged.
Claims 10-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/9/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 includes language at a different stage of manufacturing from the claims it depends on, rendering the claim indefinite. The claim recites “wherein a dicing process is performed on the semiconductor wafer along one or more dicing paths defined on the scribe line region, and a portion or all of each circuit probing pad is diced from the semiconductor wafer”. The claim language is directed to a stage of manufacturing after a dicing process is taken. Meanwhile, claims 1-5 are directed to an intermediate product.
Claims 7-9 are rejected based on their dependency on claim 6
Claim 8 includes language at a different stage of manufacturing from the claims it depends on, rendering the claim indefinite. The claim recites “wherein the semiconductor chip package further comprises a remaining scribe-line structure and a remaining circuit probing pad obtained after the dicing process.” The semiconductor device of claim 1 pertains to a wafer before being diced while claim 8 teaches the chips after the wafer is diced.
Claim 9 is further rejected based on its dependency on claim 8.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen te al. US 20230120504 A1 (hereinafter referred to as Chen).
Regarding claim 1, Chen teaches
A semiconductor device (“example wafer 100”, para. 0049 FIG. 1A-1C), comprising:
a plurality of die regions (“plurality of dies 110aa, 110ab, 110ba, 110bb”, para. 0049 FIG. 1B-1C), disposed on a semiconductor wafer (“semiconductor substrate 102” para. 0049);
a plurality of bump pads (“device pads 160” para. 0050), disposed on a first top surface of an edge region of each die region (“device pads 160” are disposed on an edge portion of the surface of “die 110aa”);
a plurality of circuit probing pads (“test pads 170”), disposed on a second top surface of the scribe line region (“testing pads 170” are in the “dicing region 120” on “example wafer 100”); and
a plurality of metal wires (“wiring structures 180” para. 0054), disposed on the first top surface of each die region and the second top surface of the scribe line region, and configured to electrically connect the plurality of bump pads to the corresponding circuit probing pads (“wiring structures 180” extend along the top surface of “example wafer 110” to connect “device pads 160” in the “die 110aa” to the “testing pads 170” in the “dicing region 120”, para. 0054);
wherein each die region comprises functional circuitry (each die includes an “active area 140” that includes one or more active devices, such that it is understood that the circuitry in “dies 110aa, 110ab, 110ba, 110bb, etc.” comprises functional circuitry), and the scribe line region is a non-functional region (no active devices are taught in the “dicing region 120”, such that the region may be considered non-functional after a dicing operation);
wherein a center of each circuit probing pad is disposed on a center line of the scribe line region (FIG. 1C suggests that “testing pads 170” are aligned in a substantially central area of “dicing region 120”).
Regarding claim 2, Chen teaches the semiconductor device of Claim 1, wherein the bump pads are electrically connected to the functional circuitry of the die region (“device pads 160” are electrically coupled to the circuitry in “active area 140”, para. 0050).
Regarding claim 3, Chen teaches the semiconductor device of Claim 2, wherein the functional circuitry of each die region is tested via a plurality of circuit probing needles electrically connected to external test equipment and placed on the circuit probing pads (“device pads 160” are coupled to the “active area 140” and “testing pads 170” are connected to “device pads 160” and are “arranged to receive one or more external probes for determining one or more characteristics of the one or more first active devices of the plurality of testing dies 110aa, 110ab”, para. 0054).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, in view of Sakumoto et al US 5239191 A (hereinafter referred to as Sakumoto).
Chen teaches the scribe line structure of Claim 1 but fails to teach wherein each circuit probing pad is larger than each bump pad.
Nevertheless, Sakumoto teaches wherein each circuit probing pad (“testing pad 15” col 3 lines 6-7 FIG. 2) is larger than each bump pad (“pad 13” col 3 line 13).
Chen and Sakumoto teach the use of circuit probing pads in scribe line regions. Each “testing pad 15” is connected to a plurality of “pads 13” of each “chip area 12” (col 3 lines 12- 13). Because of this, “testing pad 15” acts as a common testing pad and its size can be made larger as long as it can fit in the “dicing line area 11” (col 3 lines 13-20). Furthermore, the examiner understands that a larger “testing pad 15” is easier to contact with a probe needle than a smaller testing pad since there is more area to make contact with. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that large “testing pads 15” can be used as common test pad for a plurality of the “pads 13” that is easier to contact with probing equipment.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scribe line structure taught in Chen with the circuit probing pads taught in Sakumoto. A circuit probing pad can contact multiple bump pads and be made larger so that the bump pads can be tested by a common pad and the larger size makes it easier for probing equipment to contact the circuit probing pad.
Claims 5-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, in view of Ishii US 20190164923 A1 (hereinafter referred to as Ishii).
Regarding claim 5, Chen teaches the semiconductor device of Claim 1 but fails to teach further comprising: a plurality of copper pillar bumps disposed on the bump pads.
Nevertheless, Ishii teaches
A plurality of copper pillar bumps (“metal post 25” para. 0041 FIG. 1) disposed on the bump pads (“electrode pads 21” para. 0041).
Chen and Ishii teach semiconductor die regions with interconnections for external devices. Ishii teaches “metal posts 25” on “electrode pads 21” that are used for external connection. A “bump 30” is formed on each “metal post 25” for interconnection with “wiring substrate 40” (para. 0050). Such a connection establishes a large enough gap between the devices so that sealing resin can be poured in the gap, improving the bonding strength between “semiconductor substrate 20” and “wiring substrate 40” (para. 0051). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “metal posts 25” are rigid conductive structures that help establish a gap between bonded devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scribe line structure taught in Chen with the copper pillar bumps taught in Ishii. Copper pillar bumps offer a minimum standoff between bonded chips.
Regarding claim 6, Chen, modified by Sakumoto, teach the semiconductor device of Claim 5 but fail to teach wherein a dicing process is performed on the semiconductor wafer along one or more dicing paths defined on the scribe line region, and a portion or all of each circuit probing pad is diced from the semiconductor wafer.
Nevertheless, claim 6 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. Furthermore, the process steps pertain to a different step in manufacturing to that of claims 1-5. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed semiconductor device comprising a plurality of die regions, a plurality of bump pads, a plurality of circuit probing pads, a plurality of metal wires, and a plurality of copper pillar bumps disposed on the bump pads needs not the process of “wherein a dicing process is performed on the semiconductor wafer along one or more dicing paths defined on the scribe line region, and a portion or all of each circuit probing pad is diced from the semiconductor wafer”. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Regarding claim 7, Chen, modified by Ishii, teach the semiconductor device of Claim 6, wherein the die region, the bump pads, and the copper pillar bumps are packaged into a semiconductor chip package (After combining, the “die 110aa, 110ab, 110ba, 110bb” with “die pads 160” from Chen, each with corresponding “metal posts 25” from Ishii, can be considered a semiconductor chip package).
Regarding claim 9, Chen, modified by Ishii The semiconductor device of Claim 7,wherein the die region (“semiconductor substrate 20” in Ishii is analogous to the region containing “die 110a” in Chen, para. 0038 FIG. 2) is electrically connected to a substrate of a printed circuit board (“wiring substrate 40” para. 0050) through the one or more copper pillar bumps (metal posts 25” para. 0041) using flip-chip packaging on the die region (“semiconductor substrate 20” and “wiring substrate 40” are packaged in a flip-chip manner as seen in FIG. 2, para. 0050).
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, modified by Ishii, as applied to claim 7 above, in view of Takahashi US 20230064636 A1 (hereinafter referred to as Takahashi), in view of Katkar et al. US 20150262972 A1 (hereinafter referred to as Katkar).
Chen, modified by Ishii, teach the semiconductor device of Claim 7 but fail to teach wherein the semiconductor chip package further comprises a remaining scribe-line structure and a remaining circuit probing pad obtained after the dicing process.
Nevertheless, the “test pads 170” in “dicing region 120” in Chen are understood to be later diced in a manner similar to how Takahashi dices through “conductive pattern CP3” (Takahashi para. 0074 FIG. 3-4) and Katkar dices through “test pad 1610” (Katkar para. 0082 FIG. 16-17), where there are portions of the scribe region and probing pads that remain. Katkar suggests there is a remaining pad portion so that testing can still be done after dicing (Katkar para. 0082). However, Takahashi teaches that the possibility of testing with the conductive pattern depends on its size (Takahashi para. 0010): if the remaining portion of “conductive pattern CP3” after dicing is too small, testing may be difficult or not possible. The examiner understands this depends on the relative sizes of the pad and dicing apparatus. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that dicing along the “test pads 170” may produce a remaining portion that may be disabled for testing if is too small.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that there can be a remaining circuit probing pad portion when dicing is done along the circuit probing pads. The remaining circuit probing pad portion may be disabled for testing if it is too small to make contact with.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898