Prosecution Insights
Last updated: May 29, 2026
Application No. 18/381,907

SEMICONDUCTOR DEVICE STRUCTURE WITH LINER LAYER HAVING TAPERED SIDEWALL AND METHOD FOR PREPARING THE SAME

Non-Final OA §103
Filed
Oct 19, 2023
Examiner
MUSE, ISMAIL A
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nanya Technology Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
538 granted / 622 resolved
+18.5% vs TC avg
Moderate +8% lift
Without
With
+8.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
16 currently pending
Career history
658
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
83.1%
+43.1% vs TC avg
§102
13.0%
-27.0% vs TC avg
§112
3.3%
-36.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 622 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 5-6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yang [US PGPUB 20100301491] in view of Hsueh et al [US PGPUB 20210335663] and further in view of Cheng et al. [US PGPUB 20240038666] (hereinafter Hsueh and Cheng). Regarding claim 1, Yang teaches a semiconductor device structure, comprising: a first dielectric layer (103 or 103/105, Para 31/10); a second dielectric layer (107, Para 31) disposed over the first dielectric layer (Fig. 7E); a third dielectric layer (112, Para 10) disposed over the second dielectric layer (Fig. 7E); a spacer structure (503, Fig. 7E) disposed in the second dielectric layer (Fig. 7E); a conductive structure (709/715, Para 127/128) disposed in the third dielectric layer (Fig. 7E), penetrating through the second dielectric layer, and extending into the first dielectric layer (Fig. 7E), wherein the conductive structure is surrounded by the spacer structure (Fig. 7E); a liner layer (701, Fig. 7E) separating the conductive structure from the first dielectric layer, the second dielectric layer, and the spacer structure (Fig. 7E), wherein the liner layer has a tapered sidewall in direct contact with the first dielectric layer (Fig. 7E; i.e., directly contacting 103). Yang does not specifically disclose that the first dielectric layer is disposed over a semiconductor substrate; an inner silicide portion disposed over the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner layer; and an upper plug disposed over the inner silicide portion and the outer silicide portion. Referring to the invention of Hsueh, Hsueh teaches forming structure (Fig. 5; i.e., from layer 206a to top surface of layer 204c contacting layer 502), wherein the structure is formed on a semiconductor substrate 102 (Para 48, Fig. 5), wherein the structure further comprises forming: an inner capping portion (portion of 214 overlapping the conductive structure 212) disposed over conductive structure (Fig. 5); an outer capping portion (remaining portion of 214 not overlapping the conductive structure 212) surrounding the inner capping portion and covering layer 110/208/210 (Fig. 5); and an upper plug (506-512, Fig. 5) disposed over the inner capping portion and the outer capping portion (Fig. 5). In view of such teaching by Hsueh, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Yang comprise the teachings of Hsueh at least based on the rationale of using known technique to improve similar devices (methods, or products) to achieve predictable results (MPEP 2143), such as, providing adequate/reliable interconnection structure in a device. Regarding capping layer 214, it is noted that Hsueh discloses that capping layer 214 may comprise and/or be cobalt, ruthenium, tungsten, or the like (Para 30). Referring to the invention of Cheng teaches forming capping layer 60 to comprise a metal and wherein in certain instance, the capping layer can be a silicide of the metal capping layer (Para 23). In view of such teaching by Cheng, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the capping layer of Hsueh applied to the invention of Yang be a silicide layer at least based on the rationale of simple substitution of one known element/structure with a suitable another to obtain predictable results (MPEP 2143.I.B) –wherein a metal silicide is known to have numerous advantages over corresponding metal, regarding electrical resistivity, thermal stability, electromigration etc. Regarding claim 2, Yang teaches a semiconductor device wherein the spacer structure is in direct contact with a top surface of the first dielectric layer (Fig. 7E; i.e., a top surface of 105). Regarding claim 3, Yang teaches a semiconductor device wherein an angle between the tapered sidewall and a bottom surface of the liner layer is greater than 90 degrees (Fig. 7E). Regarding claim 5, Yang teaches a semiconductor device wherein the conductive structure further comprises: a barrier layer (709, Fig. 7E); and a metal filling portion disposed over and surrounded by the barrier layer, wherein the metal filling portion comprises copper (Cu) (Para 128). Regarding claim 6, Yang teaches a semiconductor device wherein a top width of the metal filling portion is greater than a bottom width of the metal filling portion (Fig. 7E). Regarding claim 14, the modified invention of Yang specifically in view of Hsueh, teaches a semiconductor device structure wherein the upper plug comprises tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), or a combination thereof (Para 70). In view of such teaching by Hsueh, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Yang comprise the material disclosed by Hsueh at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C). Allowable Subject Matter Claims 4, 7-13 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ISMAIL A MUSE whose telephone number is (571)272-1470. The examiner can normally be reached Monday - Friday 8:00 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571)270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Oct 19, 2023
Application Filed
Dec 22, 2025
Non-Final Rejection mailed — §103
Jan 15, 2026
Response Filed

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+8.0%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 622 resolved cases by this examiner. Grant probability derived from career allowance rate.

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