DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim(USPGPUB DOCUMENT: 2018/0261601, hereinafter Kim) in view of Huang (USPGPUB DOCUMENT: 2021/0398879, hereinafter Huang) and Kwon (USPGPUB DOCUMENT: 2016/0181143, hereinafter Kwon).
Re claim 1 Kim discloses a method for fabricating a semiconductor device, comprising: providing a substrate(100) and forming a drain(50) in the substrate(100); forming a top dielectric layer(240) on the substrate(100) and forming an opening(CH1 in Fig 9B) along the top dielectric layer(240) to expose the drain(50); conformally forming a sacrificial layer(303) in the opening(CH1 in Fig 9B); performing a first etching process[0072] to partially remove the sacrificial layer(303), resulting in a sacrificial segment(303a) on a sidewall of the opening(CH1 in Fig 9B) and exposing the drain(50); forming a cell contact bottom conductive layer(254/252) on the drain(50) and surrounded by the sacrificial segment(303a); performing a removal process to remove the sacrificial segment(303a)[0085] and form a space surrounding the cell contact bottom conductive layer(254/252); forming a cell contact top sealing layer(276a) on the cell contact bottom conductive layer(254/252) to seal the space, resulting in a first air gap(AG)[0086] surrounding the cell contact bottom conductive layer(254/252); and forming a cell contact top conductive layer(276b) on the cell contact bottom conductive layer(254/252) and surrounded by the cell contact top sealing layer(276a); wherein the cell contact bottom conductive layer(254/252), the cell contact top conductive layer(276b), and the cell contact top sealing layer(276a) configure a cell contact structure.
Kim does not disclose performing a first punch etching process[0072]; wherein at least a portion of the drain is exposed from the first air gap; wherein the first air gap is sealed by the top dielectric layer, the cell contact bottom conductive layer, and the cell contact top sealing layer.
Huang disclose performing a first punch etching process[0089]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Huang to the teachings of Kim in order to have improved quality, yield, performance, and reliability and reduced complexity [0002, Huang].
Kim and Huang does not disclose wherein at least a portion of the drain is exposed from the first air gap; wherein the first air gap is sealed by the top dielectric layer, the cell contact bottom conductive layer, and the cell contact top sealing layer.
Kwon disclose in Fig 4I wherein at least a portion of the drain(33/40) is exposed from the first air gap(39/50L); wherein the first air gap is sealed by the top dielectric layer(34B/36B/42/43)[0091,0092], the cell contact bottom conductive layer(17/28A/28B/25/49), and the cell contact top sealing layer(34B/36B/42/43)[0091,0092].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Kwon to the teachings of Kim in order to have improved reduced parasitic capacitance [0004, Kwon].
A punch etching or a etch-back process for a etching process would have been obvious because a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. KSR, see MPEP 2143.
Re claim 2 Kim, Huang and Kwon disclose the method for fabricating the semiconductor device of claim 1, wherein the removal process may comprise a vapor etchingprocess.
Re claim 3 Kim, Huang and Kwon disclose the method for fabricating the semiconductor device of claim 2, wherein the top dielectric layer(240) comprises undoped oxide.
Re claim 4 Kim, Huang and Kwon disclose the method for fabricating the semiconductor device of claim 3, wherein the sacrificial segment(303a) comprises doped oxide.
Re claim 5 Kim, Huang and Kwon disclose the method for fabricating the semiconductor device of claim 4, wherein the vapor etching process[0072] comprises employing vapor hydrogen fluoride to remove the sacrificial segment(303a)[0085].
Re claim 6 Kim, Huang and Kwon disclose the method for fabricating the semiconductor device of claim 5, wherein the cell contact bottom conductive layer(254/252) comprises polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, doped polycrystalline silicon[0060], doped polycrystalline germanium, doped polycrystalline silicon germanium, or a combination thereof.
Re claim 7 Kim, Huang and Kwon disclose the method for fabricating the semiconductor device of claim 6, wherein the cell contact top conductive layer(276b) comprises tungsten, cobalt[0030], zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, or a combination thereof.
Re claim 8 Kim, Huang and Kwon disclose the method for fabricating the semiconductor device of claim 7, wherein the cell contact top sealing layer(276a) comprises silicon oxide[0061] or silicon nitride.
Re claim 9 Kim, Huang and Kwon disclose the method for fabricating the semiconductor device of claim 8, wherein the first air gap(AG) comprises a ring-shaped cross-sectional profile in a top-view perspective(see Fig 1).
Re claim 10 Kim, Huang and Kwon disclose the method for fabricating the semiconductor device ofclaim 9, wherein the cell contact top sealing layer(276a) comprises a ring-shaped cross-sectional profile in a top-view perspective(see Fig 1).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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