Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 01/16/2026 is acknowledged.
Claims 11-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/16/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 1, the claim recites “a horizontal distance between the fuse electrode of the fuse structure and the first word line changes along a direction far away from the substrate” in lines 7-9 however it is unclear with respect to what the distance is changing for example is the change in time or with respect to a distance and what a “direction far away from the substrate” requires for the purpose of examination the claim will be interpreted to mean -- a horizontal distance between the fuse electrode of the fuse structure and the first word line changes with respect to a depth of the fuse electrode along a direction perpendicular to the substrate--.
Regarding claims 2-10, the claims are dependent on and require all the limitations of claim 1 and are therefore rejected for the same reason as claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1- is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Lin et. Al. (US 20200212049 A1 hereinafter Lin).
Regarding claim 1, Lin teaches in Figs. 3-4 with associated text a semiconductor device structure, comprising: a substrate 201; a fuse structure (210 and 201e) comprising a fuse electrode 210b disposed within the substrate (Fig. 4, [0060]); a first word line 204 electrically coupled to the fuse structure (they are part of the same circuit so that they are interpreted to be electrically coupled, Fig. 4, [0057]); and a doped region (201d and 201e) surrounding the first word line (Figs. 3-4, [0057]); wherein a horizontal distance between the fuse electrode of the fuse structure and the first word line changes along a direction far away from the substrate (distance changes due to the tapering of.210 with respect to the depth Fig. 4).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 5-7 is rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 1 and further in view of Wu et. Al. (US 20200075610 A1 hereinafter Wu).
Regarding claim 2, Lin teaches the semiconductor device structure of claim 1.
Lin does not specify a second word line electrically connected to the fuse structure.
Wu discloses in Figs. 9 with associated text a first and second word line (GR0, GR1 and associated transistors [0025]-[0026]) electrically connected to a fuse structure (GP0, OXP0 and portions of SD2 and SD3 thereunder) (Fig. 1A, [0027])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate the word lines of Lin to make a circuit similar to that taught by Wu so as to be electrically connected to the fuse structure of Lin because according to Wu compared to approaches in which a single transistor couples an anti-fuse device to a bit line through a single current path such a structure enables an increased current during read operations, thereby improving the ability to detect a programmed status of an anti-fuse device, e.g., anti-fuse device MNP0 [0048].
Regarding claim 3, Lin in view of Wu teaches the first word line is electrically connected to the second word line in parallel (Wu Fig. 1A).
Regarding claim 5, Lin in view of Wu teaches a metallization layer (WLRM0, V1 and V3 of Wu) disposed on the substrate and electrically connected (connected through the word line) to the fuse electrode of the fuse structure, wherein the metallization layer vertically overlaps the first word line (Fig. 1B, [0034]).
Regarding claim 6, Lin in view of Wu teaches the metallization layer has a first portion (portion over GR0 of Wu) extending between the first word line and second word line (-x direction) and a second portion (V1 and or V3) extending substantially orthogonal to the first portion (out of the page in Fig 1B).
Regarding claim 7, Lin in view of Wu teaches the metallization layer vertically overlaps the second word line (Wu Fig. 1B, [0034]).
Claims 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Wu as applied to claim 1 and further in view of Ha et. Al. (US 20070077713 A1 hereinafter Ha.
Regarding claim 4, Lin in view of Wu teaches the semiconductor device structure of claim 1.
Lin does not specify an air gap disposed between the first word line and the second word line however Wu teaches the fuse electrode GP0 disposed between the first word line and the second word line Wu Fig. 1A).
Ha discloses in Figs. 9 with associated text an electrode similar to the fuse electrode of Lin comprising an air gap 152 surrounded by the fuse electrode (Fig. 9, [0152]) so that by using an airgap in the fuse electrode of Lin in view of Wu an air gap would be disposed between the first word line and the second word line.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the fuse electrode of Lin in view of Wu in such a way that an air gap is surrounded by the fuse electrode because according to Ha it is possible that a void 152 may be formed in the lower channel trench 107a because the width of the lower channel trench 107a is greater than that of the upper channel trench 107b [0056] so that such a void would naturally occur in the device of Lin in view of Wu.
Claims 8-10 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Wu as applied to claim 5 above and further in view of Chang (KR 20060009417 A as cited in IDS).
Regarding claim 8, Lin in view of Wu teaches the semiconductor device structure of claim 5.
Lin does not specify the fuse electrode has a lateral surface protruded toward the first word line..
Chang discloses in Fig. 1I with associated text a fuse electrode 8 similar to that of Lin has a lateral surface protruded toward a first word line 9 (lateral surface at 4a protrudes toward 9 Fig. 1l).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to fuse the protruding fuse electrode of Chang for the fuse electrode of Lin in view of Wu because according to Chang a second junction region which forms a first junction region 11 in the surface of one side of the gate 9 and serves as a lower electrode between the gate 9 and the upper electrode 8.(12) is formed, at this time, the second junction region 12 forms an interface with the dielectric film 7,and an electric field is concentrated at the portion “A”, thereby destroying the dielectric film 7 and thus the upper electrode 8 and the second electrode a conduction layer is formed between the junction regions 12 to form an electrical fuse [2] so that such a structure would be suitable for forming a fuse in Lin in view of Wu.
Regarding claim 9, Lin in view of Wu and Chang teaches the fuse electrode has a lower surface substantially parallel to an upper surface of the substrate.
Regarding claim 10, Lin in view of Wu teaches the semiconductor device structure of claim 5.
Lin does not specify a block layer disposed under the fuse electrode of the fuse structure; and a fuse medium disposed between the block layer and the fuse electrode.
Chang discloses in Fig. 1I with associated text a block layer 6 disposed under a fuse electrode 8 of a fuse structure similar to that of Lin (Fig. 1I); and a fuse medium 7 disposed between the block layer 6 and the fuse electrode (Fig. 1I).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form block layer of Chang under the fuse electrode of the fuse structure of Lin in view of Wu because according to Chang a second junction region which forms a first junction region 11 in the surface of one side of the gate 9 and serves as a lower electrode between the gate 9 and the upper electrode 8.(12) is formed, at this time, the second junction region 12 forms an interface with the dielectric film 7,and an electric field is concentrated at the portion “A”, thereby destroying the dielectric film 7 and thus the upper electrode 8 and the second electrode a conduction layer is formed between the junction regions 12 to form an electrical fuse so that such a structure would be suitable for forming a fuse in Lin in view of Wu.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897
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